From nobody Mon Nov 25 09:35:38 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC9391EF950; Mon, 28 Oct 2024 20:26:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730147212; cv=none; b=HVWjA0q0C/Z8QdHoEGoxgw3UieNkUjNtW2XKovQAuM+QR47RoSDG2E02mCgTWHGvV0j7ceG+1oodkShf4ZJYSc2uVbTebAZQIkTKWi1cP9o6+5U79D++oCG6+XG7MLEGP8NFa0gznumFsE5XBpC535av5zN0QHVpiSvQaQmHb8w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730147212; c=relaxed/simple; bh=h2Wehl87NboyijTuuRSERBYg5ixqNkdqmXD3SKKUYoE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fO/WGpx5oFoq2cRaJ6E+xwmN1ksIATHKJgzhRG7e9pUbngsyB3vF9D+znUSs8aOgg7Qw/yTXs2h/1gsAuF6uaIziCfiv9Z2CHdKsNjAwyXjrol7b8Q6MBPaN2JDvMLKIJq92Ur5J3yRcB45TafXTb2qztEKocdIWuQdMtLdtG3E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Tspuvubf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Tspuvubf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DDC23C4CEE3; Mon, 28 Oct 2024 20:26:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730147211; bh=h2Wehl87NboyijTuuRSERBYg5ixqNkdqmXD3SKKUYoE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Tspuvubf3x10cF+HBMECbXSucjNCcaUq2vMSM+Ymsbw7FHEsOHIyFCtGbCMy0YveM 6vEWnLmCJEKbvkua/vL1GOLDLKJSgnu7GSeSKGpFYLQWAR1EDnYSnl+OZiSPZF5Wk9 ENN0uljhzz3JZt5BY9khATJ/CwZ2NF/jd7BafqbaY6Sfm+2R1+ifcxz9s3HZ30HEen Zvb7/To34xTgWAtzvA7alyykJxJZiLOlV9mI/kNroZC2gDU1ru4UlSMOWAElXIcEaw Ixe/iqrYd9avLYbNDyouNUElRy4L6l+OR2oeHler24fJd+Z5GRNs6xQuKdanEemc22 WhTl+EHDNsPNg== From: Mark Brown Date: Mon, 28 Oct 2024 20:24:18 +0000 Subject: [PATCH 9/9] kselftest/arm64: Add 2024 dpISA extensions to hwcap test Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241028-arm64-2024-dpisa-v1-9-a38d08b008a8@kernel.org> References: <20241028-arm64-2024-dpisa-v1-0-a38d08b008a8@kernel.org> In-Reply-To: <20241028-arm64-2024-dpisa-v1-0-a38d08b008a8@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=9994; i=broonie@kernel.org; h=from:subject:message-id; bh=h2Wehl87NboyijTuuRSERBYg5ixqNkdqmXD3SKKUYoE=; b=owGbwMvMwMWocq27KDak/QLjabUkhnT5zzlffMJrd59beGZZGRufyGd1YetbuXdbEmZv5gv3E9na 0/qzk9GYhYGRi0FWTJFl7bOMVenhElvnP5r/CmYQKxPIFAYuTgGYSOZK9v+umV++5hrl7Opm46ybzt tm9eP431cc6xsWJpatNpvNEBT5cYn0gsnpm5XvtpbOXMi7KYdXeWPfpp2J5/RvGm3tZZwQs3WeWdl2 8zM9m3+ZerzXzDypc/9hcxWbt/newkXWPdOZAtSnVhsw6/jd5lpe/S9tW4ac109/u/Mu6xRTudl+OT efNc4su7eBkUmNRbx5R+LyIB1bxqbPoecZp9YplF34mK7+fIlzqcPOn8YvI2sfsyUcEvfeY9b7WU6+ YOLx+XIxBoJZf+6faOrJKnIX9M1Ler009JvQJ9UzK2pLWmexxtz/P908JoDbmY05SFKBe6rS5oftMY kK4TNt83PFzMqzb0hcKXySZNYEAA== X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB We don't actually test SIGILL generation for CMPBR since the need to branch makes it a pain to generate and the SIGILL detection would be unreliable anyway. Since this should be very unusual we provide a stub function rather than supporting a missing function. The sigill functions aren't well sorted in the file so the ordering is a bit random. Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/abi/hwcap.c | 273 ++++++++++++++++++++++++++= +++- 1 file changed, 271 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/self= tests/arm64/abi/hwcap.c index f2d6007a2b983eba77a880ec7e614396a6cb1377..beb380bc09b0d07269a85a60e5d= 2977367740473 100644 --- a/tools/testing/selftests/arm64/abi/hwcap.c +++ b/tools/testing/selftests/arm64/abi/hwcap.c @@ -46,6 +46,12 @@ static void atomics_sigill(void) asm volatile(".inst 0xb82003ff" : : : ); } =20 +static void cmpbr_sigill(void) +{ + /* Not implemented, too complicated and unreliable anyway */ +} + + static void crc32_sigill(void) { /* CRC32W W0, W0, W1 */ @@ -82,6 +88,18 @@ static void f8fma_sigill(void) asm volatile(".inst 0xec0fc00"); } =20 +static void f8mm4_sigill(void) +{ + /* FMMLA V0.4SH, V0.16B, V0.16B */ + asm volatile(".inst 0x6e00ec00"); +} + +static void f8mm8_sigill(void) +{ + /* FMMLA V0.4S, V0.16B, V0.16B */ + asm volatile(".inst 0x6e80ec00"); +} + static void faminmax_sigill(void) { /* FAMIN V0.4H, V0.4H, V0.4H */ @@ -98,6 +116,12 @@ static void fpmr_sigill(void) asm volatile("mrs x0, S3_3_C4_C4_2" : : : "x0"); } =20 +static void fprcvt_sigill(void) +{ + /* FCVTAS S0, H0 */ + asm volatile(".inst 0x1efa0000"); +} + static void ilrcpc_sigill(void) { /* LDAPUR W0, [SP, #8] */ @@ -215,6 +239,42 @@ static void sme2p1_sigill(void) asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); } =20 +static void sme2p2_sigill(void) +{ + /* SMSTART SM */ + asm volatile("msr S0_3_C4_C3_3, xzr" : : : ); + + /* UXTB Z0.D, P0/Z, Z0.D */ + asm volatile(".inst 0x4c1a000" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void sme_aes_sigill(void) +{ + /* SMSTART SM */ + asm volatile("msr S0_3_C4_C3_3, xzr" : : : ); + + /* AESD z0.b, z0.b, z0.b */ + asm volatile(".inst 0x4522e400" : : : "z0"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void sme_sbitperm_sigill(void) +{ + /* SMSTART SM */ + asm volatile("msr S0_3_C4_C3_3, xzr" : : : ); + + /* BDEP Z0.B, Z0.B, Z0.B */ + asm volatile(".inst 0x4500b400" : : : "z0"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + static void smei16i32_sigill(void) { /* SMSTART */ @@ -323,13 +383,73 @@ static void smesf8dp4_sigill(void) asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); } =20 +static void smesf8mm8_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FMMLA V0.4S, V0.16B, V0.16B */ + asm volatile(".inst 0x6e80ec00"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smesf8mm4_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FMMLA V0.4SH, V0.16B, V0.16B */ + asm volatile(".inst 0x6e00ec00"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + static void smesf8fma_sigill(void) { /* SMSTART */ asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); =20 - /* FMLALB V0.8H, V0.16B, V0.16B */ - asm volatile(".inst 0xec0fc00"); + /* FMLALB Z0.8H, Z0.B, Z0.B */ + asm volatile(".inst 0x64205000"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smesfexpa_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FEXPA Z0.D, Z0.D */ + asm volatile(".inst 0x04e0b800"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smesmop4_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* SMOP4A ZA0.S, Z0.B, { Z0.B - Z1.B } */ + asm volatile(".inst 0x80108000"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smestmop_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* STMOPA ZA0.S, { Z0.H - Z1.H }, Z0.H, Z20[0] */ + asm volatile(".inst 0x80408008"); =20 /* SMSTOP */ asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); @@ -353,18 +473,42 @@ static void sve2p1_sigill(void) asm volatile(".inst 0x65000000" : : : "z0"); } =20 +static void sve2p2_sigill(void) +{ + /* NOT Z0.D, P0/Z, Z0.D */ + asm volatile(".inst 0x4cea000" : : : "z0"); +} + static void sveaes_sigill(void) { /* AESD z0.b, z0.b, z0.b */ asm volatile(".inst 0x4522e400" : : : "z0"); } =20 +static void sveaes2_sigill(void) +{ + /* AESD {Z0.B - Z1.B }, { Z0.B - Z1.B }, Z0.Q */ + asm volatile(".inst 0x4522ec00" : : : "z0"); +} + static void sveb16b16_sigill(void) { /* BFADD ZA.H[W0, 0], {Z0.H-Z1.H} */ asm volatile(".inst 0xC1E41C00" : : : ); } =20 +static void svebfscale_sigill(void) +{ + /* BFSCALE Z0.H, P0/M, Z0.H, Z0.H */ + asm volatile(".inst 0x65098000" : : : "z0"); +} + +static void svef16mm_sigill(void) +{ + /* FMMLA Z0.S, Z0.H, Z0.H */ + asm volatile(".inst 0x6420e400"); +} + static void svepmull_sigill(void) { /* PMULLB Z0.Q, Z0.D, Z0.D */ @@ -383,6 +527,12 @@ static void svesha3_sigill(void) asm volatile(".inst 0x4203800" : : : "z0"); } =20 +static void sveeltperm_sigill(void) +{ + /* COMPACT Z0.B, P0, Z0.B */ + asm volatile(".inst 0x5218000" : : : "x0"); +} + static void svesm4_sigill(void) { /* SM4E Z0.S, Z0.S, Z0.S */ @@ -458,6 +608,13 @@ static const struct hwcap_data { .cpuinfo =3D "aes", .sigill_fn =3D aes_sigill, }, + { + .name =3D "CMPBR", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_CMPBR, + .cpuinfo =3D "cmpbr", + .sigill_fn =3D cmpbr_sigill, + }, { .name =3D "CRC32", .at_hwcap =3D AT_HWCAP, @@ -512,6 +669,20 @@ static const struct hwcap_data { .cpuinfo =3D "f8fma", .sigill_fn =3D f8fma_sigill, }, + { + .name =3D "F8MM8", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_F8MM8, + .cpuinfo =3D "f8mm8", + .sigill_fn =3D f8mm8_sigill, + }, + { + .name =3D "F8MM4", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_F8MM4, + .cpuinfo =3D "f8mm4", + .sigill_fn =3D f8mm4_sigill, + }, { .name =3D "FAMINMAX", .at_hwcap =3D AT_HWCAP2, @@ -534,6 +705,13 @@ static const struct hwcap_data { .sigill_fn =3D fpmr_sigill, .sigill_reliable =3D true, }, + { + .name =3D "FPRCVT", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_FPRCVT, + .cpuinfo =3D "fprcvt", + .sigill_fn =3D fprcvt_sigill, + }, { .name =3D "JSCVT", .at_hwcap =3D AT_HWCAP, @@ -672,6 +850,20 @@ static const struct hwcap_data { .cpuinfo =3D "sme2p1", .sigill_fn =3D sme2p1_sigill, }, + { + .name =3D "SME 2.2", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SME2P2, + .cpuinfo =3D "sme2p2", + .sigill_fn =3D sme2p2_sigill, + }, + { + .name =3D "SME AES", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SME_AES, + .cpuinfo =3D "smeaes", + .sigill_fn =3D sme_aes_sigill, + }, { .name =3D "SME I16I32", .at_hwcap =3D AT_HWCAP2, @@ -721,6 +913,13 @@ static const struct hwcap_data { .cpuinfo =3D "smelutv2", .sigill_fn =3D smelutv2_sigill, }, + { + .name =3D "SME SBITPERM", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SME_SBITPERM, + .cpuinfo =3D "smesbitperm", + .sigill_fn =3D sme_sbitperm_sigill, + }, { .name =3D "SME SF8FMA", .at_hwcap =3D AT_HWCAP2, @@ -728,6 +927,20 @@ static const struct hwcap_data { .cpuinfo =3D "smesf8fma", .sigill_fn =3D smesf8fma_sigill, }, + { + .name =3D "SME SF8MM8", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SME_SF8MM8, + .cpuinfo =3D "smesf8mm8", + .sigill_fn =3D smesf8mm8_sigill, + }, + { + .name =3D "SME SF8MM4", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SME_SF8MM8, + .cpuinfo =3D "smesf8mm4", + .sigill_fn =3D smesf8mm4_sigill, + }, { .name =3D "SME SF8DP2", .at_hwcap =3D AT_HWCAP2, @@ -742,6 +955,27 @@ static const struct hwcap_data { .cpuinfo =3D "smesf8dp4", .sigill_fn =3D smesf8dp4_sigill, }, + { + .name =3D "SME SFEXPA", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SME_SFEXPA, + .cpuinfo =3D "smesfexpa", + .sigill_fn =3D smesfexpa_sigill, + }, + { + .name =3D "SME SMOP4", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SME_SMOP4, + .cpuinfo =3D "smesmop4", + .sigill_fn =3D smesmop4_sigill, + }, + { + .name =3D "SME STMOP", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SME_STMOP, + .cpuinfo =3D "smestmop", + .sigill_fn =3D smestmop_sigill, + }, { .name =3D "SVE", .at_hwcap =3D AT_HWCAP, @@ -764,6 +998,13 @@ static const struct hwcap_data { .cpuinfo =3D "sve2p1", .sigill_fn =3D sve2p1_sigill, }, + { + .name =3D "SVE 2.2", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SVE2P2, + .cpuinfo =3D "sve2p2", + .sigill_fn =3D sve2p2_sigill, + }, { .name =3D "SVE AES", .at_hwcap =3D AT_HWCAP2, @@ -771,6 +1012,34 @@ static const struct hwcap_data { .cpuinfo =3D "sveaes", .sigill_fn =3D sveaes_sigill, }, + { + .name =3D "SVE AES2", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SVE_AES2, + .cpuinfo =3D "sveaes2", + .sigill_fn =3D sveaes2_sigill, + }, + { + .name =3D "SVE BFSCALE", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SVE_BFSCALE, + .cpuinfo =3D "svebfscale", + .sigill_fn =3D svebfscale_sigill, + }, + { + .name =3D "SVE ELTPERM", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SVE_ELTPERM, + .cpuinfo =3D "sveeltperm", + .sigill_fn =3D sveeltperm_sigill, + }, + { + .name =3D "SVE F16MM", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SVE_F16MM, + .cpuinfo =3D "svef16mm", + .sigill_fn =3D svef16mm_sigill, + }, { .name =3D "SVE2 B16B16", .at_hwcap =3D AT_HWCAP2, --=20 2.39.2