From nobody Mon Nov 25 08:01:27 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A344A1E25ED; Mon, 28 Oct 2024 20:26:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730147188; cv=none; b=UdWmyuyi8Wrl9A+dgxYQUYvR0auj5z6PX5ZTruWeGOZUuKRmF27ZgOSxgtieIaSD4GRCoOHvXmZotB0vbNLlMlffF4otV2U4wUYpN6rW0bAzUjkGHRzvAgYm2PPzoBo5JYOLTYTS5/1o27D1BKXYGkwuvzIWfsqtkkA/bo35ZQc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730147188; c=relaxed/simple; bh=d5RZlEZoZQWLA36Igji31xBn/i/cyogK0e7bQd2Qjxc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BDMGRJeuDsWKImh4iyZmr9+4CnuAMpiyvA4jvKY6QaXlZOSXt/8L8zYO/SFTPCzDO2aCvfyu/D7Auw0LhJYGdmlksO2MAYhp2mCXPUUu7OlGsnJUQe6+ynfU/UG9RUJDXcQJLsbbiH6wmE2BdNmWd4+NQukB7HJW8NSEJNfx6j0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ca9O+nmc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ca9O+nmc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7D8E5C4CEE4; Mon, 28 Oct 2024 20:26:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730147187; bh=d5RZlEZoZQWLA36Igji31xBn/i/cyogK0e7bQd2Qjxc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ca9O+nmc/ULVPHICC06J102/ac23bPptAvij71woBc/CiUdXPY1jqmfSks2EyLu/p LoS16hYAFSVSg8m+bmqFH0fsyEkpBfa0n+GH6QpmZeIUXURu5kTQjPThOEdlQD2Imv XzrKZmNmKWDHAB1XO1bBfIooUH9r6j1GjfB6qTkGaB139mFAMk1UJZSixvqHWYRUeI o/ql74U9c8MYpy4TyuoAIhg2i9g+Enk79ELpXhKqzybDI/bzcnTFQZgqeByyMVxh6a ofzyoMsqm/15ZQ44vVVFWu6/Or5AOlILDQJNRa8doRxvctMITpSRHu/38bL9imYla2 hT5iMIVRqS9WQ== From: Mark Brown Date: Mon, 28 Oct 2024 20:24:10 +0000 Subject: [PATCH 1/9] arm64/sysreg: Update ID_AA64PFR2_EL1 to DDI0601 2024-09 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241028-arm64-2024-dpisa-v1-1-a38d08b008a8@kernel.org> References: <20241028-arm64-2024-dpisa-v1-0-a38d08b008a8@kernel.org> In-Reply-To: <20241028-arm64-2024-dpisa-v1-0-a38d08b008a8@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=771; i=broonie@kernel.org; h=from:subject:message-id; bh=d5RZlEZoZQWLA36Igji31xBn/i/cyogK0e7bQd2Qjxc=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnH/NmtcwIhaUHJF6vujwEbcssTw5+zAnH4nKBXEeV 7p/j+eaJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZx/zZgAKCRAk1otyXVSH0KnMB/ 44tLFchLAec/zksuwpz3Xuq+jtawdVudOA57yX0bSZwwDh1CaftQpmVtcS1++VJj+vTEsSNABNu9ZD JPEI5cbOvMO2t3paBegspl6GMFRxFO4HHaAhgnWpKOymESR5O0xNwqx3OVQNLhxpKTIo1OheeU61Vi eM+OH3NE+6Awp3naCglIlW53grpKnyfOuDHk1MsDR4vZpilHo9/eWUq68dqU8pyoloRr0PZbn4R1vN HfeBayZB6S8JzUiqkoPeMFqQqsvN0b5HafqsJYpuLZ3kNrWjdm2+hsmSVGAFaWxZ/y28S4O4bhExam BDS0THEKt/mtt9BA+lSPalvM33K9kx X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB DDI0601 2024-09 defines a new feature flags in ID_AA64PFR2_EL1 describing support for injecting UNDEF exceptions, update sysreg to include this. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 8d637ac4b7c6b9c266156b4a8518d8d64c555461..72d6ff1a9c7588dc4894ec6d673= 791fde108a857 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1010,7 +1010,12 @@ UnsignedEnum 35:32 FPMR 0b0000 NI 0b0001 IMP EndEnum -Res0 31:12 +Res0 31:20 +UnsignedEnum 19:16 UINJ + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 15:12 UnsignedEnum 11:8 MTEFAR 0b0000 NI 0b0001 IMP --=20 2.39.2 From nobody Mon Nov 25 08:01:27 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95041204022; Mon, 28 Oct 2024 20:26:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730147190; cv=none; b=AAqQ7JV2AxCO5cggxGj9vc8gvfE0TtWKZrNGoH/WcIfxrsksCUAJ1QkAmrTSoVXWIYkQ9gVDZ1hKCK8/zaclfkyBc3BHjfQ8VP824IjD8/t4vg7tUCHb+WPMw+4c+v7XiSFJ6NjwmkHH24kwptIbtzZJxJsy+35wUbnV94FBMTQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730147190; c=relaxed/simple; bh=zpkfrQGx3HEw4mQkvZcocv9aZkCal4I29KIfJ/D2G4s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PpHSrU3j3WQ2t+nG9Lr5Xyw8ja79xGhEFtcak+CmsVCStnxkU4EOr11/HNVCYbKQk3EllSq6c6q8sxplYkD19f0SEKpyDBV9h/ZZG6+mmUJct6MQwIV3ZGBcetC7erkGNDl3M5P74BulChLzDntf+7XTZ8kEPirwZBwMT3WFAZM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LVoJOtnl; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LVoJOtnl" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 930BEC4CEE7; Mon, 28 Oct 2024 20:26:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730147190; bh=zpkfrQGx3HEw4mQkvZcocv9aZkCal4I29KIfJ/D2G4s=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=LVoJOtnls23eeaY/JLQ9u58NUppI2xcVbHSx61MBQzlwCA9cvWdyqkugW21ljicTp RH5u8HEe/rDyPYo/EblJOSZGQxmDcocD5anHKnFeehpHn/l+6rF1IWo74bChmbKR0q DqCV5Tc8g7HmrzOqxD7Yeca/EX7a6nSKiDGxV59PjA4RTVSjsPToxhFG/TM/80lHpI z/vCkmAXAaEQAmKRT0MWEJjn4sOIu0v0mlXvqOfVsiT6DFYO/UKXv8/jY4bx9llwJv gOmslRVjsSxFhoE5FH/zwk7FPnV8g1/fVnuLC7gCYNDe1Tkd0vqhLNF0W82w+IsRJC H4GJjhKcNtPyA== From: Mark Brown Date: Mon, 28 Oct 2024 20:24:11 +0000 Subject: [PATCH 2/9] arm64/sysreg: Update ID_AA64ISAR3_EL1 to DDI0601 2024-09 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241028-arm64-2024-dpisa-v1-2-a38d08b008a8@kernel.org> References: <20241028-arm64-2024-dpisa-v1-0-a38d08b008a8@kernel.org> In-Reply-To: <20241028-arm64-2024-dpisa-v1-0-a38d08b008a8@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=944; i=broonie@kernel.org; h=from:subject:message-id; bh=zpkfrQGx3HEw4mQkvZcocv9aZkCal4I29KIfJ/D2G4s=; b=owGbwMvMwMWocq27KDak/QLjabUkhnT5z+lfj//cpOPFHn0oY+PzWrl9shuCzibou/z988Bh785k A/WVnYzGLAyMXAyyYoosa59lrEoPl9g6/9H8VzCDWJlApjBwcQrARLaHsv9TPs6/mcEkp99f6M+uH9 v6ftW3zZa831Yfc7JL8EpTu1CmZO2ePOeLdQGLlj5cm8apEblc5tLXtddZHBUWBEg+uu6U2JLq4Oip sDBshbhOZrvR5z8Rd/OYVe3z1JIntqpIn4g4oXH1qJSfvZ713czJNULVEe9+TQpw4d1Ypif4Iasm78 d3lluHUk4tdt7PYmY82bT0/69EJ+7omQGFHX+9zBpm/rzaN6Eks3z9ros9N4tktwT+ifWMelwvfWfh jKl8Hro+dXlMX3iNZy2/wvRTRE5mYq9WOONCtg0uoacjN0WJFn/1P87By/CO9XFLWNfxGnWF5080S7 ZW7rBJMu9KNJWeFyXd2vY5KfYvAA== X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB DDI0601 2024-09 defines several new feature flags in ID_AA64ISAR3_EL1, update our description in sysreg to reflect these. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 72d6ff1a9c7588dc4894ec6d673791fde108a857..c77343ff0901bbaee98eb76615d= c7b81a563c4b0 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1531,7 +1531,23 @@ EndEnum EndSysreg =20 Sysreg ID_AA64ISAR3_EL1 3 0 0 6 3 -Res0 63:16 +Res0 63:32 +UnsignedEnum 31:28 FPRCVT + 0b0000 NI + 0b0010 IMP +EndEnum +UnsignedEnum 27:24 LSUI + 0b0000 NI + 0b0010 IMP +EndEnum +UnsignedEnum 23:20 OCCMO + 0b0000 NI + 0b0010 IMP +EndEnum +UnsignedEnum 19:16 LSFE + 0b0000 NI + 0b0010 IMP +EndEnum UnsignedEnum 15:12 PACM 0b0000 NI 0b0001 TRIVIAL_IMP --=20 2.39.2 From nobody Mon Nov 25 08:01:27 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92C781E25F8; Mon, 28 Oct 2024 20:26:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730147193; cv=none; b=Iui26oFa3Xe2o0UOvPx2eLJ+j46lE5fJrg2OuHwrqBPH9sjkwPUdF5ErrGzxMTrW1A1LOfqBfKaTSunr2ATdE7RVZM7NDxf2nE88OE8dXuGnmM8TzTYUiGwX43jW+eoDPmiyU2f5lPnaBdS+WHVvLzlvs2tWWISrSb/tdWJBPjM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730147193; c=relaxed/simple; bh=txJPBAKW/px8wqxUeO43xJFh9Jn0eyt07T5bMMNoQs0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mp9keRDQH+SvaNiynFE3qXYI0waaGS4lrvOJrBgdyZS4TleXm03GhbGdaGjdOGvfq6wTjHQTThRBqB446GFcq7ggnVE+jVv/pTvj2l6mnJtSlWHiYAzql7kCLID1noX3H7J9PebH2KQds+Ozr4xg522DGmQtyj0XGWzdQ7ufrSU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Ztrykpt+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Ztrykpt+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 94765C4CEC3; Mon, 28 Oct 2024 20:26:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730147193; bh=txJPBAKW/px8wqxUeO43xJFh9Jn0eyt07T5bMMNoQs0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Ztrykpt+4b7wD4gyj6F+Wr6ZINzimVJUWczh+xmbnDbb55sTX5kn9+tc4qgX/jIhW klLnlzPu/Yo2GHMWMXbhh8Pp1bGKYOgl6pV8vRwHOQMeZBggY01628hCMd/i1V/GYl GVbnEdvSLoOB2zSzsimquyN4sg/WZWKMIAWFOUy70BSkKGBq2zzK5nwsRf/lm3klA1 PiJRjsOFWyeL7bqxIQXMJkrkPfrU42RdAKBlQ7L5760CuSmVViFeSPTQeYYXkocTlp lBKMYK1mq5HMq6Ev1/BRMCSXPAUq+QcVXycTCxLvWjI8su+GlR6obHnIaOStDhL9ky b2hzEssrxzG7g== From: Mark Brown Date: Mon, 28 Oct 2024 20:24:12 +0000 Subject: [PATCH 3/9] arm64/sysreg: Update ID_AA64FPFR0_EL1 to DDI0601 2024-09 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241028-arm64-2024-dpisa-v1-3-a38d08b008a8@kernel.org> References: <20241028-arm64-2024-dpisa-v1-0-a38d08b008a8@kernel.org> In-Reply-To: <20241028-arm64-2024-dpisa-v1-0-a38d08b008a8@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=766; i=broonie@kernel.org; h=from:subject:message-id; bh=txJPBAKW/px8wqxUeO43xJFh9Jn0eyt07T5bMMNoQs0=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnH/NnuV9phKJk9PYMPihoIk1sMnV7v0rwyQvWGFwr BqIRvviJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZx/zZwAKCRAk1otyXVSH0IxZB/ 9V3mOfS/3YcuhQpBI0oXyJHV9MoTvOq6YGCtMPwQs2imeiPfLoooRLEAVju+MCRFb7WxFaV6Uevp0K qu4i03F+KDohg7V5MgE2ODAMS+r9xn4fpLVXWBiIfJ1xCdDvsOd6dpmKLqAYGqODvCvk4sF/W6+S6j q7y2KTfR76DWdMXdBod6WAG/SL45Ck72Pzm9BBBggGrxw/3XSwzy5KqjqrFtqDiEAczxjU1bpZsJya z3I8KrQR6yRmJqZR7ZxJKTgmThmyaPZVXbb1HF9DVPVJYZ+JuPZrr/VZOyhNlW4ho9Ah2N+tAhogx3 Kh25R8TO5Infk8/21yO4RIoDjzP9dZ X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB DDI0601 2024-09 defines two new feature flags in ID_AA64FPFR0_EL1 describing new FP8 operations, describe them in sysreg. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index c77343ff0901bbaee98eb76615dc7b81a563c4b0..26f1350c9d2e3baf39ac3bdcc96= fc1e6deb5a5c6 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1180,7 +1180,15 @@ UnsignedEnum 28 F8DP2 0b0 NI 0b1 IMP EndEnum -Res0 27:2 +UnsignedEnum 27 F8MM8 + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 26 F8MM4 + 0b0 NI + 0b1 IMP +EndEnum +Res0 25:2 UnsignedEnum 1 F8E4M3 0b0 NI 0b1 IMP --=20 2.39.2 From nobody Mon Nov 25 08:01:27 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 955171E25F8; Mon, 28 Oct 2024 20:26:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730147197; cv=none; b=WGme/BQ+TODY7jMWX/owOC3wQVfFdHYsmv4hAy5AHeaHMgCkRzyyiQUeNuGlk3o4+KR16DLruobagavaLbPX/dsvsE+q0ViCEvaaEUvrpgWRImWOw/RptmCCGTVvsnvmx8efrCS0GYnOPCP0+NsmO5vBxnGMZWzdc2dslsTgT1Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730147197; c=relaxed/simple; bh=FN01wAAM5D8ZMfrYQkBkqRMg6r+p3qmFRREh7tSlgYo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ATFrdDo2MShW7xA39kaAYws1VuXXn/371YuE+HGMNAadvyLDWeCddOaS6hoJoJ6S23VX59pTp/AfumqQslm4o5wWLHBsyDUMaeOZpIXAiu1cokbWi9A54M0tLKIuAfCq2IN6eeCDVzN0UUvuNTpX4PvFBYiwLBeL14NfLK5wALo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=P3C0ddgp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="P3C0ddgp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 97E4EC4CEE4; Mon, 28 Oct 2024 20:26:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730147196; bh=FN01wAAM5D8ZMfrYQkBkqRMg6r+p3qmFRREh7tSlgYo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=P3C0ddgp4phz7rTiKtrn+fbmvzltuGLSD+3p+Au18P72iXatX5ce7fvsRnFjBbYqj QipLXVvqhMxyL9mFgsi4y1qU1u7xgFRKZmJaDSJezL0IFf2s5j1IHM2exEhd8mkCHz uOv5WokY6qtcIi+cfa9LMoMBaf3nU9+Bm9QcQItDxhPG1iJJwseN5Bm5zWNJZSgTkf PKmSp3T+COJUc3f4cwSdMMGvuqDAU89JrkkoTbYHO1TJlQzOPoqMPNrVyVGx4s4wsG kXplxAixT1Thq+rH2uzki76Wufh0CjMVp4rCVwXUyJlDKwuzF7ZNfDFkcoji57A0/q yeIdarDR0v6Hw== From: Mark Brown Date: Mon, 28 Oct 2024 20:24:13 +0000 Subject: [PATCH 4/9] arm64/sysreg: Update ID_AA64ZFR0_EL1 to DDI0601 2024-09 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241028-arm64-2024-dpisa-v1-4-a38d08b008a8@kernel.org> References: <20241028-arm64-2024-dpisa-v1-0-a38d08b008a8@kernel.org> In-Reply-To: <20241028-arm64-2024-dpisa-v1-0-a38d08b008a8@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=1302; i=broonie@kernel.org; h=from:subject:message-id; bh=FN01wAAM5D8ZMfrYQkBkqRMg6r+p3qmFRREh7tSlgYo=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnH/NoFqkcnBz5GKBfDodahpIRTDaaf4zSQp/88sVI r9TS7PyJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZx/zaAAKCRAk1otyXVSH0FzMB/ 96ysFmW6P71QjtffhaS+xwXkOmBCPFj+RfWbn6KXXPQ0pqf5VxBamOOlh0hjvifAHQ8DClaDeupO5H 9/qXOFxmb9tJLD8pC5OxDdCJT2tRBIzEwP9fOJW4h1kD9N5ZczGGiOYsSrScvrKqO3WUZPij2pd4ks j0n8HTPMWOlZXhtNk7OHlaFdQrvjEVjnCY1A0kzAusHYnImNGMAuXrV1/aHcGoiT8sWWBftSNo6FFr BlsTWLMYWf5sopFeNA5y/iVHffBe0QLCxCo3HfzdwghVYvbJ6HVCp23aARQfFC43L4+4I0hkvgHJHu uY1EesCMNi9sjo1Qf+JXtkFkM+jlHS X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB DDI0601 2024-09 introduces SVE 2.2 as well as a few new optional features, update sysreg to reflect the changes in ID_AA64ZFR0_EL1 enumerating them. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 26f1350c9d2e3baf39ac3bdcc96fc1e6deb5a5c6..d487c78520b97c8f96c70181e39= eccb91d6fe1af 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1040,7 +1040,10 @@ UnsignedEnum 55:52 F32MM 0b0000 NI 0b0001 IMP EndEnum -Res0 51:48 +UnsignedEnum 51:48 F16MM + 0b0000 NI + 0b0001 IMP +EndEnum UnsignedEnum 47:44 I8MM 0b0000 NI 0b0001 IMP @@ -1058,6 +1061,7 @@ Res0 31:28 UnsignedEnum 27:24 B16B16 0b0000 NI 0b0001 IMP + 0b0010 BFSCALE EndEnum UnsignedEnum 23:20 BF16 0b0000 NI @@ -1068,16 +1072,22 @@ UnsignedEnum 19:16 BitPerm 0b0000 NI 0b0001 IMP EndEnum -Res0 15:8 +UnsignedEnum 15:12 EltPerm + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 11:8 UnsignedEnum 7:4 AES 0b0000 NI 0b0001 IMP 0b0010 PMULL128 + 0b0011 AES2 EndEnum UnsignedEnum 3:0 SVEver 0b0000 IMP 0b0001 SVE2 0b0010 SVE2p1 + 0b0011 SVE2p2 EndEnum EndSysreg =20 --=20 2.39.2 From nobody Mon Nov 25 08:01:27 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B110F20400A; Mon, 28 Oct 2024 20:26:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730147199; cv=none; b=Vz2HBITskBXYp0o9PiGV0A7S4MhI2YmgxF4CF0EnCW3QNThC6vT8c/XbVAKGxRKTELol770pTiDg4NHturqo7EJE6qoPGltRvA9oyA2NL9Uye5fBXNipDaYXCyFoiVG4/DEC5qGI50iN8YCreb/POFB0Aao7XEXklzZIt4lVJrg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730147199; c=relaxed/simple; bh=7uuIvssgPmNN0rgvBR2HltfMJC/cwbms6ZSXTgQ7BIU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uCPK2PggaAtZZntZ+JpxdRH40AyLH72+gTQmL62Z2iKefbl7ajmR2QBQ03Pn9SHs/ex0U1PQUG2n6Oqw3npPH2YASXcZTagPHKpeeaklbYK9Zt93tXJqVw3u20mH+wGoPhtw9Z2eEoYG/z8HHFP6mtp5imaZALMH/5V4W0jSj4A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=l3uO/ulc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="l3uO/ulc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9BE27C4CEC3; Mon, 28 Oct 2024 20:26:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730147199; bh=7uuIvssgPmNN0rgvBR2HltfMJC/cwbms6ZSXTgQ7BIU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=l3uO/ulc3ocueXipIvwxjEj/c0ijlaZ8oAL1cZRXhMGXqldt5LMHpkebFm2iuqR2R 7lbwBHsAAPGxe/+dCexr2UqrJ5wc6L7KrxBvFHgyV0XOkcZlXtjctHrvu8u0ZEbKlY 9nloLi+6tYnF3gzNGET6LnpXD8jgenT89wgATOkpsP1Ldcn1dn7BCPodS2Ek6RgPO3 QK3teelEI8OjQCkABs26+pmK7WK0JlEFuqzYgaA8majnKgc1yDivewwr91jLB6uwYG vFSBMCUjdFAgqJQaowbwDPLjHd3Fa5VhPMUbNvbxbobkjeU9Fl3te0ddMkX+IXm54j /Ow5vr52c7vDg== From: Mark Brown Date: Mon, 28 Oct 2024 20:24:14 +0000 Subject: [PATCH 5/9] arm64/sysreg: Update ID_AA64SMFR0_EL1 to DDI0601 2024-09 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241028-arm64-2024-dpisa-v1-5-a38d08b008a8@kernel.org> References: <20241028-arm64-2024-dpisa-v1-0-a38d08b008a8@kernel.org> In-Reply-To: <20241028-arm64-2024-dpisa-v1-0-a38d08b008a8@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=1279; i=broonie@kernel.org; h=from:subject:message-id; bh=7uuIvssgPmNN0rgvBR2HltfMJC/cwbms6ZSXTgQ7BIU=; b=owGbwMvMwMWocq27KDak/QLjabUkhnT5z5mhH1wdu152/fp1M+Nmta6exZnPv89NDVWS8TbbX8uk w6XZyWjMwsDIxSArpsiy9lnGqvRwia3zH81/BTOIlQlkCgMXpwDcaD/2v+I3dtbv5FOdtKPxtczuko mWjM2LjJd7qiRpvo59mu6WXOkiEiF/YtZUx/hDe6V/ylkuOhd7ZPN0jgn2RoLusvUZ/V+YVZ7rteqI 3ZjnNpfpdEbF8y/M/ifiz3O5MfNz2CuenOaif01OcfJ5eRkxzR7fB8ZnwpW0LFmDWyK/JAst9Tu0fn 2lzGPbp2sttK4H+Wx5szDvwqF3istZNyReu/C7vu1MjFZKUaytRpO+pU0A//+bUUc0dOxf5W4TZUnz 9p3qOc0h5vsl+c+BAZuP9e6tcnj01y1dS0rnZT6f8pq0MBG+p+t1So9vju2M+XFcfLGDs1Nlx7/bL4 KWbWZgVmu17/mo0Bpgc0T8zFkA X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB DDI0601 2024-09 introduces SME 2.2 as well as a few new optional features, update sysreg to reflect the changes in ID_AA64SMFR0_EL1 enumerating them. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index d487c78520b97c8f96c70181e39eccb91d6fe1af..808bbd6d3a40a4cd652ac25d686= f11ccafc5acf3 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1105,6 +1105,7 @@ UnsignedEnum 59:56 SMEver 0b0000 SME 0b0001 SME2 0b0010 SME2p1 + 0b0011 SME2p2 0b0000 IMP EndEnum UnsignedEnum 55:52 I16I64 @@ -1169,7 +1170,36 @@ UnsignedEnum 28 SF8DP2 0b0 NI 0b1 IMP EndEnum -Res0 27:0 +UnsignedEnum 27 SF8MM8 + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 26 SF8MM4 + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 25 SBitPerm + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 24 AES + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 23 SFEXPA + 0b0 NI + 0b1 IMP +EndEnum +Res0 22:17 +UnsignedEnum 16 STMOP + 0b0 NI + 0b1 IMP +EndEnum +Res0 15:1 +UnsignedEnum 0 SMOP4 + 0b0 NI + 0b1 IMP +EndEnum EndSysreg =20 Sysreg ID_AA64FPFR0_EL1 3 0 0 4 7 --=20 2.39.2 From nobody Mon Nov 25 08:01:27 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A917D204940; Mon, 28 Oct 2024 20:26:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730147202; cv=none; b=SoFdIg4INcfEMvzyw3mSu/tdsY4K6yUfsFUxZs7AFiu6wwpd24ImV6zfQabipTY4OM7PJASjRsJpzcKxC5yqwL2budgverv8nP5tbNPkGzFVeQu/I2yZFA+o8d/gF52+bHW1RbigoZ0iOkgstEYsF1H8lVWmnRk5qoAnRrUe8p0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730147202; c=relaxed/simple; bh=mdF9l8XoMfCClmS8E8sWltwQ5YchWlsCeLs+M166hTU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jEdJa+8fXl4+2ZXKLNoeVmLEz1HhPgbE/uyzk2mKh4kmLJihfk5Y91wdHTsh6gqlnubrNh44KgJqs0gfP4AQdAaAbGRuMtSykGGJLnMIS9OXc/VdtJYisjMMcCxlEgBlRd+IiM43XFUZAlS6uiYsmCFy0gj04mkY+ZzVDWnLkgY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NEh+k01m; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NEh+k01m" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A217DC4CEE8; Mon, 28 Oct 2024 20:26:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730147202; bh=mdF9l8XoMfCClmS8E8sWltwQ5YchWlsCeLs+M166hTU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=NEh+k01mKNAjZgDUCPOTdCquL2nTEfy+ZnLWxFDAsaCwzT+uceoQMdemFHfflgUfd GwJrX3IvpRTWcdXJS0rAmxVWgcjFBSTDjJWsBYLKruTDveZhROgOvRQAnBlqhuufZX IOtbp7LHObELb1OhoCOflwbNDXd5F/yWFJ6CZqA+er57UH92+7a4cLlEUo9W4bN3cS wBYJoTQcGt1t0LYNPHixT1d1h7h1xsKOo/t18Wxrv7HtpJc1n3wnf6zRK5j8l+tnbb n+I5y9AH3Og2Eyohj6nDm8zOnTSSlguVLlb29LnSbd9rEFG6q2O4wCMVQjdUS+Otte 10OylvTyc8eJQ== From: Mark Brown Date: Mon, 28 Oct 2024 20:24:15 +0000 Subject: [PATCH 6/9] arm64/sysreg: Update ID_AA64ISAR2_EL1 to DDI0601 2024-09 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241028-arm64-2024-dpisa-v1-6-a38d08b008a8@kernel.org> References: <20241028-arm64-2024-dpisa-v1-0-a38d08b008a8@kernel.org> In-Reply-To: <20241028-arm64-2024-dpisa-v1-0-a38d08b008a8@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=827; i=broonie@kernel.org; h=from:subject:message-id; bh=mdF9l8XoMfCClmS8E8sWltwQ5YchWlsCeLs+M166hTU=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnH/Nq5LJBcitKLDEOlNZDCWc/2DHd32O0aS1++eFY SxSju/2JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZx/zagAKCRAk1otyXVSH0GBsB/ oD272FS08Rd91ruHA5rXXew1m9uEA/IO7IIc1f+0kZxT1TSgFZ4W5bZuTvHf9SUO+0bN/hKAtOH/HT 1Kd/q5uus5t9et0SXPzQ8NE1SBpQtDjKVfICT78BR6O9m0RnsDGVZKq1JrBIZfEiXgp28xK+vFEqVH MGs1s64zzM2bVKGSGAaQuct8DgBJKs1vLW6T7Nva4kAxB1uofJ8AqpmWaeXT1HqK2f2mBTCC76NZ1u vy6qflr5j+k1GTyA9jgqkbIZle6nq3wwX/gPOlx0ns++b88Ue4INdFevmegh4/zEv4q2S7z3JQgiwP 8j7unaCUhq5XOi+xI7vpDk+/VsO98+ X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB DDI0601 2024-09 introduces new features which are enumerated via ID_AA64ISAR2_EL1, update the sysreg file to reflect these updates. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 808bbd6d3a40a4cd652ac25d686f11ccafc5acf3..c8cc092fc0f63f91c7e87d67926= 6a1f8a38176b0 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1521,12 +1521,16 @@ EndEnum UnsignedEnum 55:52 CSSC 0b0000 NI 0b0001 IMP + 0b0010 CMPBR EndEnum UnsignedEnum 51:48 RPRFM 0b0000 NI 0b0001 IMP EndEnum -Res0 47:44 +UnsignedEnum 47:44 PCDPHINT + 0b0000 NI + 0b0001 IMP +EndEnum UnsignedEnum 43:40 PRFMSLC 0b0000 NI 0b0001 IMP --=20 2.39.2 From nobody Mon Nov 25 08:01:27 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D69C20495B; Mon, 28 Oct 2024 20:26:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730147205; cv=none; b=tSTajeQpQrOcnBOoJJ7oE3CPKzlTNIUabIhNzXP5AYHjUMcrkTCaVQbjnlfd2ALIQRzk9hXNeHHvQ3q5KgAZRho5LhCIWty8gKJGYjfcwJCxqCTzwn2puJfmRIO9v7iKMTVLFMcdwo5qkPh5CSIs0A7VYcn10ZsJYWH4W9kTZqc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730147205; c=relaxed/simple; bh=G7tcq3Seo5cpWXELSNXBCez29eWf6wZuSlfxRLSzlko=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SgQe1zYORtI72M+/h4nhLvGxYnzjRKPmwZNO4ERh7P2dO1jHwagNsou/orpmlbnaoqwZ4BwRWG/Khii6xwC75GF8+DTzUHZsMpn8vv7Nf6vDqTCnD0P2fUzxJmqZeYrN9PH/Pc7NypIljRr+JvS+y0jrm25uEIDnpXWr+fTVcd0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nNMT5tQa; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nNMT5tQa" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A6A90C4CEE3; Mon, 28 Oct 2024 20:26:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730147205; bh=G7tcq3Seo5cpWXELSNXBCez29eWf6wZuSlfxRLSzlko=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=nNMT5tQawyH5AAsYYN2SLVMMSlxYwOcR41Z99TwYLIa13AmWMZNVovXtt6giBUEro tIDhn75bLhoeZC7UADNv1kS8q9KIvsVp7zuGqOGpU4Y0UQfrWIc7l72v/nu0zkwTxX 2Wrvh/+2buH/B8f/IQtLxcf7b0wUS1LaFcjGqQUTjVnyoKelkp7Lt6vpSG64ZSYYRN Kq5r69y0zXJQMOafhIFqvO+6obVci75PZRcbD49mSIQEkkEkyQ07/6Ge2H1icvC2np /aP6eXfgbxXwrCL5ukL6eWN5vuH+lIG1fWFEK2BN2eG87aXyx3Su33vY2e3sPz819i 2vD/YOWcTvwww== From: Mark Brown Date: Mon, 28 Oct 2024 20:24:16 +0000 Subject: [PATCH 7/9] arm64/hwcap: Describe 2024 dpISA extensions to userspace Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241028-arm64-2024-dpisa-v1-7-a38d08b008a8@kernel.org> References: <20241028-arm64-2024-dpisa-v1-0-a38d08b008a8@kernel.org> In-Reply-To: <20241028-arm64-2024-dpisa-v1-0-a38d08b008a8@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=14318; i=broonie@kernel.org; h=from:subject:message-id; bh=G7tcq3Seo5cpWXELSNXBCez29eWf6wZuSlfxRLSzlko=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnH/NqJ5vjIbjIWCK71H9LX1oaJEMDmh3F45BPmw7i ACR9F3GJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZx/zagAKCRAk1otyXVSH0C/bB/ 0XSo2aC7lWO17804YLBo+MHdRHmZY7ZXMHAe2ZN4vm5aHhoS/uibiL/tXYGdLB6VFX1h806hvi39fa VYx0//T5AwOfZMWDqsh8iI4/VyE0BggHJUNXRwx8G5IURslEflVHUlnG5etrM4T6ykeZUUozSMLFZI lffOc3Ed9DnVPMG2/whPHJkxOz4sCurBFvuw4E9O3Vr8iydysGxwazvybb7b98nLe8/Rd2jJnn9oP0 u576D3dE6UZpuFZ6uyRoCBCBllrjdJzTk9H4Va4LUfEz4PirW+VETl83UcbAWc+vEAS5mgSUMroni5 27DJr7dM3ZOBIwwIm2e12+yJGcRUNU X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The 2024 dpISA introduces a number of architecture features all of which only add new instructions so only require the addition of hwcaps and ID register visibility. Signed-off-by: Mark Brown --- Documentation/arch/arm64/elf_hwcaps.rst | 51 +++++++++++++++++++++++++++++= ++++ arch/arm64/include/asm/hwcap.h | 17 +++++++++++ arch/arm64/include/uapi/asm/hwcap.h | 17 +++++++++++ arch/arm64/kernel/cpufeature.c | 35 ++++++++++++++++++++++ arch/arm64/kernel/cpuinfo.c | 17 +++++++++++ 5 files changed, 137 insertions(+) diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/a= rm64/elf_hwcaps.rst index 694f67fa07d196816b1292e896ebe6a1b599c125..a364bb04cc797e2597d31798540= ccd3a2e6ddd71 100644 --- a/Documentation/arch/arm64/elf_hwcaps.rst +++ b/Documentation/arch/arm64/elf_hwcaps.rst @@ -170,6 +170,57 @@ HWCAP_PACG ID_AA64ISAR1_EL1.GPI =3D=3D 0b0001, as described by Documentation/arch/arm64/pointer-authentication.rst. =20 +HWCAP_CMPBR + Functionality implied by ID_AA64ISAR2_EL1.CSSC =3D=3D 0b0010. + +HWCAP_FPRCVT + Functionality implied by ID_AA64ISAR3_EL1.FPRCVT =3D=3D 0b0001. + +HWCAP_F8MM8 + Functionality implied by ID_AA64FPFR0_EL1.F8MM8 =3D=3D 0b0001. + +HWCAP_F8MM4 + Functionality implied by ID_AA64FPFR0_EL1.F8MM4 =3D=3D 0b0001. + +HWCAP_SVE_F16MM + Functionality implied by ID_AA64ZFR0_EL1.F16MM =3D=3D 0b0001. + +HWCAP_SVE_ELTPERM + Functionality implied by ID_AA64ZFR0_EL1.ELTPERM =3D=3D 0b0001. + +HWCAP_SVE_AES2 + Functionality implied by ID_AA64ZFR0_EL1.AES =3D=3D 0b0011. + +HWCAP_SVE_BFSCALE + Functionality implied by ID_AA64ZFR0_EL1.B16B16 =3D=3D 0b0010. + +HWCAP_SVE2P2 + Functionality implied by ID_AA64ZFR0_EL1.SVEver =3D=3D 0b0011. + +HWCAP_SME2P2 + Functionality implied by ID_AA64SMFR0_EL1.SMEver =3D=3D 0b0011. + +HWCAP_SME_SF8MM8 + Functionality implied by ID_AA64SMFR0_EL1.SF8MM8 =3D=3D 0b1. + +HWCAP_SME_SF8MM4 + Functionality implied by ID_AA64SMFR0_EL1.SF8MM4 =3D=3D 0b1. + +HWCAP_SME_SBITPERM + Functionality implied by ID_AA64SMFR0_EL1.SBitPerm =3D=3D 0b1. + +HWCAP_SME_AES + Functionality implied by ID_AA64SMFR0_EL1.AES =3D=3D 0b1. + +HWCAP_SME_SFEXPA + Functionality implied by ID_AA64SMFR0_EL1.SFEXPA =3D=3D 0b1. + +HWCAP_SME_STMOP + Functionality implied by ID_AA64SMFR0_EL1.STMOP =3D=3D 0b1. + +HWCAP_SME_SMOP4 + Functionality implied by ID_AA64SMFR0_EL1.SMOP4 =3D=3D 0b1. + HWCAP2_DCPODP Functionality implied by ID_AA64ISAR1_EL1.DPB =3D=3D 0b0010. =20 diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index a775adddecf25633e87d58fb9ac9e6293beac1b3..aad44880c31d4ddb1691a22946e= d492456ab6cd6 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -92,6 +92,23 @@ #define KERNEL_HWCAP_SB __khwcap_feature(SB) #define KERNEL_HWCAP_PACA __khwcap_feature(PACA) #define KERNEL_HWCAP_PACG __khwcap_feature(PACG) +#define KERNEL_HWCAP_CMPBR __khwcap_feature(CMPBR) +#define KERNEL_HWCAP_FPRCVT __khwcap_feature(FPRCVT) +#define KERNEL_HWCAP_F8MM8 __khwcap_feature(F8MM8) +#define KERNEL_HWCAP_F8MM4 __khwcap_feature(F8MM4) +#define KERNEL_HWCAP_SVE_F16MM __khwcap_feature(SVE_F16MM) +#define KERNEL_HWCAP_SVE_ELTPERM __khwcap_feature(SVE_ELTPERM) +#define KERNEL_HWCAP_SVE_AES2 __khwcap_feature(SVE_AES2) +#define KERNEL_HWCAP_SVE_BFSCALE __khwcap_feature(SVE_BFSCALE) +#define KERNEL_HWCAP_SVE2P2 __khwcap_feature(SVE2P2) +#define KERNEL_HWCAP_SME2P2 __khwcap_feature(SME2P2) +#define KERNEL_HWCAP_SME_SF8MM8 __khwcap_feature(SME_SF8MM8) +#define KERNEL_HWCAP_SME_SF8MM4 __khwcap_feature(SME_SF8MM4) +#define KERNEL_HWCAP_SME_SBITPERM __khwcap_feature(SME_SBITPERM) +#define KERNEL_HWCAP_SME_AES __khwcap_feature(SME_AES) +#define KERNEL_HWCAP_SME_SFEXPA __khwcap_feature(SME_SFEXPA) +#define KERNEL_HWCAP_SME_STMOP __khwcap_feature(SME_STMOP) +#define KERNEL_HWCAP_SME_SMOP4 __khwcap_feature(SME_SMOP4) =20 #define __khwcap2_feature(x) (const_ilog2(HWCAP2_ ## x) + 64) #define KERNEL_HWCAP_DCPODP __khwcap2_feature(DCPODP) diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/= asm/hwcap.h index 055381b2c61595361c2d57d38be936c2dfeaa195..6720c7b6cfa4df818b088b858b1= bffe084dd85f3 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -55,6 +55,23 @@ #define HWCAP_SB (1 << 29) #define HWCAP_PACA (1 << 30) #define HWCAP_PACG (1UL << 31) +#define HWCAP_CMPBR (1UL << 33) +#define HWCAP_FPRCVT (1UL << 34) +#define HWCAP_F8MM8 (1UL << 35) +#define HWCAP_F8MM4 (1UL << 36) +#define HWCAP_SVE_F16MM (1UL << 37) +#define HWCAP_SVE_ELTPERM (1UL << 38) +#define HWCAP_SVE_AES2 (1UL << 39) +#define HWCAP_SVE_BFSCALE (1UL << 40) +#define HWCAP_SVE2P2 (1UL << 41) +#define HWCAP_SME2P2 (1UL << 42) +#define HWCAP_SME_SF8MM8 (1UL << 43) +#define HWCAP_SME_SF8MM4 (1UL << 44) +#define HWCAP_SME_SBITPERM (1UL << 45) +#define HWCAP_SME_AES (1UL << 46) +#define HWCAP_SME_SFEXPA (1UL << 47) +#define HWCAP_SME_STMOP (1UL << 48) +#define HWCAP_SME_SMOP4 (1UL << 49) =20 /* * HWCAP2 flags - for AT_HWCAP2 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 718728a85430fad5151b73fa213a510efac3f834..fc4acd62e853dfc9793dcf0afac= 52d7dfed78519 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -266,6 +266,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = =3D { }; =20 static const struct arm64_ftr_bits ftr_id_aa64isar3[] =3D { + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_E= L1_FPRCVT_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_E= L1_FAMINMAX_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -313,6 +314,8 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = =3D { FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F16MM_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), @@ -325,6 +328,8 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = =3D { FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_EltPerm_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), @@ -369,6 +374,20 @@ static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = =3D { FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8MM8_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8MM4_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SBitPerm_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_AES_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SFEXPA_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_STMOP_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMOP4_SHIFT, 1, 0), ARM64_FTR_END, }; =20 @@ -377,6 +396,8 @@ static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = =3D { ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA= _SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4= _SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2= _SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM8= _SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM4= _SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M= 3_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M= 2_SHIFT, 1, 0), ARM64_FTR_END, @@ -2992,12 +3013,15 @@ static const struct arm64_cpu_capabilities arm64_el= f_hwcaps[] =3D { HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), #ifdef CONFIG_ARM64_SVE HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), + HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2p2, CAP_HWCAP, KERNEL_HWCAP_SVE2P2= ), HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1= ), HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), HWCAP_CAP(ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), HWCAP_CAP(ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMUL= L), + HWCAP_CAP(ID_AA64ZFR0_EL1, AES, AES2, CAP_HWCAP, KERNEL_HWCAP_SVE_AES2), HWCAP_CAP(ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPE= RM), HWCAP_CAP(ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B1= 6), + HWCAP_CAP(ID_AA64ZFR0_EL1, B16B16, BFSCALE, CAP_HWCAP, KERNEL_HWCAP_SVE_B= FSCALE), HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16= ), HWCAP_CAP(ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), @@ -3005,6 +3029,8 @@ static const struct arm64_cpu_capabilities arm64_elf_= hwcaps[] =3D { HWCAP_CAP(ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), HWCAP_CAP(ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), HWCAP_CAP(ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), + HWCAP_CAP(ID_AA64ZFR0_EL1, F16MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_F16MM), + HWCAP_CAP(ID_AA64ZFR0_EL1, EltPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_ELTP= ERM), #endif HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), #ifdef CONFIG_ARM64_BTI @@ -3021,6 +3047,7 @@ static const struct arm64_cpu_capabilities arm64_elf_= hwcaps[] =3D { HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), + HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, CMPBR, CAP_HWCAP, KERNEL_HWCAP_CMPBR), HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), @@ -3030,6 +3057,7 @@ static const struct arm64_cpu_capabilities arm64_elf_= hwcaps[] =3D { HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), HWCAP_CAP(ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2= ), + HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p2, CAP_HWCAP, KERNEL_HWCAP_SME2P= 2), HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P= 1), HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I= 64), @@ -3047,6 +3075,13 @@ static const struct arm64_cpu_capabilities arm64_elf= _hwcaps[] =3D { HWCAP_CAP(ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8F= MA), HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8D= P4), HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8D= P2), + HWCAP_CAP(ID_AA64SMFR0_EL1, SF8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8M= M8), + HWCAP_CAP(ID_AA64SMFR0_EL1, SF8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8M= M4), + HWCAP_CAP(ID_AA64SMFR0_EL1, SBitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SB= ITPERM), + HWCAP_CAP(ID_AA64SMFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_AES), + HWCAP_CAP(ID_AA64SMFR0_EL1, SFEXPA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SFEX= PA), + HWCAP_CAP(ID_AA64SMFR0_EL1, STMOP, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_STMOP= ), + HWCAP_CAP(ID_AA64SMFR0_EL1, SMOP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SMOP4= ), #endif /* CONFIG_ARM64_SME */ HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 44718d0482b3b43175a1673ccbebc70cf16ddcb2..d2e4f1a861e59d73bb77a06b030= c4b51a8542db6 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -144,6 +144,23 @@ static const char *const hwcap_str[] =3D { [KERNEL_HWCAP_SME_SF8DP4] =3D "smesf8dp4", [KERNEL_HWCAP_SME_SF8DP2] =3D "smesf8dp2", [KERNEL_HWCAP_POE] =3D "poe", + [KERNEL_HWCAP_CMPBR] =3D "cmpbr", + [KERNEL_HWCAP_FPRCVT] =3D "fprcvt", + [KERNEL_HWCAP_F8MM8] =3D "f8mm8", + [KERNEL_HWCAP_F8MM4] =3D "f8mm4", + [KERNEL_HWCAP_SVE_F16MM] =3D "svef16mm", + [KERNEL_HWCAP_SVE_ELTPERM] =3D "sveeltperm", + [KERNEL_HWCAP_SVE_AES2] =3D "sveaes2", + [KERNEL_HWCAP_SVE_BFSCALE] =3D "svebfscale", + [KERNEL_HWCAP_SVE2P2] =3D "sve2p2", + [KERNEL_HWCAP_SME2P2] =3D "sme2p2", + [KERNEL_HWCAP_SME_SF8MM8] =3D "smesf8mm8", + [KERNEL_HWCAP_SME_SF8MM4] =3D "smesf8mm4", + [KERNEL_HWCAP_SME_SBITPERM] =3D "smesbitperm", + [KERNEL_HWCAP_SME_AES] =3D "smeaes", + [KERNEL_HWCAP_SME_SFEXPA] =3D "smesfexpa", + [KERNEL_HWCAP_SME_STMOP] =3D "smestmop", + [KERNEL_HWCAP_SME_SMOP4] =3D "smesmop4", }; =20 #ifdef CONFIG_COMPAT --=20 2.39.2 From nobody Mon Nov 25 08:01:27 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client 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extensions in ID_AA64ISAR3_EL1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241028-arm64-2024-dpisa-v1-8-a38d08b008a8@kernel.org> References: <20241028-arm64-2024-dpisa-v1-0-a38d08b008a8@kernel.org> In-Reply-To: <20241028-arm64-2024-dpisa-v1-0-a38d08b008a8@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=975; i=broonie@kernel.org; h=from:subject:message-id; bh=2mKXsQoc2fyKgSSWiRx7xITP+IRuxdOT5z6VLLnJRWs=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnH/NrEBfq3hDnWISMfuy4nvcRlrxy6aWqNbzOnn1T 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Expose FPRCVT and FAMINMAX, two simple instruction only extensions to guests. Signed-off-by: Mark Brown --- arch/arm64/kvm/sys_regs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index dad88e31f9537fe02e28b117d6a740f15572e0ba..ab348c314d7963437e1876d4411= 69f3ef4eff095 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2409,7 +2409,8 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 | ID_AA64ISAR2_EL1_APA3 | ID_AA64ISAR2_EL1_GPA3)), - ID_UNALLOCATED(6,3), + ID_WRITABLE(ID_AA64ISAR3_EL1, (ID_AA64ISAR3_EL1_FPRCVT | + ID_AA64ISAR3_EL1_FAMINMAX)), ID_UNALLOCATED(6,4), ID_UNALLOCATED(6,5), ID_UNALLOCATED(6,6), --=20 2.39.2 From nobody Mon Nov 25 08:01:27 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC9391EF950; Mon, 28 Oct 2024 20:26:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730147212; cv=none; b=HVWjA0q0C/Z8QdHoEGoxgw3UieNkUjNtW2XKovQAuM+QR47RoSDG2E02mCgTWHGvV0j7ceG+1oodkShf4ZJYSc2uVbTebAZQIkTKWi1cP9o6+5U79D++oCG6+XG7MLEGP8NFa0gznumFsE5XBpC535av5zN0QHVpiSvQaQmHb8w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730147212; c=relaxed/simple; bh=h2Wehl87NboyijTuuRSERBYg5ixqNkdqmXD3SKKUYoE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fO/WGpx5oFoq2cRaJ6E+xwmN1ksIATHKJgzhRG7e9pUbngsyB3vF9D+znUSs8aOgg7Qw/yTXs2h/1gsAuF6uaIziCfiv9Z2CHdKsNjAwyXjrol7b8Q6MBPaN2JDvMLKIJq92Ur5J3yRcB45TafXTb2qztEKocdIWuQdMtLdtG3E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Tspuvubf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Tspuvubf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DDC23C4CEE3; Mon, 28 Oct 2024 20:26:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730147211; bh=h2Wehl87NboyijTuuRSERBYg5ixqNkdqmXD3SKKUYoE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Tspuvubf3x10cF+HBMECbXSucjNCcaUq2vMSM+Ymsbw7FHEsOHIyFCtGbCMy0YveM 6vEWnLmCJEKbvkua/vL1GOLDLKJSgnu7GSeSKGpFYLQWAR1EDnYSnl+OZiSPZF5Wk9 ENN0uljhzz3JZt5BY9khATJ/CwZ2NF/jd7BafqbaY6Sfm+2R1+ifcxz9s3HZ30HEen Zvb7/To34xTgWAtzvA7alyykJxJZiLOlV9mI/kNroZC2gDU1ru4UlSMOWAElXIcEaw Ixe/iqrYd9avLYbNDyouNUElRy4L6l+OR2oeHler24fJd+Z5GRNs6xQuKdanEemc22 WhTl+EHDNsPNg== From: Mark Brown Date: Mon, 28 Oct 2024 20:24:18 +0000 Subject: [PATCH 9/9] kselftest/arm64: Add 2024 dpISA extensions to hwcap test Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241028-arm64-2024-dpisa-v1-9-a38d08b008a8@kernel.org> References: <20241028-arm64-2024-dpisa-v1-0-a38d08b008a8@kernel.org> In-Reply-To: <20241028-arm64-2024-dpisa-v1-0-a38d08b008a8@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=9994; i=broonie@kernel.org; h=from:subject:message-id; bh=h2Wehl87NboyijTuuRSERBYg5ixqNkdqmXD3SKKUYoE=; b=owGbwMvMwMWocq27KDak/QLjabUkhnT5zzlffMJrd59beGZZGRufyGd1YetbuXdbEmZv5gv3E9na 0/qzk9GYhYGRi0FWTJFl7bOMVenhElvnP5r/CmYQKxPIFAYuTgGYSOZK9v+umV++5hrl7Opm46ybzt tm9eP431cc6xsWJpatNpvNEBT5cYn0gsnpm5XvtpbOXMi7KYdXeWPfpp2J5/RvGm3tZZwQs3WeWdl2 8zM9m3+ZerzXzDypc/9hcxWbt/newkXWPdOZAtSnVhsw6/jd5lpe/S9tW4ac109/u/Mu6xRTudl+OT efNc4su7eBkUmNRbx5R+LyIB1bxqbPoecZp9YplF34mK7+fIlzqcPOn8YvI2sfsyUcEvfeY9b7WU6+ YOLx+XIxBoJZf+6faOrJKnIX9M1Ler009JvQJ9UzK2pLWmexxtz/P908JoDbmY05SFKBe6rS5oftMY kK4TNt83PFzMqzb0hcKXySZNYEAA== X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB We don't actually test SIGILL generation for CMPBR since the need to branch makes it a pain to generate and the SIGILL detection would be unreliable anyway. Since this should be very unusual we provide a stub function rather than supporting a missing function. The sigill functions aren't well sorted in the file so the ordering is a bit random. Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/abi/hwcap.c | 273 ++++++++++++++++++++++++++= +++- 1 file changed, 271 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/self= tests/arm64/abi/hwcap.c index f2d6007a2b983eba77a880ec7e614396a6cb1377..beb380bc09b0d07269a85a60e5d= 2977367740473 100644 --- a/tools/testing/selftests/arm64/abi/hwcap.c +++ b/tools/testing/selftests/arm64/abi/hwcap.c @@ -46,6 +46,12 @@ static void atomics_sigill(void) asm volatile(".inst 0xb82003ff" : : : ); } =20 +static void cmpbr_sigill(void) +{ + /* Not implemented, too complicated and unreliable anyway */ +} + + static void crc32_sigill(void) { /* CRC32W W0, W0, W1 */ @@ -82,6 +88,18 @@ static void f8fma_sigill(void) asm volatile(".inst 0xec0fc00"); } =20 +static void f8mm4_sigill(void) +{ + /* FMMLA V0.4SH, V0.16B, V0.16B */ + asm volatile(".inst 0x6e00ec00"); +} + +static void f8mm8_sigill(void) +{ + /* FMMLA V0.4S, V0.16B, V0.16B */ + asm volatile(".inst 0x6e80ec00"); +} + static void faminmax_sigill(void) { /* FAMIN V0.4H, V0.4H, V0.4H */ @@ -98,6 +116,12 @@ static void fpmr_sigill(void) asm volatile("mrs x0, S3_3_C4_C4_2" : : : "x0"); } =20 +static void fprcvt_sigill(void) +{ + /* FCVTAS S0, H0 */ + asm volatile(".inst 0x1efa0000"); +} + static void ilrcpc_sigill(void) { /* LDAPUR W0, [SP, #8] */ @@ -215,6 +239,42 @@ static void sme2p1_sigill(void) asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); } =20 +static void sme2p2_sigill(void) +{ + /* SMSTART SM */ + asm volatile("msr S0_3_C4_C3_3, xzr" : : : ); + + /* UXTB Z0.D, P0/Z, Z0.D */ + asm volatile(".inst 0x4c1a000" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void sme_aes_sigill(void) +{ + /* SMSTART SM */ + asm volatile("msr S0_3_C4_C3_3, xzr" : : : ); + + /* AESD z0.b, z0.b, z0.b */ + asm volatile(".inst 0x4522e400" : : : "z0"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void sme_sbitperm_sigill(void) +{ + /* SMSTART SM */ + asm volatile("msr S0_3_C4_C3_3, xzr" : : : ); + + /* BDEP Z0.B, Z0.B, Z0.B */ + asm volatile(".inst 0x4500b400" : : : "z0"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + static void smei16i32_sigill(void) { /* SMSTART */ @@ -323,13 +383,73 @@ static void smesf8dp4_sigill(void) asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); } =20 +static void smesf8mm8_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FMMLA V0.4S, V0.16B, V0.16B */ + asm volatile(".inst 0x6e80ec00"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smesf8mm4_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FMMLA V0.4SH, V0.16B, V0.16B */ + asm volatile(".inst 0x6e00ec00"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + static void smesf8fma_sigill(void) { /* SMSTART */ asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); =20 - /* FMLALB V0.8H, V0.16B, V0.16B */ - asm volatile(".inst 0xec0fc00"); + /* FMLALB Z0.8H, Z0.B, Z0.B */ + asm volatile(".inst 0x64205000"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smesfexpa_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FEXPA Z0.D, Z0.D */ + asm volatile(".inst 0x04e0b800"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smesmop4_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* SMOP4A ZA0.S, Z0.B, { Z0.B - Z1.B } */ + asm volatile(".inst 0x80108000"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smestmop_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* STMOPA ZA0.S, { Z0.H - Z1.H }, Z0.H, Z20[0] */ + asm volatile(".inst 0x80408008"); =20 /* SMSTOP */ asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); @@ -353,18 +473,42 @@ static void sve2p1_sigill(void) asm volatile(".inst 0x65000000" : : : "z0"); } =20 +static void sve2p2_sigill(void) +{ + /* NOT Z0.D, P0/Z, Z0.D */ + asm volatile(".inst 0x4cea000" : : : "z0"); +} + static void sveaes_sigill(void) { /* AESD z0.b, z0.b, z0.b */ asm volatile(".inst 0x4522e400" : : : "z0"); } =20 +static void sveaes2_sigill(void) +{ + /* AESD {Z0.B - Z1.B }, { Z0.B - Z1.B }, Z0.Q */ + asm volatile(".inst 0x4522ec00" : : : "z0"); +} + static void sveb16b16_sigill(void) { /* BFADD ZA.H[W0, 0], {Z0.H-Z1.H} */ asm volatile(".inst 0xC1E41C00" : : : ); } =20 +static void svebfscale_sigill(void) +{ + /* BFSCALE Z0.H, P0/M, Z0.H, Z0.H */ + asm volatile(".inst 0x65098000" : : : "z0"); +} + +static void svef16mm_sigill(void) +{ + /* FMMLA Z0.S, Z0.H, Z0.H */ + asm volatile(".inst 0x6420e400"); +} + static void svepmull_sigill(void) { /* PMULLB Z0.Q, Z0.D, Z0.D */ @@ -383,6 +527,12 @@ static void svesha3_sigill(void) asm volatile(".inst 0x4203800" : : : "z0"); } =20 +static void sveeltperm_sigill(void) +{ + /* COMPACT Z0.B, P0, Z0.B */ + asm volatile(".inst 0x5218000" : : : "x0"); +} + static void svesm4_sigill(void) { /* SM4E Z0.S, Z0.S, Z0.S */ @@ -458,6 +608,13 @@ static const struct hwcap_data { .cpuinfo =3D "aes", .sigill_fn =3D aes_sigill, }, + { + .name =3D "CMPBR", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_CMPBR, + .cpuinfo =3D "cmpbr", + .sigill_fn =3D cmpbr_sigill, + }, { .name =3D "CRC32", .at_hwcap =3D AT_HWCAP, @@ -512,6 +669,20 @@ static const struct hwcap_data { .cpuinfo =3D "f8fma", .sigill_fn =3D f8fma_sigill, }, + { + .name =3D "F8MM8", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_F8MM8, + .cpuinfo =3D "f8mm8", + .sigill_fn =3D f8mm8_sigill, + }, + { + .name =3D "F8MM4", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_F8MM4, + .cpuinfo =3D "f8mm4", + .sigill_fn =3D f8mm4_sigill, + }, { .name =3D "FAMINMAX", .at_hwcap =3D AT_HWCAP2, @@ -534,6 +705,13 @@ static const struct hwcap_data { .sigill_fn =3D fpmr_sigill, .sigill_reliable =3D true, }, + { + .name =3D "FPRCVT", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_FPRCVT, + .cpuinfo =3D "fprcvt", + .sigill_fn =3D fprcvt_sigill, + }, { .name =3D "JSCVT", .at_hwcap =3D AT_HWCAP, @@ -672,6 +850,20 @@ static const struct hwcap_data { .cpuinfo =3D "sme2p1", .sigill_fn =3D sme2p1_sigill, }, + { + .name =3D "SME 2.2", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SME2P2, + .cpuinfo =3D "sme2p2", + .sigill_fn =3D sme2p2_sigill, + }, + { + .name =3D "SME AES", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SME_AES, + .cpuinfo =3D "smeaes", + .sigill_fn =3D sme_aes_sigill, + }, { .name =3D "SME I16I32", .at_hwcap =3D AT_HWCAP2, @@ -721,6 +913,13 @@ static const struct hwcap_data { .cpuinfo =3D "smelutv2", .sigill_fn =3D smelutv2_sigill, }, + { + .name =3D "SME SBITPERM", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SME_SBITPERM, + .cpuinfo =3D "smesbitperm", + .sigill_fn =3D sme_sbitperm_sigill, + }, { .name =3D "SME SF8FMA", .at_hwcap =3D AT_HWCAP2, @@ -728,6 +927,20 @@ static const struct hwcap_data { .cpuinfo =3D "smesf8fma", .sigill_fn =3D smesf8fma_sigill, }, + { + .name =3D "SME SF8MM8", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SME_SF8MM8, + .cpuinfo =3D "smesf8mm8", + .sigill_fn =3D smesf8mm8_sigill, + }, + { + .name =3D "SME SF8MM4", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SME_SF8MM8, + .cpuinfo =3D "smesf8mm4", + .sigill_fn =3D smesf8mm4_sigill, + }, { .name =3D "SME SF8DP2", .at_hwcap =3D AT_HWCAP2, @@ -742,6 +955,27 @@ static const struct hwcap_data { .cpuinfo =3D "smesf8dp4", .sigill_fn =3D smesf8dp4_sigill, }, + { + .name =3D "SME SFEXPA", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SME_SFEXPA, + .cpuinfo =3D "smesfexpa", + .sigill_fn =3D smesfexpa_sigill, + }, + { + .name =3D "SME SMOP4", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SME_SMOP4, + .cpuinfo =3D "smesmop4", + .sigill_fn =3D smesmop4_sigill, + }, + { + .name =3D "SME STMOP", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SME_STMOP, + .cpuinfo =3D "smestmop", + .sigill_fn =3D smestmop_sigill, + }, { .name =3D "SVE", .at_hwcap =3D AT_HWCAP, @@ -764,6 +998,13 @@ static const struct hwcap_data { .cpuinfo =3D "sve2p1", .sigill_fn =3D sve2p1_sigill, }, + { + .name =3D "SVE 2.2", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SVE2P2, + .cpuinfo =3D "sve2p2", + .sigill_fn =3D sve2p2_sigill, + }, { .name =3D "SVE AES", .at_hwcap =3D AT_HWCAP2, @@ -771,6 +1012,34 @@ static const struct hwcap_data { .cpuinfo =3D "sveaes", .sigill_fn =3D sveaes_sigill, }, + { + .name =3D "SVE AES2", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SVE_AES2, + .cpuinfo =3D "sveaes2", + .sigill_fn =3D sveaes2_sigill, + }, + { + .name =3D "SVE BFSCALE", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SVE_BFSCALE, + .cpuinfo =3D "svebfscale", + .sigill_fn =3D svebfscale_sigill, + }, + { + .name =3D "SVE ELTPERM", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SVE_ELTPERM, + .cpuinfo =3D "sveeltperm", + .sigill_fn =3D sveeltperm_sigill, + }, + { + .name =3D "SVE F16MM", + .at_hwcap =3D AT_HWCAP, + .hwcap_bit =3D HWCAP_SVE_F16MM, + .cpuinfo =3D "svef16mm", + .sigill_fn =3D svef16mm_sigill, + }, { .name =3D "SVE2 B16B16", .at_hwcap =3D AT_HWCAP2, --=20 2.39.2