From nobody Mon Nov 25 10:36:45 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 835BF1DFDB1; Mon, 28 Oct 2024 18:45:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730141130; cv=none; b=phZ8Ut+VqdY7JFrFkW9j8jD5mugSdVED09oo+D1xoOEOik74n/hes6ZlPYIXnbCyuFHAy3c9hx4RwHhj/DpfqtOzlILx0perFvLcIgXZPlhtSXTncEXPEinDhVqar9flzIJNmfcLSjXunhOojcUy03xGeaAdWaeW/TZokvdJJkM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730141130; c=relaxed/simple; bh=+CvngsTHz2ClZoR/Vw1+MREwpHm2as9JGwxps/AEPKI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=jS1KR9nhzj+f7EtkTA5/OpnKOxTgcrZUBjpcr6Ro9a2CDePhx3MKy9qLb9aaRm18T6x44827zlTl4m/bKJeu2OpvyoGsyUSiBgl0FzQWY8xL60+6hkiBEbbXuFWjeuq4HVnPo+fXyAcmmVs4Ls/F3DTLKXN71ETY9C5CZS/SeQI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=NDJSH0i2; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="NDJSH0i2" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49SBU8Bs023659; Mon, 28 Oct 2024 18:45:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= XRYtLbjjnpYdhjvtF6N8WzglTBQQH6Uq8UGfg015vHU=; b=NDJSH0i2a9unat7A zyxLHvmOJ0+daQZDEhMozG5c6t+Ui6fB1Mr+5eRD9UamZ1+0Ps6cUJxmul5hBH3T v5d8YryW3VTPhDRDoELYu07hZEl7komBzBaVS8NywX58y8unO4wG198OAyeEnwW8 8X+6DIk2HYjW+kAMateXVHJYNxouK64xbKnU5RdOWoitLbU2sXyB+01zNGsK72gX P6n3WA/XHYfxkb7/G+t1uNHnsVxefx//yQQVBK85zA2B9ivZfNYJ3KIA0D5MrQUz X9V8CbF4n1OvozAm+uzDt1sR6SdrBOORunklvRm94hNWwXwFNZ9HubBhoy9zcvPg R8iW1w== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42gskjwvhh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2024 18:45:02 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49SIj1k9011342 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2024 18:45:01 GMT Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 28 Oct 2024 11:45:00 -0700 From: Elliot Berman Date: Mon, 28 Oct 2024 11:44:55 -0700 Subject: [PATCH v7 1/5] dt-bindings: power: reset: Convert mode-.* properties to array Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241028-arm-psci-system_reset2-vendor-reboots-v7-1-a4c40b0ebc54@quicinc.com> References: <20241028-arm-psci-system_reset2-vendor-reboots-v7-0-a4c40b0ebc54@quicinc.com> In-Reply-To: <20241028-arm-psci-system_reset2-vendor-reboots-v7-0-a4c40b0ebc54@quicinc.com> To: Bjorn Andersson , Sebastian Reichel , Rob Herring , Conor Dooley , Vinod Koul , Andy Yan , Lorenzo Pieralisi , "Mark Rutland" , Bartosz Golaszewski , Arnd Bergmann , "Olof Johansson" , Catalin Marinas , "Will Deacon" , , "Krzysztof Kozlowski" , Konrad Dybcio , Konrad Dybcio CC: Satya Durga Srinivasu Prabhala , Melody Olvera , Shivendra Pratap , , , , Florian Fainelli , Stephen Boyd , , , Elliot Berman X-Mailer: b4 0.14.1 X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: SuZpT0B2WjN7T3W4qmiiJafUep_Z--pc X-Proofpoint-ORIG-GUID: SuZpT0B2WjN7T3W4qmiiJafUep_Z--pc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 impostorscore=0 suspectscore=0 phishscore=0 priorityscore=1501 mlxlogscore=999 bulkscore=0 mlxscore=0 malwarescore=0 lowpriorityscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410280147 PSCI reboot mode will map a mode name to multiple magic values instead of just one. Convert the mode-.* property to an array. Users of the reboot-mode schema will need to specify the maxItems of the mode-.* properties. Existing users will all be 1. Reviewed-by: Rob Herring (Arm) Signed-off-by: Elliot Berman --- .../devicetree/bindings/power/reset/nvmem-reboot-mode.yaml | 4 ++++ Documentation/devicetree/bindings/power/reset/qcom,pon.yaml | 7 +++= ++++ Documentation/devicetree/bindings/power/reset/reboot-mode.yaml | 4 ++-- .../devicetree/bindings/power/reset/syscon-reboot-mode.yaml | 4 ++++ 4 files changed, 17 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/power/reset/nvmem-reboot-mod= e.yaml b/Documentation/devicetree/bindings/power/reset/nvmem-reboot-mode.ya= ml index 627f8a6078c2..7f5f94673e9c 100644 --- a/Documentation/devicetree/bindings/power/reset/nvmem-reboot-mode.yaml +++ b/Documentation/devicetree/bindings/power/reset/nvmem-reboot-mode.yaml @@ -31,6 +31,10 @@ properties: allOf: - $ref: reboot-mode.yaml# =20 +patternProperties: + "^mode-.*$": + maxItems: 1 + required: - compatible - nvmem-cells diff --git a/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml b/= Documentation/devicetree/bindings/power/reset/qcom,pon.yaml index fc8105a7b9b2..3da3d02a6690 100644 --- a/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml +++ b/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml @@ -54,6 +54,10 @@ required: - compatible - reg =20 +patternProperties: + "^mode-.*$": + maxItems: 1 + unevaluatedProperties: false =20 allOf: @@ -75,6 +79,9 @@ allOf: reg-names: items: - const: pon + else: + patternProperties: + "^mode-.*$": false =20 # Special case for pm8941, which doesn't store reset mode - if: diff --git a/Documentation/devicetree/bindings/power/reset/reboot-mode.yaml= b/Documentation/devicetree/bindings/power/reset/reboot-mode.yaml index ad0a0b95cec1..3ddac06cec72 100644 --- a/Documentation/devicetree/bindings/power/reset/reboot-mode.yaml +++ b/Documentation/devicetree/bindings/power/reset/reboot-mode.yaml @@ -28,13 +28,13 @@ description: | =20 properties: mode-normal: - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32-array description: Default value to set on a reboot if no command was provided. =20 patternProperties: "^mode-.*$": - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32-array =20 additionalProperties: true =20 diff --git a/Documentation/devicetree/bindings/power/reset/syscon-reboot-mo= de.yaml b/Documentation/devicetree/bindings/power/reset/syscon-reboot-mode.= yaml index b6acff199cde..79ffc78b23ea 100644 --- a/Documentation/devicetree/bindings/power/reset/syscon-reboot-mode.yaml +++ b/Documentation/devicetree/bindings/power/reset/syscon-reboot-mode.yaml @@ -32,6 +32,10 @@ properties: allOf: - $ref: reboot-mode.yaml# =20 +patternProperties: + "^mode-.*$": + maxItems: 1 + unevaluatedProperties: false =20 required: --=20 2.34.1 From nobody Mon Nov 25 10:36:45 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91C3E1E522; Mon, 28 Oct 2024 18:45:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730141126; cv=none; b=E9Gidr/oRPGhsnyFJOph9R1YhNpq44TTy3LHX/PwiULb44Vb9xnSdGIBedLL+d+yupom/ZRw5x6rtboaPcXLy+AfTZ9gUYbZinIVvcL4tOR8pfq1m/X/birXzo49TPTk5p+H0J5LkqR1MoHumHcxkS3v13gBPT4sakxYLwq88e8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730141126; c=relaxed/simple; bh=R5srwtmYR9mElcqoklp/38dP5Tt9ykPaevQOEd9DkO4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=D3sVZgyQ0Di+sT0yYIaiR3MaloYEBXa+qhXq60TPD86waz55leqxE/aSOesxMHWbYTCVaVW+EfL4UdewpiqsIWzc9NR08unHL9s2nNr+J0hirR5bE2FjswrnZ5S9vOjptEbMQbR/LS1CLp8FgallmvYWeA4VjrkGhYIf88UD9dA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=BynwRC9r; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="BynwRC9r" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49SB2497014424; Mon, 28 Oct 2024 18:45:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= quj/S3JGad34i2NN7vazFj3Fjo2WdB7ZqzccTBfoKo8=; b=BynwRC9rd6nBN2y1 nMRcQ4bmR5RVX4YLTngkjbP+4+bjDA1KIfGAcUzmpt1pGeRyYZD9yk2L4td3oH+S OGkBHU+hR6tEYu7wQys3/iUe5LPYTfsNe3Zom2zI9X6/gEyHafjUrIX9VKMEYs7j WOypU5lGFvEU0Q8UNBBDF1aSn6p6/9GgEnBNUnsp9g4aRp2LjJ0C5US2Rg8tv3O7 8Rc967VDxxLqlusjJqWEVq4peRfZoxZfHfODp9gevDn/CKPnj/umNstDa1HfrhQU sUzdOWGQNE8qj0QXU9jzrWuqqqFO7C+sTwNaaoKaQAmb1q0mBdkwETs47v+HGcYJ arHbAQ== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42gnsmp6c6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2024 18:45:04 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49SIj25v027569 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2024 18:45:02 GMT Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 28 Oct 2024 11:45:01 -0700 From: Elliot Berman Date: Mon, 28 Oct 2024 11:44:56 -0700 Subject: [PATCH v7 2/5] dt-bindings: arm: Document reboot mode magic Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241028-arm-psci-system_reset2-vendor-reboots-v7-2-a4c40b0ebc54@quicinc.com> References: <20241028-arm-psci-system_reset2-vendor-reboots-v7-0-a4c40b0ebc54@quicinc.com> In-Reply-To: <20241028-arm-psci-system_reset2-vendor-reboots-v7-0-a4c40b0ebc54@quicinc.com> To: Bjorn Andersson , Sebastian Reichel , Rob Herring , Conor Dooley , Vinod Koul , Andy Yan , Lorenzo Pieralisi , "Mark Rutland" , Bartosz Golaszewski , Arnd Bergmann , "Olof Johansson" , Catalin Marinas , "Will Deacon" , , "Krzysztof Kozlowski" , Konrad Dybcio , Konrad Dybcio CC: Satya Durga Srinivasu Prabhala , Melody Olvera , Shivendra Pratap , , , , Florian Fainelli , Stephen Boyd , , , Elliot Berman X-Mailer: b4 0.14.1 X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: AxZnAW99DLn_RaCc7F6WKYUE-wPkUGiL X-Proofpoint-GUID: AxZnAW99DLn_RaCc7F6WKYUE-wPkUGiL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 adultscore=0 priorityscore=1501 bulkscore=0 phishscore=0 spamscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410280146 Add bindings to describe vendor-specific reboot modes. Values here correspond to valid parameters to vendor-specific reset types in PSCI SYSTEM_RESET2 call. Reviewed-by: Rob Herring (Arm) Signed-off-by: Elliot Berman --- Documentation/devicetree/bindings/arm/psci.yaml | 43 +++++++++++++++++++++= ++++ 1 file changed, 43 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/psci.yaml b/Documentatio= n/devicetree/bindings/arm/psci.yaml index cbb012e217ab..5e07c62fe5d7 100644 --- a/Documentation/devicetree/bindings/arm/psci.yaml +++ b/Documentation/devicetree/bindings/arm/psci.yaml @@ -98,6 +98,27 @@ properties: [1] Kernel documentation - ARM idle states bindings Documentation/devicetree/bindings/cpu/idle-states.yaml =20 + reset-types: + type: object + $ref: /schemas/power/reset/reboot-mode.yaml# + unevaluatedProperties: false + properties: + # "mode-normal" is just SYSTEM_RESET + mode-normal: false + patternProperties: + "^mode-.*$": + minItems: 1 + maxItems: 2 + description: | + Describes a vendor-specific reset type. The string after "mode-" + maps a reboot mode to the parameters in the PSCI SYSTEM_RESET2 c= all. + + Parameters are named mode-xxx =3D , where xxx + is the name of the magic reboot mode, type is the lower 31 bits + of the reset_type, and, optionally, the cookie value. If the coo= kie + is not provided, it is defaulted to zero. + The 31st bit (vendor-resets) will be implicitly set by the drive= r. + patternProperties: "^power-domain-": $ref: /schemas/power/power-domain.yaml# @@ -137,6 +158,15 @@ allOf: required: - cpu_off - cpu_on + - if: + not: + properties: + compatible: + contains: + const: arm,psci-1.0 + then: + properties: + reset-types: false =20 additionalProperties: false =20 @@ -261,4 +291,17 @@ examples: domain-idle-states =3D <&CLUSTER_RET>, <&CLUSTER_PWRDN>; }; }; + + - |+ + + // Case 5: SYSTEM_RESET2 vendor resets + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + reset-types { + mode-edl =3D <0>; + mode-bootloader =3D <1 2>; + }; + }; ... --=20 2.34.1 From nobody Mon Nov 25 10:36:45 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 708AE1DFE0B; Mon, 28 Oct 2024 18:45:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730141131; cv=none; b=jnWBRSxthu5Flw9yvfrqVIdlq4jICvdkWg2QJa948XR18ramPg6/5PLPAQGKDZ+6iExLSrJy5g5RkM57Kxni3vxuF29OThnXFTbifn7oDySjjVHPUzJEMacV1U7gc7sHlgIXJFx7n1EdjwoukjI4WO+Zt0nd1o4XhCQ5KedGIPg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730141131; c=relaxed/simple; bh=cUkBEdrTSKfJnh55BiESktGrAnUgoJe2ay0L0ERWxk0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=WKGLwR9TmPZqmYcqqKHnoFXdokh+HRYhfJR6CW2M9aW6M6rYMkXZBlMCXn/3DyHtwJ4Wso5Y+XHghzf2G5iCoEpfSYGv3xi0Mq33fOHmwu9zTqdm//5rR49uRJepWn3M4TF0A+drN6okr6ojP7juksjZEjKeCbHRo3uTRB0mIak= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=QmYwtrTC; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="QmYwtrTC" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49SAWsTX031602; Mon, 28 Oct 2024 18:45:03 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= QezESXxHqBez0fhuBmP1of7VV/80rnDoCk4pnfhP+14=; b=QmYwtrTCwyrtMWoY 6luxXCp+njCCtwlReb2W/0q41/jEDMCZxoiBC5bHN66huZe4JNif7QXalu2fsmOT wftDsBccfpEFc0u1sVKPfA7vNfcweutOz5jt/FnNkvE8Zi5rJZyngg6fkn+Mccxt smKV2gyZj7whetbo09jEy5z5mRKs+fr937IkqT4cexIhqjOhbA999y5kR0rvladp EtBZwJEoRhrSsHJrYEtJmeQraPBBcd7JmHnEPFpNg+1aC64HALS/2INj/HuXFIlq EXUzAc8sypz8sxfDr6R9SUzgcJP/v2ljJa2Sb/DDsrYJ9DnLXFrYiM41BcoiwQMd t2sxLw== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42gsq8dyun-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2024 18:45:03 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49SIj25w027569 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2024 18:45:02 GMT Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 28 Oct 2024 11:45:01 -0700 From: Elliot Berman Date: Mon, 28 Oct 2024 11:44:57 -0700 Subject: [PATCH v7 3/5] firmware: psci: Read and use vendor reset types Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241028-arm-psci-system_reset2-vendor-reboots-v7-3-a4c40b0ebc54@quicinc.com> References: <20241028-arm-psci-system_reset2-vendor-reboots-v7-0-a4c40b0ebc54@quicinc.com> In-Reply-To: <20241028-arm-psci-system_reset2-vendor-reboots-v7-0-a4c40b0ebc54@quicinc.com> To: Bjorn Andersson , Sebastian Reichel , Rob Herring , Conor Dooley , Vinod Koul , Andy Yan , Lorenzo Pieralisi , "Mark Rutland" , Bartosz Golaszewski , Arnd Bergmann , "Olof Johansson" , Catalin Marinas , "Will Deacon" , , "Krzysztof Kozlowski" , Konrad Dybcio , Konrad Dybcio CC: Satya Durga Srinivasu Prabhala , Melody Olvera , Shivendra Pratap , , , , Florian Fainelli , Stephen Boyd , , , Elliot Berman X-Mailer: b4 0.14.1 X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Zz7cm5HOTG31oEA3rQNNnz8V0W4_KbHF X-Proofpoint-ORIG-GUID: Zz7cm5HOTG31oEA3rQNNnz8V0W4_KbHF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 adultscore=0 mlxscore=0 priorityscore=1501 mlxlogscore=999 impostorscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1011 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410280147 SoC vendors have different types of resets and are controlled through various registers. For instance, Qualcomm chipsets can reboot to a "download mode" that allows a RAM dump to be collected. Another example is they also support writing a cookie that can be read by bootloader during next boot. PSCI offers a mechanism, SYSTEM_RESET2, for these vendor reset types to be implemented without requiring drivers for every register/cookie. Add support in PSCI to statically map reboot mode commands from userspace to a vendor reset and cookie value using the device tree. A separate initcall is needed to parse the devicetree, instead of using psci_dt_init because mm isn't sufficiently set up to allocate memory. Reboot mode framework is close but doesn't quite fit with the design and requirements for PSCI SYSTEM_RESET2. Some of these issues can be solved but doesn't seem reasonable in sum: 1. reboot mode registers against the reboot_notifier_list, which is too early to call SYSTEM_RESET2. PSCI would need to remember the reset type from the reboot-mode framework callback and use it psci_sys_reset. 2. reboot mode assumes only one cookie/parameter is described in the device tree. SYSTEM_RESET2 uses 2: one for the type and one for cookie. 3. psci cpuidle driver already registers a driver against the arm,psci-1.0 compatible. Refactoring would be needed to have both a cpuidle and reboot-mode driver. Tested-by: Florian Fainelli Signed-off-by: Elliot Berman --- drivers/firmware/psci/psci.c | 104 +++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 104 insertions(+) diff --git a/drivers/firmware/psci/psci.c b/drivers/firmware/psci/psci.c index 2328ca58bba6..2d7b6efc8743 100644 --- a/drivers/firmware/psci/psci.c +++ b/drivers/firmware/psci/psci.c @@ -79,6 +79,14 @@ struct psci_0_1_function_ids get_psci_0_1_function_ids(v= oid) static u32 psci_cpu_suspend_feature; static bool psci_system_reset2_supported; =20 +struct psci_reset_param { + const char *mode; + u32 reset_type; + u32 cookie; +}; +static struct psci_reset_param *psci_reset_params; +static size_t num_psci_reset_params; + static inline bool psci_has_ext_power_state(void) { return psci_cpu_suspend_feature & @@ -305,9 +313,38 @@ static int get_set_conduit_method(const struct device_= node *np) return 0; } =20 +static void psci_vendor_system_reset2(unsigned long action, void *data) +{ + const char *cmd =3D data; + unsigned long ret; + size_t i; + + for (i =3D 0; i < num_psci_reset_params; i++) { + if (!strcmp(psci_reset_params[i].mode, cmd)) { + ret =3D invoke_psci_fn(PSCI_FN_NATIVE(1_1, SYSTEM_RESET2), + psci_reset_params[i].reset_type, + psci_reset_params[i].cookie, 0); + /* + * if vendor reset fails, log it and fall back to + * architecture reset types + */ + pr_err("failed to perform reset \"%s\": %ld\n", cmd, + (long)ret); + } + } +} + static int psci_sys_reset(struct notifier_block *nb, unsigned long action, void *data) { + /* + * try to do the vendor system_reset2 + * If the reset fails or there wasn't a match on the command, + * fall back to architectural resets + */ + if (data && num_psci_reset_params) + psci_vendor_system_reset2(action, data); + if ((reboot_mode =3D=3D REBOOT_WARM || reboot_mode =3D=3D REBOOT_SOFT) && psci_system_reset2_supported) { /* @@ -750,6 +787,73 @@ static const struct of_device_id psci_of_match[] __ini= tconst =3D { {}, }; =20 +#define REBOOT_PREFIX "mode-" + +static int __init psci_init_system_reset2_modes(void) +{ + const size_t len =3D strlen(REBOOT_PREFIX); + struct psci_reset_param *param; + struct device_node *psci_np __free(device_node) =3D NULL; + struct device_node *np __free(device_node) =3D NULL; + struct property *prop; + size_t count =3D 0; + u32 magic[2]; + int num; + + if (!psci_system_reset2_supported) + return 0; + + psci_np =3D of_find_matching_node(NULL, psci_of_match); + if (!psci_np) + return 0; + + np =3D of_find_node_by_name(psci_np, "reset-types"); + if (!np) + return 0; + + for_each_property_of_node(np, prop) { + if (strncmp(prop->name, REBOOT_PREFIX, len)) + continue; + num =3D of_property_count_u32_elems(np, prop->name); + if (num !=3D 1 && num !=3D 2) + continue; + + count++; + } + + param =3D psci_reset_params =3D + kcalloc(count, sizeof(*psci_reset_params), GFP_KERNEL); + if (!psci_reset_params) + return -ENOMEM; + + for_each_property_of_node(np, prop) { + if (strncmp(prop->name, REBOOT_PREFIX, len)) + continue; + + param->mode =3D kstrdup_const(prop->name + len, GFP_KERNEL); + if (!param->mode) + continue; + + num =3D of_property_read_variable_u32_array(np, prop->name, magic, + 1, ARRAY_SIZE(magic)); + if (num < 0) { + pr_warn("Failed to parse vendor reboot mode %s\n", + param->mode); + kfree_const(param->mode); + continue; + } + + /* Force reset type to be in vendor space */ + param->reset_type =3D PSCI_1_1_RESET_TYPE_VENDOR_START | magic[0]; + param->cookie =3D num > 1 ? magic[1] : 0; + param++; + num_psci_reset_params++; + } + + return 0; +} +arch_initcall(psci_init_system_reset2_modes); + int __init psci_dt_init(void) { struct device_node *np; --=20 2.34.1 From nobody Mon Nov 25 10:36:45 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 708541DFE0A; Mon, 28 Oct 2024 18:45:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730141131; cv=none; b=uv4bBbRXLP2b4oZNDhNFor0xBd/ZsHMzrZlpF9PwpfMAiLznVwPGsn/M0UYQKbaayrOJdtWvZqAbj6uenLIhwSzDG1C3axxY3AhC1iVHLWMnQiWWy0JZczVIe8Jl8dZ7SJ79RZf07ujMblxUR2Y4los47x2fAblmvznYYZl2dYg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730141131; c=relaxed/simple; bh=h8PQnh8F9i6MkcgRlZaaJYKo+Vsg5LT/gUf2VKZtXdY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=pBP0vAcx23cWW4T0OkoilfFuIdtm+1fb9iNBRzJdIpOlg+z0Iu3IczlMOi3EzWvlI+e8MHf9IhZ9AkyA0qZlg58Sc3EBerC62joJEjdNWoLUQ+qLLx8I7BL7C7NniwXeZeem/1/0EUX+TKKRwI0fezuUjKU2XGy9cH1gDIwPsc4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=ECQW6rd6; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ECQW6rd6" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49SB6GQe015991; Mon, 28 Oct 2024 18:45:03 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= sFFmDDAWd1KAkhfjqJBVFcxEijY65eQyMZIWz5ge9lc=; b=ECQW6rd68fUy94P4 aWqCDSJCT8wUQTWmshD9VqSDMGDeIY5SEgFNNv3Esd9SVkh8L4o57GsKbjHuctMP Wj+eCqY3MlklerFrHdUN4drAgTsGMJuwFSbPxjWMC76ht+4s3lvafIS0wGnbXGRa c2zZAhht+qd4L8b7Da14AT/ZjbkqZ24IGzUDFBY5uqEYu8yZoBq/GhbILHdGsDTA pY0Omw19ENZEY1GG8+zGG5sUkh+jfgETa+0AiOZv9SinjfAUjcqOKYPYn4Mdmygz XbMLZGIFORVGPl/Lgr+T0KXaitCuf9CaIZh12bdIn6JQ698XfQzbQwRjtfEP51N5 HGLMzQ== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42gp4dx6a5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2024 18:45:03 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49SIj2Sm011663 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2024 18:45:02 GMT Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 28 Oct 2024 11:45:02 -0700 From: Elliot Berman Date: Mon, 28 Oct 2024 11:44:58 -0700 Subject: [PATCH v7 4/5] arm64: dts: qcom: Add PSCI SYSTEM_RESET2 types for qcm6490-idp Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241028-arm-psci-system_reset2-vendor-reboots-v7-4-a4c40b0ebc54@quicinc.com> References: <20241028-arm-psci-system_reset2-vendor-reboots-v7-0-a4c40b0ebc54@quicinc.com> In-Reply-To: <20241028-arm-psci-system_reset2-vendor-reboots-v7-0-a4c40b0ebc54@quicinc.com> To: Bjorn Andersson , Sebastian Reichel , Rob Herring , Conor Dooley , Vinod Koul , Andy Yan , Lorenzo Pieralisi , "Mark Rutland" , Bartosz Golaszewski , Arnd Bergmann , "Olof Johansson" , Catalin Marinas , "Will Deacon" , , "Krzysztof Kozlowski" , Konrad Dybcio , Konrad Dybcio CC: Satya Durga Srinivasu Prabhala , Melody Olvera , Shivendra Pratap , , , , Florian Fainelli , Stephen Boyd , , , Elliot Berman X-Mailer: b4 0.14.1 X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 4Ilf5PDTkc9UCNlqDz3L55cTf4TCT1_l X-Proofpoint-GUID: 4Ilf5PDTkc9UCNlqDz3L55cTf4TCT1_l X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 mlxlogscore=779 clxscore=1015 spamscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 adultscore=0 phishscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410280147 Add nodes for the vendor-defined system resets. "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Co-developed-by: Shivendra Pratap Signed-off-by: Shivendra Pratap Reviewed-by: Konrad Dybcio Signed-off-by: Elliot Berman --- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 7 +++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts= /qcom/qcm6490-idp.dts index a0668f767e4b..9c141244a7b2 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -617,6 +617,13 @@ &pon_resin { status =3D "okay"; }; =20 +&psci { + reset-types { + mode-bootloader =3D <0x10001 0x2>; + mode-edl =3D <0 0x1>; + }; +}; + &qupv3_id_0 { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 3d8410683402..5360d0e51a65 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -850,7 +850,7 @@ pmu { interrupts =3D ; }; =20 - psci { + psci: psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 --=20 2.34.1 From nobody Mon Nov 25 10:36:45 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93F2C1DFE13; Mon, 28 Oct 2024 18:45:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730141132; cv=none; b=CougeZTVTfQHwd3CiMtoerePIfmqApOTRys1vpB0T+bLjkVvsGYO2QD2ioZfVUet9ibB7T+CctaWmPpkfpxcwA2QpxBwIUBbFQZ0UOUNYQ6xNNKg6rEaQN0K9JCGXJML5fqjfDaoN3wg0fIgCF2eeqoMMXMbq+pKIHiaJYzTXno= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730141132; c=relaxed/simple; bh=SdEevymtrIAaa5wYZ7tbEjzfMEv+LIeEhjDsRCbg648=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=XajAV/0Bwd4UrPL8oLWlE/BAm7OTeEdhkdg22wRV9gifaqoXf/unTXReVoBnQoEEmPoimQf/ObaWAviLbI1k7bE9amg0px13ZNl+ZepvrYGZXmZfabGewIx7IjhU4FYKTk01BIlMu4awqWQv9gjhPyFBupdIonaeNhmSKa5RoaE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=OHLyJlfK; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="OHLyJlfK" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49SAeelO028808; Mon, 28 Oct 2024 18:45:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= jovw9Io0FAsNVpy/zr5AVFcQbEL15/Uxof+hWVloP3s=; b=OHLyJlfKQvOOmWnx 2ec107juJ3RbvuOLJh/6/smBna+D6XpwYYHQoaiIBTdhDiIrlk3lmLG2oGxS84L+ fuRjslkd4sFO+n+Bajhstv6H5734lsVO1pSVSF0uvEadFWg5yqwVeMEMDYL/rpiK GFUeMxWdd3fwf0LIHI00l4AzfEnxGrMNNTtWtePBOv+HaF6LdaauE5NAP128qF5B 2JTNdnSSmpf01YgmnqZzfsb8iygSx1BkwxW15vQQacb9VS+8LBrTKBmYTMPaLNAE MJaL/1YPZLjLBsTyPsLAj4/YQHrE7iGuD4HdY7ruXunjxI6PDqL0/XDgmnxGzOJ7 HLSyMg== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42gsq8dyup-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2024 18:45:04 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49SIj3Vd011697 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2024 18:45:03 GMT Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 28 Oct 2024 11:45:02 -0700 From: Elliot Berman Date: Mon, 28 Oct 2024 11:44:59 -0700 Subject: [PATCH v7 5/5] arm64: dts: qcom: Add PSCI SYSTEM_RESET2 types for sa8775p-ride Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241028-arm-psci-system_reset2-vendor-reboots-v7-5-a4c40b0ebc54@quicinc.com> References: <20241028-arm-psci-system_reset2-vendor-reboots-v7-0-a4c40b0ebc54@quicinc.com> In-Reply-To: <20241028-arm-psci-system_reset2-vendor-reboots-v7-0-a4c40b0ebc54@quicinc.com> To: Bjorn Andersson , Sebastian Reichel , Rob Herring , Conor Dooley , Vinod Koul , Andy Yan , Lorenzo Pieralisi , "Mark Rutland" , Bartosz Golaszewski , Arnd Bergmann , "Olof Johansson" , Catalin Marinas , "Will Deacon" , , "Krzysztof Kozlowski" , Konrad Dybcio , Konrad Dybcio CC: Satya Durga Srinivasu Prabhala , Melody Olvera , Shivendra Pratap , , , , Florian Fainelli , Stephen Boyd , , , Elliot Berman X-Mailer: b4 0.14.1 X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 3Iwzot7UU9L9vClWMjUBPtv_g1CK5vVS X-Proofpoint-ORIG-GUID: 3Iwzot7UU9L9vClWMjUBPtv_g1CK5vVS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 adultscore=0 mlxscore=0 priorityscore=1501 mlxlogscore=811 impostorscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410280147 Add nodes for the vendor-defined system resets. "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Co-developed-by: Shivendra Pratap Signed-off-by: Shivendra Pratap Signed-off-by: Elliot Berman --- arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 7 +++++++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/d= ts/qcom/sa8775p-ride.dtsi index 2a6170623ea9..9e8cc2187333 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi @@ -498,6 +498,13 @@ &pmm8654au_3_gpios { "GNSS_BOOT_MODE"; }; =20 +&psci { + reset-types { + mode-bootloader =3D <0x10001 0x2>; + mode-edl =3D <0 0x1>; + }; +}; + &qupv3_id_1 { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index 23f1b2e5e624..dd36eea80f7c 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -329,7 +329,7 @@ pmu { interrupts =3D ; }; =20 - psci { + psci: psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; }; --=20 2.34.1