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[93.89.165.28]) by smtp.googlemail.com with ESMTPSA id a640c23a62f3a-a9b1f029617sm397585166b.81.2024.10.28.11.48.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Oct 2024 11:48:26 -0700 (PDT) From: Gabor Juhos Date: Mon, 28 Oct 2024 19:48:17 +0100 Subject: [PATCH v2 3/5] clk: qcom: gcc-ipq6018: remove alpha values from NSS Crypto PLL's config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241028-alpha-mode-cleanup-v2-3-9bc6d712bd76@gmail.com> References: <20241028-alpha-mode-cleanup-v2-0-9bc6d712bd76@gmail.com> In-Reply-To: <20241028-alpha-mode-cleanup-v2-0-9bc6d712bd76@gmail.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Gabor Juhos X-Mailer: b4 0.14.2 Since both the 'alpha' and 'alpha_hi' members of the configuration is initialized with zero values, the output rate of the PLL will be the same whether alpha mode is enabled or not. Remove the initialization of the alpha* members to make it clear that alpha mode is not required to get the desired output rate. Despite that enabling alpha mode is not needed for the initial configuration, the set_rate() op might require that it is enabled already. In this particular case however, the clk_alpha_pll_set_rate() function will get reset the ALPHA_EN bit when the PLL's rate changes, so dropping 'alpha_en_mask' is safe. While at it, also add a comment to indicate the frequency the PLL runs at with the current configuration. No functional changes, the PLL runs at 1.2 GHz both before and after the change. Tested on Xiaomi Mi Router AX1800 (IPQ6018, out-of-tree board). Reviewed-by: Dmitry Baryshkov Signed-off-by: Gabor Juhos --- Changes in v2: - extend the commit message to indicate that dropping 'alpha_en_mask' is = safe - add RB tag from Dmitry - Link to v1: https://lore.kernel.org/r/20241021-alpha-mode-cleanup-v1-3-= 55df8ed73645@gmail.com --- drivers/clk/qcom/gcc-ipq6018.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c index ab0f7fc665a9790dd8edba0cf4b86c5c672a337d..d861191b0c85ccc105ac0e62d7a= 68210c621fc13 100644 --- a/drivers/clk/qcom/gcc-ipq6018.c +++ b/drivers/clk/qcom/gcc-ipq6018.c @@ -4194,10 +4194,9 @@ static const struct alpha_pll_config ubi32_pll_confi= g =3D { .test_ctl_hi_val =3D 0x4000, }; =20 +/* 1200 MHz configuration */ static const struct alpha_pll_config nss_crypto_pll_config =3D { .l =3D 0x32, - .alpha =3D 0x0, - .alpha_hi =3D 0x0, .config_ctl_val =3D 0x4001055b, .main_output_mask =3D BIT(0), .pre_div_val =3D 0x0, @@ -4206,7 +4205,6 @@ static const struct alpha_pll_config nss_crypto_pll_c= onfig =3D { .post_div_mask =3D GENMASK(11, 8), .vco_mask =3D GENMASK(21, 20), .vco_val =3D 0x0, - .alpha_en_mask =3D BIT(24), }; =20 static struct clk_hw *gcc_ipq6018_hws[] =3D { --=20 2.47.0