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charset="utf-8" Earlier this year a new DTSI file was created to define common properties for the StarFive VisionFive 2 and Milk-V Mars boards, both of which use the StarFive JH7110 SoC. The Pine64 Star64 board has also been added since that time. Some of the nodes defined in "jh7110-common.dtsi" are enabled in that file because all of the boards including it "want" them enabled. An upcoming patch enables another JH7110 board, but for that board not all of these common nodes should be enabled. Prepare for supporting the new board by avoiding enabling these nodes in "jh711-common.dtsi", and enable them instead in these files: jh7110-milkv-mars.dts jh7110-pine64-star64.dts jh7110-starfive-visionfive-2.dtsi Signed-off-by: Alex Elder Signed-off-by: Guodong Xu Reviewed-by: Emil Renner Berthing --- v6: New patch .../boot/dts/starfive/jh7110-common.dtsi | 5 ----- .../boot/dts/starfive/jh7110-milkv-mars.dts | 17 ++++++++++++++++ .../dts/starfive/jh7110-pine64-star64.dts | 17 ++++++++++++++++ .../jh7110-starfive-visionfive-2.dtsi | 20 +++++++++++++++++++ 4 files changed, 54 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/b= oot/dts/starfive/jh7110-common.dtsi index c7771b3b6475..9e77f79ec162 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi .../boot/dts/starfive/jh7110-common.dtsi | 5 ----- .../boot/dts/starfive/jh7110-milkv-mars.dts | 17 ++++++++++++++++ .../dts/starfive/jh7110-pine64-star64.dts | 17 ++++++++++++++++ .../jh7110-starfive-visionfive-2.dtsi | 20 +++++++++++++++++++ 4 files changed, 54 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/b= oot/dts/starfive/jh7110-common.dtsi index c7771b3b6475..9e77f79ec162 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -176,7 +176,6 @@ csi2rx_to_camss: endpoint { &gmac0 { phy-handle =3D <&phy0>; phy-mode =3D "rgmii-id"; - status =3D "okay"; =20 mdio { #address-cells =3D <1>; @@ -196,7 +195,6 @@ &i2c0 { i2c-scl-falling-time-ns =3D <510>; pinctrl-names =3D "default"; pinctrl-0 =3D <&i2c0_pins>; - status =3D "okay"; }; =20 &i2c2 { @@ -311,7 +309,6 @@ &pcie1 { &pwmdac { pinctrl-names =3D "default"; pinctrl-0 =3D <&pwmdac_pins>; - status =3D "okay"; }; =20 &qspi { @@ -350,13 +347,11 @@ uboot@100000 { &pwm { pinctrl-names =3D "default"; pinctrl-0 =3D <&pwm_pins>; - status =3D "okay"; }; =20 &spi0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&spi0_pins>; - status =3D "okay"; =20 spi_dev0: spi@0 { compatible =3D "rohm,dh2228fv"; diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts b/arch/risc= v/boot/dts/starfive/jh7110-milkv-mars.dts index 5cb9e99e1dac..66ad3eb2fd66 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts @@ -15,6 +15,11 @@ &gmac0 { starfive,tx-use-rgmii-clk; assigned-clocks =3D <&aoncrg JH7110_AONCLK_GMAC0_TX>; assigned-clock-parents =3D <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>; + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; }; =20 &pcie0 { @@ -35,3 +40,15 @@ &phy0 { rx-internal-delay-ps =3D <1500>; tx-internal-delay-ps =3D <1500>; }; + +&pwm { + status =3D "okay"; +}; + +&pwmdac { + status =3D "okay"; +}; + +&spi0 { + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts b/arch/r= iscv/boot/dts/starfive/jh7110-pine64-star64.dts index b720cdd15ed6..dbc8612b8464 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts @@ -18,6 +18,7 @@ &gmac0 { starfive,tx-use-rgmii-clk; assigned-clocks =3D <&aoncrg JH7110_AONCLK_GMAC0_TX>; assigned-clock-parents =3D <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>; + status =3D "okay"; }; =20 &gmac1 { @@ -39,6 +40,10 @@ phy1: ethernet-phy@1 { }; }; =20 +&i2c0 { + status =3D "okay"; +}; + &pcie1 { status =3D "okay"; }; @@ -63,3 +68,15 @@ &phy1 { motorcomm,tx-clk-10-inverted; motorcomm,tx-clk-100-inverted; }; + +&pwm { + status =3D "okay"; +}; + +&pwmdac { + status =3D "okay"; +}; + +&spi0 { + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi= b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 18f38fc790a4..ef93a394bb2f 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -13,6 +13,10 @@ aliases { }; }; =20 +&gmac0 { + status =3D "okay"; +}; + &gmac1 { phy-handle =3D <&phy1>; phy-mode =3D "rgmii-id"; @@ -29,6 +33,10 @@ phy1: ethernet-phy@1 { }; }; =20 +&i2c0 { + status =3D "okay"; +}; + &mmc0 { non-removable; }; @@ -40,3 +48,15 @@ &pcie0 { &pcie1 { status =3D "okay"; }; + +&pwm { + status =3D "okay"; +}; + +&pwmdac { + status =3D "okay"; +}; + +&spi0 { + status =3D "okay"; +}; --=20 2.34.1 From nobody Mon Nov 25 12:25:27 2024 Received: from mail-pf1-f174.google.com (mail-pf1-f174.google.com [209.85.210.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C044168497 for ; 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Sun, 27 Oct 2024 07:46:22 -0700 (PDT) Received: from localhost.localdomain ([2a11:3:200::401b]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72057a0cb06sm4065110b3a.115.2024.10.27.07.46.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:46:22 -0700 (PDT) From: Guodong Xu To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , rafal@milecki.pl, Greg Kroah-Hartman Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Neil Armstrong , Heiko Stuebner , Michael Zhu , Drew Fustini , Alexandru Stan , Daniel Schaefer , Sandie Cao , Yuning Liang , Huiming Qiu , Alex Elder , linux@frame.work, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Guodong Xu Subject: [PATCH v6 2/5] riscv: dts: starfive: jh7110-common: move usb0 config to board dts Date: Sun, 27 Oct 2024 22:44:45 +0800 Message-Id: <20241027144448.1813611-3-guodong@riscstar.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241027144448.1813611-1-guodong@riscstar.com> References: <20241027144448.1813611-1-guodong@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The JH7110 USB0 can operate as a dual-role USB device. Different boards can have different configuration. For all current boards this device operates in peripheral mode, but on a new board this operates in host mode. This property will no longer be common, so define the "dr_mode" property in the board files rather than in the common DTSI file. Signed-off-by: Alex Elder Signed-off-by: Guodong Xu Reviewed-by: Emil Renner Berthing --- v6: New patch arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 5 ----- arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts | 5 +++++ arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts | 5 +++++ .../boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 5 +++++ 4 files changed, 15 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/b= oot/dts/starfive/jh7110-common.dtsi index 9e77f79ec162..87ea81e9fed4 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -637,11 +637,6 @@ &uart0 { status =3D "okay"; }; =20 -&usb0 { - dr_mode =3D "peripheral"; - status =3D "okay"; -}; - &U74_1 { cpu-supply =3D <&vdd_cpu>; }; diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts b/arch/risc= v/boot/dts/starfive/jh7110-milkv-mars.dts index 66ad3eb2fd66..0d248b671d4b 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts @@ -52,3 +52,8 @@ &pwmdac { &spi0 { status =3D "okay"; }; + +&usb0 { + dr_mode =3D "peripheral"; + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts b/arch/r= iscv/boot/dts/starfive/jh7110-pine64-star64.dts index dbc8612b8464..d5180c67ac55 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts @@ -80,3 +80,8 @@ &pwmdac { &spi0 { status =3D "okay"; }; + +&usb0 { + dr_mode =3D "peripheral"; + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi= b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index ef93a394bb2f..5f14afb2c24d 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -60,3 +60,8 @@ &pwmdac { &spi0 { status =3D "okay"; }; + +&usb0 { + dr_mode =3D "peripheral"; + status =3D "okay"; +}; --=20 2.34.1 From nobody Mon Nov 25 12:25:27 2024 Received: from mail-pf1-f174.google.com (mail-pf1-f174.google.com [209.85.210.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A31BA16FF45 for ; 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charset="utf-8" From: Sandie Cao Add "deepcomputing" to the Devicetree Vendor Prefix Registry. Signed-off-by: Sandie Cao Acked-by: Krzysztof Kozlowski [elder@riscstar.com: revised the description] Signed-off-by: Alex Elder Signed-off-by: Guodong Xu --- v6: No change v5: Removed extra "From:" line in the commit message v4: Updated description v3: Add Krzysztof's ack v2: Add deepcomputing into Vendor Prefix Registery Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index b320a39de7fe..f8bb3df65797 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -356,6 +356,8 @@ patternProperties: description: DataImage, Inc. "^davicom,.*": description: DAVICOM Semiconductor, Inc. + "^deepcomputing,.*": + description: DeepComputing (HK) Limited "^dell,.*": description: Dell Inc. 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charset="utf-8" From: Sandie Cao Add "deepcomputing,fml13v01" as a StarFive SoC-based board. The DeepComputing FML13V01 board incorporates a StarFive JH7110 SoC, and it's designed for the Framework Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001. Signed-off-by: Sandie Cao Acked-by: Rob Herring (Arm) [elder@riscstar.com: considerably shortened the description] Signed-off-by: Alex Elder Signed-off-by: Guodong Xu Reviewed-by: Emil Renner Berthing --- v6: Added Emil's Reviewed-by v5: Removed extra "From:" line in the commit message v4: Added Rob's Ack Updated description Changed board name from fm7110 to fml13v01 v3: No change v2: Add deepcomputing,fm7110 into model compatible list Documentation/devicetree/bindings/riscv/starfive.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Docume= ntation/devicetree/bindings/riscv/starfive.yaml index 4d5c857b3cac..7ef85174353d 100644 --- a/Documentation/devicetree/bindings/riscv/starfive.yaml +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml @@ -26,6 +26,7 @@ properties: =20 - items: - enum: + - deepcomputing,fml13v01 - milkv,mars - pine64,star64 - starfive,visionfive-2-v1.2a --=20 2.34.1 From nobody Mon Nov 25 12:25:27 2024 Received: from mail-pf1-f181.google.com (mail-pf1-f181.google.com [209.85.210.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C25FBC13B for ; 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Sun, 27 Oct 2024 07:47:21 -0700 (PDT) Received: from localhost.localdomain ([2a11:3:200::401b]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72057a0cb06sm4065110b3a.115.2024.10.27.07.47.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:47:20 -0700 (PDT) From: Guodong Xu To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , rafal@milecki.pl, Greg Kroah-Hartman Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Neil Armstrong , Heiko Stuebner , Michael Zhu , Drew Fustini , Alexandru Stan , Daniel Schaefer , Sandie Cao , Yuning Liang , Huiming Qiu , Alex Elder , linux@frame.work, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Guodong Xu Subject: [PATCH v6 5/5] riscv: dts: starfive: add DeepComputing FML13V01 board device tree Date: Sun, 27 Oct 2024 22:44:48 +0800 Message-Id: <20241027144448.1813611-6-guodong@riscstar.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241027144448.1813611-1-guodong@riscstar.com> References: <20241027144448.1813611-1-guodong@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sandie Cao The FML13V01 board from DeepComputing incorporates a StarFive JH7110 SoC. It is a mainboard designed for the Framework Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001. The FML13V01 board features: - StarFive JH7110 SoC - LPDDR4 8GB - eMMC 32GB or 128GB - QSPI Flash - MicroSD Slot - PCIe-based Wi-Fi - 4 USB-C Ports - Port 1: PD 3.0 (60W Max), USB 3.2 Gen 1, DP 1.4 (4K@30Hz/2.5K@60Hz) - Port 2: PD 3.0 (60W Max), USB 3.2 Gen 1 - Port 3 & 4: USB 3.2 Gen 1 Create the DTS file for the DeepComputing FML13V01 board. Based on 'jh7110-common.dtsi', usb0 is enabled and is set to operate as a "host". Signed-off-by: Sandie Cao [elder@riscstar.com: revised the description, updated some nodes] Signed-off-by: Alex Elder Signed-off-by: Guodong Xu Reviewed-by: Emil Renner Berthing --- v6: Dropped all node status disabled code Enabled usb0 and set its operation mode to "host" v5: No change v4: Changed model string to "DeepComputing FML13V01" Changed dts filename and Makefile accordingly to reflect the change Updated device nodes status, and verified functional Revised the commit message v3: Updated the commit message v2: Changed the model and copmatible strings Updated the commit message with board features arch/riscv/boot/dts/starfive/Makefile | 1 + .../starfive/jh7110-deepcomputing-fml13v01.dts | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13= v01.dts diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/st= arfive/Makefile index 7a163a7d6ba3..b3bb12f78e7d 100644 --- a/arch/riscv/boot/dts/starfive/Makefile +++ b/arch/riscv/boot/dts/starfive/Makefile @@ -8,6 +8,7 @@ DTC_FLAGS_jh7110-starfive-visionfive-2-v1.3b :=3D -@ dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7100-beaglev-starlight.dtb dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7100-starfive-visionfive-v1.dtb =20 +dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7110-deepcomputing-fml13v01.dtb dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7110-milkv-mars.dtb dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7110-pine64-star64.dtb dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7110-starfive-visionfive-2-v1.2a.dtb diff --git a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts= b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts new file mode 100644 index 000000000000..30b0715196b6 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2024 DeepComputing (HK) Limited + */ + +/dts-v1/; +#include "jh7110-common.dtsi" + +/ { + model =3D "DeepComputing FML13V01"; + compatible =3D "deepcomputing,fml13v01", "starfive,jh7110"; +}; + +&usb0 { + dr_mode =3D "host"; + status =3D "okay"; +}; --=20 2.34.1