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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b331b0d44sm281127966b.187.2024.10.27.07.36.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:36:57 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv3 01/22] ARM: dts: socfpga: fix typo Date: Sun, 27 Oct 2024 14:36:33 +0000 Message-Id: <20241027143654.28474-2-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241027143654.28474-1-l.rubusch@gmail.com> References: <20241027143654.28474-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" A semicolon was fallen off the wall. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/ar= m/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 6b6e77596..7113fe5b5 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -169,8 +169,7 @@ main_gpio_db_clk: main_gpio_db_clk@74 { =20 main_sdmmc_clk: main_sdmmc_clk@78 { #clock-cells =3D <0>; - compatible =3D "altr,socfpga-a10-perip-clk" -; + compatible =3D "altr,socfpga-a10-perip-clk"; clocks =3D <&main_pll>; reg =3D <0x78>; }; --=20 2.25.1 From nobody Mon Nov 25 12:17:15 2024 Received: from mail-ed1-f51.google.com (mail-ed1-f51.google.com [209.85.208.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49CD3166F25; Sun, 27 Oct 2024 14:37:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039823; cv=none; b=tSNTzYEFooO1w2ebc4UWD/3K2Rzgn9Q5iS30UUj4x9kFg1X8cjl5bW48DWvfqeqUx/8gxbDHdQIq6vn1p+rWQI7+0pXO5NsXzhYwCMR6bAHCsMvi3a963vtaPi9B/fGAPhdHB8EBYQtRTObAgDSlr/YfhOaspsVjgavPrSFvZc4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039823; c=relaxed/simple; bh=McMTyWzS0Bg4WFWkM4x5Eq6n8AM1vXInQ676orlwBs8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=CpbF8smzrBZ/OGGTlpea4ISPFhSXzjtAIc2Q0azyqEy8s1jna+xxsvx3Dhh03JO1yLqpDGTi4kJUYBtlGwWW8uteApLx04qtTXcGAo1B0OSIcAV/w8e8T39xHAjndDU/8FHFfJyjSDXmkAgdOCMJpPGgffiIqI4EgxwI841ICwA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=DKsQsLv4; arc=none smtp.client-ip=209.85.208.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="DKsQsLv4" Received: by mail-ed1-f51.google.com with SMTP id 4fb4d7f45d1cf-5c94c0bf354so470419a12.1; Sun, 27 Oct 2024 07:37:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730039820; x=1730644620; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a7BTF2QgV5p9nNttdJyKFEUTkRzHJB1L1AnxAUE0mKw=; b=DKsQsLv4PmC8Fht2+m4ReXBu4RDhB1TY0ZJr2Vx0sI/uW7yhxvCyzvSWPopcLVvwAJ uAKL0s7tTPPf0JHgl6d4cFpQcNx69xENW8fKu+qODSk5l71jX1PSxXmOrIbC+HNfqbMx 3t22qjrY59W+wYxytcumkb2GqP/xXAVBdtzDZZH8wOlpzxmgKkzv/qD3UCknBz6AeeJI nUcXRSJ4wGoeCkc/uusiSZTRMf/12+L6Deui85sDO5MMGA1jpLJay2R6gP/LbjN6ET4p uoOkbW+4f5Dzv1ZNy2k443GBmCLaac29tAeP1tpvrXaFi1AwIUJcEWStnTvwC6tbRvDR 1Gog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730039820; x=1730644620; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a7BTF2QgV5p9nNttdJyKFEUTkRzHJB1L1AnxAUE0mKw=; b=CeuK1AsNMm6TzoeoJTFIPpRH/FXLPgZz0BwV66PSoyRvUXVR3Kmtr5NxcHLpnN15gm kM5ShfkqDdbiL0j/3beuLQtMGRGHBeRO9rogX93F/Z0GYqq6e/qyGcvxSmobevfdEndT i+3cJwv8mBrNQilXTm2sL6U7AMWe5WN7oBPja+99XyeS1PrUf1Gk9OdSJnqx3yNLdKi7 9HBl8oWrFX1dp+FwHVxmCRKB2zmjRVtHFiyVdNTonnO0gUCZYQMnNPDmMmXUoFdw6iBr 33iH+fcyi5fbLmJCdj3Mv4jL4/n6s/r5K6Emu9DoclHfY6bmVjOfVLjfyWzzBZrN0fsL cWrQ== X-Forwarded-Encrypted: i=1; AJvYcCWy58lP44PdOEt3e/rfAnSdqRv44GdyyAX5qKwscuIZIwRFflwfSa1V/G432p9ihQMV3q7SYaHcjw/3s99C@vger.kernel.org, AJvYcCXey1EIaXMKTkfamYYAQPtWsbR8kCuwGt1O1Xu/aMnkPRJO+e3J2IvnT2lILzhkH2WAPKoUkmKazvLS@vger.kernel.org X-Gm-Message-State: AOJu0Yw3rBCsBCz41mOfa4OuHVbLfgL741sPKKzt51yXvDMLkIrRQGjM 7vYtZhgT/KE9xtU8b5cJAJCK/xHldDvaa+eSRsALgTs3vEEe8Ak+p22qkA== X-Google-Smtp-Source: AGHT+IH213Vf8xr6wl/OZIsTWCpbeibIB0rD6ONpIkkTnKmu+a97JWDkMnauVcg5HcMoNrcqrcpmrg== X-Received: by 2002:a17:907:6d24:b0:a7a:a33e:47cd with SMTP id a640c23a62f3a-a9de5fa6a7bmr212086966b.8.1730039819577; Sun, 27 Oct 2024 07:36:59 -0700 (PDT) Received: from 6c1d2e1f4cf4.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b331b0d44sm281127966b.187.2024.10.27.07.36.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:36:58 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv3 02/22] ARM: dts: socfpga: align bus name with bindings Date: Sun, 27 Oct 2024 14:36:34 +0000 Message-Id: <20241027143654.28474-3-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241027143654.28474-1-l.rubusch@gmail.com> References: <20241027143654.28474-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Binding expects the bus node name to match bus and not amba. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 2 +- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi b/arch/arm/boot/d= ts/intel/socfpga/socfpga.dtsi index 35be14150..c7ba1e4c7 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi @@ -62,7 +62,7 @@ soc { interrupt-parent =3D <&intc>; ranges; =20 - amba { + bus { compatible =3D "simple-bus"; #address-cells =3D <1>; #size-cells =3D <1>; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/ar= m/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 7113fe5b5..7abb8a0c5 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -54,7 +54,7 @@ soc { interrupt-parent =3D <&intc>; ranges; =20 - amba { + bus { compatible =3D "simple-bus"; #address-cells =3D <1>; #size-cells =3D <1>; --=20 2.25.1 From nobody Mon Nov 25 12:17:15 2024 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C0EA16F8F5; Sun, 27 Oct 2024 14:37:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039824; cv=none; b=dW4LAdwTG1R7eNeMHfVlIVLABZjkdw6wyZcuQAwSsfsCFY3/Q2V+xhQrWFPeXIxmVtPGOYxwEhTgIZUMsU/8iUfeYnPJnnveZxmePcSISBO1A06agUP0aKcpulNciu2/dwi42wmLT+OEmYaAki2qdxJ99/+5emfTiNWL+c6Fw5w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039824; c=relaxed/simple; bh=zUAJFmmnkJAWnOviaASwhwRRUPKQVvu8A4WKyBwFSeg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jfh+tW26SHz0MwVlXcF0WiOU0Zq2MhIXiz7Sxdscl+XNGy1L5NEjIXKK8251mtoA6RyMlJ8QX6frPLzGB126r5TtZMT4va7QemgwAOFlFjQlbZ8HDaDyvy5aXkWDMnVD4OPyL6cxuvV/anWmFEmPZuJtSwYbuytChI/yCuo7A70= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=iN386mQY; arc=none smtp.client-ip=209.85.218.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="iN386mQY" Received: by mail-ej1-f42.google.com with SMTP id a640c23a62f3a-a966de2f4d3so43926366b.2; Sun, 27 Oct 2024 07:37:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730039821; x=1730644621; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qk9braQhcUfjQhD1zhHgydTWlqcLCgBL7v99PtqcEgk=; b=iN386mQY2Xvev7/hWjgHdXYsvHKHOC+24pMc5P+4u1nFclX+n9p8LME6HOxYO6eEkX D1c89AlZMcLkQUFsMpCYzp2t6W3QDAVqOusRtRmw4YPfh0sH2sW1XPzOpn+e2M+voa0m MYdAxQNJnnTKbKZWZtAmhfB5Yw9h1LGT4b7p/QL3UZ1FirDsS7AeuMs1xTr+kDlaGFNT GSu1QZhKSkpvDY+imyYj1znfiJtigyBdfHYiIcn8UkOkcQZK1AUpd52aBI028LHh9xoz b/m8ATIpU4g+bK6k7M8YUYOXvHi/Y0U2wSbJ0YnmHhaXoykGBpxpEZ6Ub9mh1N9rTcxu /COA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730039821; x=1730644621; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qk9braQhcUfjQhD1zhHgydTWlqcLCgBL7v99PtqcEgk=; b=gZDDi0jJL3oAguRdSd7gcFBMS6XcmwzNVFuyLQU7r120dWxG16DmB38eUI6Z/YwZCU /iuKd0brp7Q2j6wveQiK7Wr2wvvSUoIo+qmCPbtmtpq6JI2Mwh+2Kagudi0Z/p6hQtzj PfJvnbvajnjUKzekiZXwsxF8KaHjzTFZ/vJnU7yqSh5mFRLy+UpJbaHNsGvvXor9frAd pUVEgaO7A8ynvtALbnDnqzmGkNrOvW2H0QR0QPIx8P9240vTAFUnXaxQ2ESGA+ui7X49 gJ0tbY+CeU9A2JX3s4sOTjYDofmjYdkFrQZmuRnk273FH6HZ4dpNmHPBuicqq8BdhHN9 m9sQ== X-Forwarded-Encrypted: i=1; AJvYcCUSMQR84h3xxuSMXnf7u3Io1LkFhCRLl5yLb1yD8GbKOplcgfI/s6+hcP+VsYwzA1aKwHIqa3KI69jA@vger.kernel.org, AJvYcCWOG5x5vjP3YAXkjYPqpAQCeEtMCrc+7cfaxImmXGqmNOZoBpfX3I+fEtEOetD3xi2T1wCVbWEceYFheq1x@vger.kernel.org X-Gm-Message-State: AOJu0YyiuTllfhP+BwME8fwgJ1H+vXOA59bYpWiyB7iK65kxqdnscvZK iFA1O45Abv7qp8heUUW70byBEAWacoR1H6e3lrESOAl/FT9ggs/k X-Google-Smtp-Source: AGHT+IHNWv59mwrCGUavlqTnI52sw88LvxT0FqNsinS2oUZgdblwk8PiTWZgC8Ext0fYq+Mr2AgMTw== X-Received: by 2002:a17:907:a41:b0:a9a:cee1:3cc9 with SMTP id a640c23a62f3a-a9de631d910mr207252266b.13.1730039820623; Sun, 27 Oct 2024 07:37:00 -0700 (PDT) Received: from 6c1d2e1f4cf4.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b331b0d44sm281127966b.187.2024.10.27.07.36.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:37:00 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv3 03/22] ARM: dts: socfpga: align dma name with binding Date: Sun, 27 Oct 2024 14:36:35 +0000 Message-Id: <20241027143654.28474-4-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241027143654.28474-1-l.rubusch@gmail.com> References: <20241027143654.28474-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Binding expects the node name to match with dma-controller. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 2 +- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi b/arch/arm/boot/d= ts/intel/socfpga/socfpga.dtsi index c7ba1e4c7..01cc5280f 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi @@ -68,7 +68,7 @@ bus { #size-cells =3D <1>; ranges; =20 - pdma: pdma@ffe01000 { + pdma: dma-controller@ffe01000 { compatible =3D "arm,pl330", "arm,primecell"; reg =3D <0xffe01000 0x1000>; interrupts =3D <0 104 4>, diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/ar= m/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 7abb8a0c5..aa0e960a3 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -60,7 +60,7 @@ bus { #size-cells =3D <1>; ranges; =20 - pdma: pdma@ffda1000 { + pdma: dma-controller@ffda1000 { compatible =3D "arm,pl330", "arm,primecell"; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b331b0d44sm281127966b.187.2024.10.27.07.37.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:37:02 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv3 04/22] ARM: dts: socfpga: align fpga-region name Date: Sun, 27 Oct 2024 14:36:36 +0000 Message-Id: <20241027143654.28474-5-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241027143654.28474-1-l.rubusch@gmail.com> References: <20241027143654.28474-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Binding and setup expects to match fpga-region instead of old naming. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 2 +- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi b/arch/arm/boot/d= ts/intel/socfpga/socfpga.dtsi index 01cc5280f..1562669b3 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi @@ -87,7 +87,7 @@ pdma: dma-controller@ffe01000 { }; }; =20 - base_fpga_region { + fpga-region { compatible =3D "fpga-region"; fpga-mgr =3D <&fpgamgr0>; =20 diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/ar= m/boot/dts/intel/socfpga/socfpga_arria10.dtsi index aa0e960a3..90e4ea61d 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -80,7 +80,7 @@ pdma: dma-controller@ffda1000 { }; }; =20 - base_fpga_region { + fpga-region { #address-cells =3D <0x1>; #size-cells =3D <0x1>; =20 --=20 2.25.1 From nobody Mon Nov 25 12:17:15 2024 Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B5B417BB0F; Sun, 27 Oct 2024 14:37:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039827; cv=none; b=IgdJLU62wdPwSFLz4lqv6CbsLsCzWDvW9x+eHkeKMqjQ9Trbkr6hNAtwgJqOGEp9OpGIygS92qvwNgWcbKBeufK9cjWuIDXc3ErK0a90lV+sP75zVIyIMGJ6mnw8jMXDiTMotzrUXl+rSzucdCZ0s42sGrFYlRW2lfi1ux/9Nu4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039827; c=relaxed/simple; bh=V2yl4lNntEuPEV0X2MVL+IE3GiZVw/y9HCOf0Pz1aTk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QFNe0Cp3Q7HvSq5ljobkXkFQtnkaUSmT/C4GH59hExxJ4qjPa+8PkmnAR4FVdrlxh26RR9s+mmfDNihKUMK00FSnVHlQSULk6k+Ce3sU5PtXpnBHT4uoIp9Wg3Y/8THYIikQlpRBsrzsH9wumvAmOJ4pwdUA4upWtwnazvsONro= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=KbP65hSP; arc=none smtp.client-ip=209.85.208.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KbP65hSP" Received: by mail-ed1-f53.google.com with SMTP id 4fb4d7f45d1cf-5cb991f265aso606201a12.2; Sun, 27 Oct 2024 07:37:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730039824; x=1730644624; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9wwdH5E3n/FKvtFIFoeUG2vP8wssuIiUjkTOLgVYvdE=; b=KbP65hSPNYKPV2q3ZrfosXlt2OgRmYglSwAVWbtYJ8W1FFd3KmY1/RoetFElVvanAM P+MHehjImvnoOVC/vNGrs9YPrXRmfCWTFgnCQpFCQYxE1WVOd3b06wvpJeCVOyYfYWwg 8RH0Xc9NDFHRTmFZ9Z2W16+Hwg8oj8Xvgz4TWZ5UEuKJAZeI566RnyQDk061OYswb5jo khY80b73q2qW376vYJq/p+uZB6xrJVrw8GTYSbhyhJAQGWgO+eD/Nk91w8OsiyzLK9Qp ZZmBR69A162kRvhxTzXBOSpVDTtDzN/FcgM7NQQiiYIUWiqIJY1jyJvdSUL3rCtDmlOB dgzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730039824; x=1730644624; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9wwdH5E3n/FKvtFIFoeUG2vP8wssuIiUjkTOLgVYvdE=; b=hvaGSnTCkyhvZlwbQXZfiGrY1y9tSewqlx5y4brgMe7a6YqubIc5mShEg3kMBlmvOu SRqERKwpw7MYsFKOgzg7o6SOcwt3ukXdtZ4ftxevwzI3i86yKyHPTERn76TKP51h9TpM dNrQfoYHYITWEwBZFgRF/09p4oBApnw8H7SRgPNcwAvW1CM1GdPxAMOPSt4CoFcHUWrf 6HctN2rPiv138oWHIr7iOeCRnupy7Gw1wQBxbHDOUomZDq0mnLzHR49ZyhS9WC1C9Nie /VjI9f9fboXkmXuzrUT0MvNynVzPFhd3yFFb378vcv3ulcjc9kMl0O/w4PSxqQmrNnA3 WFsA== X-Forwarded-Encrypted: i=1; AJvYcCU0NC3TNh5tALBTsn9lFz9542t+3nNV0YP4+ui84VQPEnUsrrsssbtzkhFVm3Qab9iZNYo57M9ZqveQuxrP@vger.kernel.org, AJvYcCVJSJ+UJdYoo+XjAVEzRhIgxmm9Nb65MhzHnggfk2IcWDDyp6ilIYoS6zOaEMSiqOpR/eyzKjoxxlQX@vger.kernel.org X-Gm-Message-State: AOJu0Yw80Uz8IPJC58PH3rElRkaA9Olp9ErLdEGvfZMuvDueWp02idZR UGj1Bj1FyO+RQwjz0YfUNVfFoZ+n6BWioaqQiuJhKUOzhgnnFXjU X-Google-Smtp-Source: AGHT+IEcHq6ID7YTtz8muc3a2G7bHYg93FDPSlg+XYSAewEbpQvis45pEdsc308nxvWHdXiJyKN/gg== X-Received: by 2002:a17:907:7f0a:b0:a9a:8216:2f4d with SMTP id a640c23a62f3a-a9de5cd2244mr169957066b.3.1730039823488; Sun, 27 Oct 2024 07:37:03 -0700 (PDT) Received: from 6c1d2e1f4cf4.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b331b0d44sm281127966b.187.2024.10.27.07.37.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:37:03 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv3 05/22] ARM: dts: socfpga: add label to clock manager Date: Sun, 27 Oct 2024 14:36:37 +0000 Message-Id: <20241027143654.28474-6-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241027143654.28474-1-l.rubusch@gmail.com> References: <20241027143654.28474-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Devicetree setup expects a clock manager label to be around. In preparation of upcoming changes to allow for compatibility. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/ar= m/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 90e4ea61d..7f7ac0dc1 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -88,7 +88,7 @@ fpga-region { fpga-mgr =3D <&fpga_mgr>; }; =20 - clkmgr@ffd04000 { + clkmgr: clkmgr@ffd04000 { compatible =3D "altr,clk-mgr"; reg =3D <0xffd04000 0x1000>; =20 --=20 2.25.1 From nobody Mon Nov 25 12:17:15 2024 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 270EB17C7CA; Sun, 27 Oct 2024 14:37:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039829; cv=none; b=higG9QmXRR05t4IQVSgRzg3UZkKrEzMkBvkq/QtMAHYTaAuU7QnosJSgbMw2N8WalXd864euVBOL52QTMdhxYsgpLTSuSzK/nmo92KGFv+UjoI7n0OKs0rBe73v4Xj71ASD4WTaiAER1fnMnaVlICMuNz2FUWGHgw1KUfUfySkI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039829; c=relaxed/simple; bh=OtMc8F1P0PTrSTV9GAwD2G3wO6F1jpiSdyrg5IQ28zs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LzPWb1RYZxlTnuGtFgjBE7EoD8pgzu8WT6fYkR+BlgYHmjlEFsDikndSlPSX9nXCvRQ1qTTSq3o1Uhu9Eb3m5qp+tVROJHgDZeDYq0U8yMQSgG05ycWk5E8IcenNtBmg6EApE6XtNDfkgJZ5NTnjauL7TW3rVBEqCYBCSeTR4Iw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=kt2jTpu7; arc=none smtp.client-ip=209.85.218.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kt2jTpu7" Received: by mail-ej1-f47.google.com with SMTP id a640c23a62f3a-a966de2f4d3so43926966b.2; Sun, 27 Oct 2024 07:37:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730039825; x=1730644625; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zykG5xT9htU2beqODKL0ma8uO47wG8f6mRcFvD55rTU=; b=kt2jTpu7H7Od9SE9S/USh7wVyhJiPO5JmfuKfbb+Zp/NgmAvg9RDyVD80rtlO9Ifcd BMOUouzdCZDfLBOCBWAixSvRpgf47gYAM8BTa9cM1i3cCEFHrdrf9+9vJ7q9uwODPPt/ N3AntTyNHJQLc86O+sitRdxXK2MiuEfHyrqq6ffq27yD0aQMU0y9qvMWjnk3vWA1U0/i iutbjeVaWZATla30aHbr7wIMpR/Yo4FuBct5EC/EbyZFcuT4sx9CoiDQytclfrw9aFAy CjeqU2123Mdwl4XYWgxF/P7mZXWkb+uXqb751sfJ3QmZ6HgpJd6q0eN2Fg7CvdTP9UOE 4MRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730039825; x=1730644625; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zykG5xT9htU2beqODKL0ma8uO47wG8f6mRcFvD55rTU=; b=koiArjZBz5WE+YZgdinw2UBsUPFeghAwczg/xH/JPmu0cTlTEiiNQXBs1WdAIlZfT3 1+GzNh1t4bsHUTdTXma9JwsJ95x3x3Nj8ZZA1ltnYYKYE53XIVu9AKiWSIyn5YVw6gRC 4+sDoETr7jPvKm8N6kaXK/jEqk21LyxYJ8Oft3cB4Ec5Z+i3aVBnPHHyo0PypYi+/GFY NqIo5ur90GwETlzI6tE7ITb8EBJsmPyGxFQFFqDs3TkniQ+9GPZMrYBC1X38CyKPTfGC Up4ctnE5qfQqq1p8mXZ8YtANvckawgRsFjAdvskVjl6y1xtjW9bylEDl6PmpMYePrOyB tprw== X-Forwarded-Encrypted: i=1; AJvYcCUP/lKNZ+K/U89B6yv5nz+Y+U2P0Jdf/kG009IK6eduPuuE18+rtvhG2L8udozXOuHh3QHg+OR7ktrVH8PP@vger.kernel.org, AJvYcCX/Mv5zuzAQizOVfLU7DN1nKCgjDcTNdqcI2pBbyWgEBY+XdhdS7MuFSkM3WuUu4eY76vRSlGHVDtSC@vger.kernel.org X-Gm-Message-State: AOJu0Yysom9zc4rzyjC8mC7LWVyppBIiypqHa4Vgqgw75bsqgSg+ipyR kAYX/FiXceV7QXaxwHBm0C8NIKGXvCYgKBlsfDVnJngmsY3mMLqL X-Google-Smtp-Source: AGHT+IG80f5DbgfZu1EssjWcBVSD7TKjNuwHRHvQM+3EHA3QJl8++utETn/JSBaSgAeMJJ6bjjTUcw== X-Received: by 2002:a17:907:7248:b0:a9a:6700:1ee5 with SMTP id a640c23a62f3a-a9de5f04372mr189557766b.5.1730039825333; Sun, 27 Oct 2024 07:37:05 -0700 (PDT) Received: from 6c1d2e1f4cf4.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b331b0d44sm281127966b.187.2024.10.27.07.37.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:37:04 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv3 06/22] ARM: dts: socfpga: add missing cells properties Date: Sun, 27 Oct 2024 14:36:38 +0000 Message-Id: <20241027143654.28474-7-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241027143654.28474-1-l.rubusch@gmail.com> References: <20241027143654.28474-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Binding requires size-cells and address-cells to be around for the SRAM. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/ar= m/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 7f7ac0dc1..4b19fad1e 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -684,6 +684,8 @@ nand: nand-controller@ffb90000 { =20 ocram: sram@ffe00000 { compatible =3D "mmio-sram"; + #address-cells =3D <1>; + #size-cells =3D <1>; reg =3D <0xffe00000 0x40000>; }; =20 --=20 2.25.1 From nobody Mon Nov 25 12:17:15 2024 Received: from mail-ed1-f45.google.com (mail-ed1-f45.google.com [209.85.208.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02E87166307; Sun, 27 Oct 2024 14:37:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039829; cv=none; b=P3Y+CPh8BaYIbIDMhG9183VUDsZRME/JK/qiddXtAnZPhVDEeaItB8/VLLvDzI2aCwxyHi5tVlzkISR5DTmoNEOsc7i6msE4v9ShQLlLqL2QSh80xAHN0UBYYR77+H/qjdJEfTiLWGy5P8A0iBzrULEgdC/mFb7Wf4s6gf0xOMQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039829; c=relaxed/simple; bh=1KzJp/fai6aB837Tp2XCYOTjK4FVSS8lCtpXFfw4Wj0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gL7TgkSGwl7I+eZJbPhC+n6THaJ6MhJx0TabH7CzHewlYF6scatONeYSXA8cQeCxX0ZlP+X1UEKnEfUlmvrpGVNO0Ojj8aYQrB/liLlf60i9yll65ebZ9w3XAHEZSgiMieguU8SykCHDOlhMyFXtcM+wBJif//gGpwEh2P2j084= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=EWtNCt7C; arc=none smtp.client-ip=209.85.208.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="EWtNCt7C" Received: by mail-ed1-f45.google.com with SMTP id 4fb4d7f45d1cf-5c93346dfc8so439942a12.3; Sun, 27 Oct 2024 07:37:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730039826; x=1730644626; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=syqLQEEuQIy2cda968KqPmvPAkdMXpl9TyM7P/fgr+8=; b=EWtNCt7C/Zb8x9o9XBO4C8pf5wPK9o0ENaQVOIMBYnFetJfEBS6MfW+YdnZlETFgct 6QJ6eyTa7Sy6LlTGw1Pt+/dXecYhB2jWLO7ixGq1mxJmrSf8noR5fpBVlGhyO9RSfC3F 2u4AWtE5q+O/a4vvs0B2hU/rcaudzLExBhKksekCv2PRn6c+vfMFIqJqPfVwNmHQp03v sJhBrN9irJaKzzXb2TgztMnDaNPcE8kfMbkVwsTfi/1JY/AhukbJjTumvqvFXiK7QzNK KKPSJ7iSe6raNkUjutqyqfHQ19xZTrHNRO68g4X/Vwp2ViJyqpMyyNuScSPKw0MQ9EMi r7uQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730039826; x=1730644626; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=syqLQEEuQIy2cda968KqPmvPAkdMXpl9TyM7P/fgr+8=; b=ElGG+uZn3gfeNOfddL19kGiUtMW8ERy4m6o5CDyE0sY+cKFN9QbBISuHVn8uIsxvnQ qbJ2tOBK9oZ7+pUTHc/ApL5uawvkWLw8JzgxE2t2Jzg6oVsmZb4ETLls0CqJ4pCLsBPJ CWkpyy8vxSHjvExdLcOz+1zqpGmxOc3gACIeGAmD9gpTqvJCS8f+eQHYHj6MaIVys/vH vqq8eTnb40tBGpj7uxPB8qR4ndgZphyu9zknBBsUWDWbpvjlWKxNqMvG8ZJZN1BtEuoq Qv6IcuJl6xcYJ4vAFxMqO4sEl4w0QPz1jToTsahPl4RfHX6NTXr3YjYj5Tsfe/aKJ5iq dYxg== X-Forwarded-Encrypted: i=1; AJvYcCUSVM8L/y5cO+kD0JcAzftQhKh7pWyUsxziRMatjaCOwvjtGTJuL/fWnhmMpZiHxO/dIEmSBEVqblwzZqMA@vger.kernel.org, AJvYcCWr9Q0YTrTM+BtQW+eaSL29RZiKOzOp4ak/Yc+RxcK2cvtu3cet2cA65+whNbtfbyU4LKOvVWkM6/wi@vger.kernel.org X-Gm-Message-State: AOJu0YwQT19BxWwFweYy5XbGo71LpBhgREHAdPyV5JWZxlOEsbZFWrgQ Vd1d7pneV3aWffrSWG8alIOC9LzzNrsXyQihoa/UGmPYr6ihuJO99izPmA== X-Google-Smtp-Source: AGHT+IH7N+ec9fuWlTgo+hObp1OYAFN6tl1TIuPS2k3vhGrnYICKxluiit2A4Irm9+Hg7SIh2zYp5g== X-Received: by 2002:a17:907:74b:b0:a99:fbb6:4956 with SMTP id a640c23a62f3a-a9de6175f57mr254372566b.10.1730039826379; Sun, 27 Oct 2024 07:37:06 -0700 (PDT) Received: from 6c1d2e1f4cf4.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b331b0d44sm281127966b.187.2024.10.27.07.37.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:37:06 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv3 07/22] ARM: dts: socfpga: fix missing ranges Date: Sun, 27 Oct 2024 14:36:39 +0000 Message-Id: <20241027143654.28474-8-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241027143654.28474-1-l.rubusch@gmail.com> References: <20241027143654.28474-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add reanges, since by dtschema 'ranges' is a required property here. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/ar= m/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 4b19fad1e..65d04339f 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -81,10 +81,10 @@ pdma: dma-controller@ffda1000 { }; =20 fpga-region { + compatible =3D "fpga-region"; #address-cells =3D <0x1>; #size-cells =3D <0x1>; - - compatible =3D "fpga-region"; + ranges; fpga-mgr =3D <&fpga_mgr>; }; =20 --=20 2.25.1 From nobody Mon Nov 25 12:17:15 2024 Received: from mail-ed1-f51.google.com (mail-ed1-f51.google.com [209.85.208.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A69117E8F7; Sun, 27 Oct 2024 14:37:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039831; cv=none; b=evHUJ/zxfILfsNAMOVrTewTIZFTWzvm/LPQNQPxb6v0teguwD3aVUzLeX8PQQLPX72kwkfLy8u/+MlGHGXFbwiQ0pqSqi0aK9vgmiTeMicJaqYld3hyY7Ia/JiiJMNK4sDSUPZsSaj5NjYLfM6OxYYzKK4rhMcUvrUvRH1dFb2o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039831; c=relaxed/simple; bh=y6S/vFniqdK8FnY4Owxt462kYlq+HMo/27OIQpdXFyk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=q9kCn0KFylzBWGI/DQSImvAuJU8IOxGZWs3Y9X67e9TzBt7MmzJObrXLeR3CTq83dGQ/7RrcRZEEjJa1PdMdj8cM21oC3LDndd/J/MLg3iqnjzt9ZWWype3wzM12thNn+K5FGucOrwkMkB2K8B4j3agVMbh6nViciWJ/L4E8OzA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=GSxuJUYR; arc=none smtp.client-ip=209.85.208.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="GSxuJUYR" Received: by mail-ed1-f51.google.com with SMTP id 4fb4d7f45d1cf-5c8ae7953b2so623883a12.2; Sun, 27 Oct 2024 07:37:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730039827; x=1730644627; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QbnDXxocaCyheHFI8hTECOWKPKoXgfCmEGz3dctI1es=; b=GSxuJUYR1w/+nE6xEifphPlnP2cqHk9LZZ+EQpdeJX7JlWk4w7+G9EbqHCFENWBae8 qU8q1zsW68GmBkWROmmCOjySmXqv9d3T5nevnIGKIv/EsUW72UEsfes/QNRSFuWG8TEw S6NRz6ixO4MOByFuKJYDPlp1agjdC9dNPlbwva+hKRkCJJJmHJ0mq70WsLa9Kb8fwNeJ 1UuRxIFgUqqLS4fQF1o1nhFXToS0qXANay/8cajkfe7OPg6ZArfLHSkgkwM2Q2/xmqfD X05tamrIJP7xYaeK2fnzLWiSrZH1e2B9yQL5fB6WHIVY3C0EXKoh6Cx8hIQGKoNmhvZg pIgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730039827; x=1730644627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QbnDXxocaCyheHFI8hTECOWKPKoXgfCmEGz3dctI1es=; b=nogW9RB59O4ChE3EwVZDQstFJxrz06B8bSQOZ5sGE3mNTPCHqIpMPfCltgrzK7VYWl EcgbIJr81dM66SmjVHrxyj7Co+bmAphh3ccEuyLYIVpHZmZIfC6cZ2EzludKhwu4u/3r EYEVErg+xXkpw6lZsgf8eaAvV91msUYy/Ou7QGb3PTWj/RHfxBIro5KpIzcF/Dg/2BHm 82R8/VN/qWtEFER7II0lDLpMvqk/lWfxCmvQ16q2iPcBjpMoE/0NJiT+4qBTLjdRXxvm 9IfQKF8HIfrJIKcdyx8IdJurJyN6hj1Grs0jUxs9EOcXJE9zWhyar4BdjNwNeGSsk0JM KaeA== X-Forwarded-Encrypted: i=1; AJvYcCV/vPF9/a03X8bA6iNaZDHucnyt4wwuiZjc6HTd3kdQaV++GHBebP8DJsHec0/rQpFPi4AJSMLmN+Rd@vger.kernel.org, AJvYcCXsyqyhplc2uALyOWAij0RjyxWUuK7p4/ppRa5AnAMl28BYJxbzDX78V2NWRTS5zk6uMhX74d3AFsdz/2yq@vger.kernel.org X-Gm-Message-State: AOJu0YwxjL8nbmzOzO3ViPFrmhVaY10qhUxMA98+rhE7wVjs9Oiunca/ usi35qXs2KIe+bNQE0zPIHjYnYfPjhdujf79I60g2ezB2joYdBGU X-Google-Smtp-Source: AGHT+IEk5d8ilAP9HXUoi9ltelUyJjo7yA0FxnqN/Awpr1Z6PWz0JcVNNeUn5+0cnQdPMPL+z10MBQ== X-Received: by 2002:a17:906:d554:b0:a9a:130e:120c with SMTP id a640c23a62f3a-a9de631e898mr229491666b.12.1730039827396; Sun, 27 Oct 2024 07:37:07 -0700 (PDT) Received: from 6c1d2e1f4cf4.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b331b0d44sm281127966b.187.2024.10.27.07.37.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:37:07 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv3 08/22] ARM: dts: socfpga: add clock-frequency property Date: Sun, 27 Oct 2024 14:36:40 +0000 Message-Id: <20241027143654.28474-9-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241027143654.28474-1-l.rubusch@gmail.com> References: <20241027143654.28474-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add 'clock-frequency' is a required property by dtschema. Initialization is open, similar to agilex devices. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/ar= m/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 65d04339f..5f4bed187 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -99,21 +99,25 @@ clocks { cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { #clock-cells =3D <0>; compatible =3D "fixed-clock"; + clock-frequency =3D <0>; }; =20 cb_intosc_ls_clk: cb_intosc_ls_clk { #clock-cells =3D <0>; compatible =3D "fixed-clock"; + clock-frequency =3D <0>; }; =20 f2s_free_clk: f2s_free_clk { #clock-cells =3D <0>; compatible =3D "fixed-clock"; + clock-frequency =3D <0>; }; =20 osc1: osc1 { #clock-cells =3D <0>; compatible =3D "fixed-clock"; + clock-frequency =3D <0>; }; =20 main_pll: main_pll@40 { --=20 2.25.1 From nobody Mon Nov 25 12:17:15 2024 Received: from mail-ed1-f47.google.com (mail-ed1-f47.google.com [209.85.208.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 954B016BE2A; Sun, 27 Oct 2024 14:37:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039832; cv=none; b=Lq62rJrLGR7jgCTk08SO8PicDnfVLfPv4bYT7pkiVw3u/7QXCO14ZkOe6Dxzi22vLMMi/lipMcmwKEfkKGhxmmFajzJxxeQGoeWDP4KTBbkT9KJEA0Oe//DWFqwx7F1tJe385BrbGHBG2V23bQ83zA52EGrA/k3M6nD46Ai1IAs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039832; c=relaxed/simple; bh=Ek3f9IntqkTVZaMM5+9uMLvwBlmFC1g5tii851ibiMQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=REjDBgo32GVp5SwdzwL1eQsLufKfRtqREhUWV7NsIomMoIJv2oCLlgNyl7xJ83u2z8GZFA9QVkrziy4zL6jn7PPOdBR2XLxquJEjAnXbx580/eS17QvdJZnoClycTP64iVm0QzwGg2+AEm0umUNczJWTGaG4Bb47dmzffnFFOdk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=NmGmZcDn; arc=none smtp.client-ip=209.85.208.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NmGmZcDn" Received: by mail-ed1-f47.google.com with SMTP id 4fb4d7f45d1cf-5c93346dfc8so439944a12.3; Sun, 27 Oct 2024 07:37:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730039829; x=1730644629; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JxrWAGvbebnl7bShJIljz1Nm6dGXiAY6T1E3WWpWzg0=; b=NmGmZcDnBPW6RlFD9QZd+ngfTQfXty53NxwB4i5mTE+yaZqhppHwPmHc4B7wXcgFEt /kWi095bvHrMQadWm6Y0z9ghFhMAPaSFcLUqF/CFmPmQULgLvM/dx5YtzeZyULUURfDK 7o3/q2oxdTnaKZdpiODcSV6q8GFEtirL3K9TFx2usfT/b1eeUluDXl0iU2HumYt/8HPu TngEYvEPD/4VLiEWpE5uzjFlScv3d4SeudT78gCPv2R3GkXdqoFTYNZ5H5IyHNY9RQn0 ZkOnrePdnODUAjviUnFLQo+0bjkNFB//aa6H3lEbMVknijzSmIaJELb6OP6sTZFEIqQX BPvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730039829; x=1730644629; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JxrWAGvbebnl7bShJIljz1Nm6dGXiAY6T1E3WWpWzg0=; b=JDREZylQuiymfeiHYYeCOPfJK+PD7gr8M6scv5F0Jze/koKA2qR7UusGtI6H31ItZt bq2baPGtWHsK2QfqaZzSntZG05DIhbThGL1KRjip65maA+TlnjLu9Wi7y2MsPGjXDxr0 zyN3+CJZPUXGnB0QTTkYLS6kU00xqp+RbgRvd5WUhZU6s2woLxNn0RgyKXgT6dm1S1LS LXLr/d6j8sBcLiFRDvztpFPFk1x2a301Pnm4q9jTjF8RUCZSLrchKhZ07wfkgZbhkAz4 KoiDju1g275GDM83Ig+1Uh2wHWlIMgSIPROxlad/pPIRL2U2D0zBGj4RlzNvdDdtv37q JIqA== X-Forwarded-Encrypted: i=1; AJvYcCUW025So2cPYxB7ufN9LqTE214/btFxILzV+fwpTmuzB5nqoo2lG3katOWwUvKq3Fa7Z/YBuafatcUv@vger.kernel.org, AJvYcCVggSe8U9oIq/oT/G7rdbCHX59JbYY9nEgRIWINFVWPIoWsO17k1pWhYSvyETtluSTwZSlo9kqWyshlMlXi@vger.kernel.org X-Gm-Message-State: AOJu0YwsN5o/kt1z3M1soHUUgj8wx55oGPakCIQpiBmMw4N2Y8daa0R1 x4D8S2eROIIJH5wUBddkdeY82VQPK/BS3NnYe9cTLTXD9CTogFvQ X-Google-Smtp-Source: AGHT+IETuQshlPZqNCPXWVTwiqOC89FiAISLisVuq0sLvAjg6bOHaNi5XZVV7rgtSNaIEig0IX+2mw== X-Received: by 2002:a17:907:7d92:b0:a99:5f45:cb66 with SMTP id a640c23a62f3a-a9de6175f4cmr239115166b.11.1730039828475; Sun, 27 Oct 2024 07:37:08 -0700 (PDT) Received: from 6c1d2e1f4cf4.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b331b0d44sm281127966b.187.2024.10.27.07.37.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:37:08 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv3 09/22] ARM: dts: socfpga: add ranges property to sram Date: Sun, 27 Oct 2024 14:36:41 +0000 Message-Id: <20241027143654.28474-10-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241027143654.28474-1-l.rubusch@gmail.com> References: <20241027143654.28474-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add 'ranges' to the SRAM node as it is a required property by the dtschema. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/ar= m/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 5f4bed187..6a2ecc7ed 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -691,6 +691,7 @@ ocram: sram@ffe00000 { #address-cells =3D <1>; #size-cells =3D <1>; reg =3D <0xffe00000 0x40000>; + ranges; }; =20 eccmgr: eccmgr { --=20 2.25.1 From nobody Mon Nov 25 12:17:15 2024 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B40118454E; Sun, 27 Oct 2024 14:37:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039833; cv=none; b=R+xiBF3tVf5sEdPvT9CCsffrp9wXX0qdVVUrs056T4yZGENpifZCIyySCi2a+1285bS3A0WridXVI9Cpo8HxgvyOhfhHlKS14vSF0i5MRioODWn1b2A93vGTP4CiwCgDHIIBPmk/yB0dVEpV2CauMoNiJR5IJYm35IYPDb/SbA4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039833; c=relaxed/simple; bh=GRIprTk55YoxyAtAqBSmeVlFwn+FJRp9HdXHznTSR8s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=WEfCGH8YCb7UFb22IcHNVVf5z1PPvlpmkf0YCj4N92i2/huXRdzjVa+ThmONYHxbTZfjOSuIuZMGtpogqQIoOYp+a5i/Z2f2m58mMlZFjQSUD1JboPAYdNIoH2xGEYNylh9jcVk8Lebz56Duw8ldBBjHkfj0KYHsFlemcRcMikk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=kI5LFX5n; arc=none smtp.client-ip=209.85.218.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kI5LFX5n" Received: by mail-ej1-f42.google.com with SMTP id a640c23a62f3a-a9a139be16dso60552466b.3; Sun, 27 Oct 2024 07:37:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730039830; x=1730644630; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vySvn0PrZ5KmWWRcUjB0f7ffbO3G5ojONpptbAIcwaU=; b=kI5LFX5nrR/utQGl7IKTN6qzeG4/rqE16+rTVa5apZswBLBTDLujyqsvnqmiU4qhG9 5yzlAEor000FIrQ/4WlA+Bi2f8UYJHtXQbwPLhXBcfvNcVziUadgozSFcH/077WqgDkw Q944eyhO3D+OgfuQB6Ye9AaDQx1LU8tZvnSQPqrG6bwjD8TQlUbn8chO9QblzHR9KTQH pUAk3UYjNdhfq7Ug067ieySFrl+jYRCWQid7+22z35EqVDfMbanuPKMkeC1phmgWWevx diXpFbBli9ooGB502FTOfzkT0bIzDqmfN6n5aUPUON8ywQFaLAdsNNvxMPKdjEKcPmh0 Mlsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730039830; x=1730644630; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vySvn0PrZ5KmWWRcUjB0f7ffbO3G5ojONpptbAIcwaU=; b=Z5WxsROoBtMH6E9Sahi0tHYfNL/vohqg41tLHHTRigYu41rvlx8jCAFZ4xEQGnLiSg CG1fW4SZZR+c2FCtL/z+RPQTxZOW5VigyqTuXQuyduSPqLwQaRJG81H9hv83XMc5TTDZ xyJzrrqY29emXvmTJCsYNE77D+bKgjLOPqRBzlkzdZGqfol50dGkSE3gA59s+cEyJQT1 7i8hAuT4iBMeDcdovFxll6adYJUxtxENzXpov1J64Fjnh6qTMfNtIM7gAUXFOQDIpEZw I/9kJqksqxyecpNjQFRnGwUELdU4zqb1N1Jeoo8QPiXc7cdqgJfFT023a3t1Oi7R5s7g UI0g== X-Forwarded-Encrypted: i=1; AJvYcCW1I/eTU3FtqqF3hcm5B2+yxqDpnYKDA9QwfUipdQLohH9rJBw1XljS4B8OxDMDxuilHBibcN7iS5VfbSzi@vger.kernel.org, AJvYcCWWJjQ6iCG4lzESUIdV4sEb7TD5S6aRCUndE6yOFGnYaV2LPWduTgNP6jB6nyUD62xPiZftJlD8vTc6@vger.kernel.org X-Gm-Message-State: AOJu0YwBT0/mzUVZkDUOzD7bdfBdq4cjlIP4/ONKjYKnRp91iPcJgHo4 hm4c5FEDPzn5EZVRBNxgglRb0ot4Pcx+xUsFS+6WuHFa+MXqE6zC X-Google-Smtp-Source: AGHT+IFAXiONUp26yPFBIGRc7AqsUWO14Tji/EirrGd9LrhYWQZ2CsNCNbqO9lsi2MZlqdRDu6d/5w== X-Received: by 2002:a17:907:7f1b:b0:a9a:762a:e5b with SMTP id a640c23a62f3a-a9de61abe21mr188707966b.13.1730039829537; Sun, 27 Oct 2024 07:37:09 -0700 (PDT) Received: from 6c1d2e1f4cf4.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b331b0d44sm281127966b.187.2024.10.27.07.37.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:37:09 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv3 10/22] ARM: dts: socfpga: remove arria10 reset-names Date: Sun, 27 Oct 2024 14:36:42 +0000 Message-Id: <20241027143654.28474-11-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241027143654.28474-1-l.rubusch@gmail.com> References: <20241027143654.28474-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove the reset-names since the binding does not mention them, and they seem not to be used in arria10 (similarily to agilex). Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/ar= m/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 6a2ecc7ed..005c57843 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -818,7 +818,6 @@ timer0: timer0@ffc02700 { clocks =3D <&l4_sp_clk>; clock-names =3D "timer"; resets =3D <&rst SPTIMER0_RESET>; - reset-names =3D "timer"; }; =20 timer1: timer1@ffc02800 { @@ -828,7 +827,6 @@ timer1: timer1@ffc02800 { clocks =3D <&l4_sp_clk>; clock-names =3D "timer"; resets =3D <&rst SPTIMER1_RESET>; - reset-names =3D "timer"; }; =20 timer2: timer2@ffd00000 { @@ -838,7 +836,6 @@ timer2: timer2@ffd00000 { clocks =3D <&l4_sys_free_clk>; clock-names =3D "timer"; resets =3D <&rst L4SYSTIMER0_RESET>; - reset-names =3D "timer"; }; =20 timer3: timer3@ffd00100 { @@ -848,7 +845,6 @@ timer3: timer3@ffd00100 { clocks =3D <&l4_sys_free_clk>; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b331b0d44sm281127966b.187.2024.10.27.07.37.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:37:11 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv3 11/22] dt-bindings: net: snps,dwmac: add support for Arria10 Date: Sun, 27 Oct 2024 14:36:43 +0000 Message-Id: <20241027143654.28474-12-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241027143654.28474-1-l.rubusch@gmail.com> References: <20241027143654.28474-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The hard processor system (HPS) on the Inte/Altera Arria10 provides three Ethernet Media Access Controller (EMAC) peripherals. Each EMAC can be used to transmit and receive data at 10/100/1000 Mbps over ethernet connections in compliance with the IEEE 802.3 specification. The EMACs on the Arria10 are instances of the Synopsis DesignWare Universal 10/100/1000 Ethernet MAC, version 3.72a. Support the Synopsis DesignWare version 3.72a, which is used in Intel's Arria10 SoC, since it was missing. Signed-off-by: Lothar Rubusch --- Documentation/devicetree/bindings/net/snps,dwmac.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Docume= ntation/devicetree/bindings/net/snps,dwmac.yaml index 15073627c..d26bb77eb 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -26,6 +26,7 @@ select: - snps,dwmac-3.610 - snps,dwmac-3.70a - snps,dwmac-3.710 + - snps,dwmac-3.72a - snps,dwmac-4.00 - snps,dwmac-4.10a - snps,dwmac-4.20a @@ -88,6 +89,7 @@ properties: - snps,dwmac-3.610 - snps,dwmac-3.70a - snps,dwmac-3.710 + - snps,dwmac-3.72a - snps,dwmac-4.00 - snps,dwmac-4.10a - snps,dwmac-4.20a --=20 2.25.1 From nobody Mon Nov 25 12:17:15 2024 Received: from mail-ed1-f45.google.com (mail-ed1-f45.google.com [209.85.208.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0AFB1885A5; Sun, 27 Oct 2024 14:37:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039837; cv=none; b=rE+XlMSfd7g1XZfEeVHAhzRu0kfVSK+PFAAvh5bMnZnKnXxGYdiKjpRXXU8ucgtC7R658lQz0wcdDxUkGDIzHlFUrykVOYQJNbm2wxaKrx+ByWM3uy4rMSto0b0UuBmB8w1gP49f2Xk5GXf6fx6UWGp9mcnXDWKUtSEiYUg1Iwo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039837; c=relaxed/simple; bh=uNUTiA0HvI5A7c5xE1I8y5ErznWdRKyRHGjQDeKPcAA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HKll/22ZfAWbutZ3jYLUlZWuKLbfhJLnU/JuK9ki84wY6tgXm9SArefPfTWwC555T1JruGlbixGD7IFzndQ3pL1mWavv9PmCzcDri2eW1r0ivbuVKErVM6BBFsoSAGYFAAvCDehiMPSLMV/EvnWRbGHd6s0WiHYHGYULshltbtk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=DqAKEKZE; arc=none smtp.client-ip=209.85.208.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="DqAKEKZE" Received: by mail-ed1-f45.google.com with SMTP id 4fb4d7f45d1cf-5c933d5bdf1so595522a12.0; Sun, 27 Oct 2024 07:37:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730039833; x=1730644633; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rx0eMLUEzhYETTDB2Dx4nHIilzNRVf/VQgEFIdoul78=; b=DqAKEKZEDwFRD0mfbK1d6w3t9Kpob5yDy96mvjeN3dTc3/b7pGYY7kPIS8HW6zETRe KkrZESzkxCNFzY6VfHQiEkk6iDN9zodj5xxDeK1WajdbcLGxlNf2OS2L8brXD8gGsMIu u9RKJMuE4RrS74+tffXNJQHu5fNiiWEV1s6nRffMffEIoTiBeN9Zv2UaqX3OYwvjqoyF k/R2jnRya3Teo+d6435VLMOKS70hFlQnF0AFQEvNNJWAV50fGJlacMyLth3pctPqPcvR Ms60gvngeRmD3ZKZKkUiKplC/JaUwx947WGS1XRU7DwhOPXJWjWyr0yitLhwR5cpgZDv 2xkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730039833; x=1730644633; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rx0eMLUEzhYETTDB2Dx4nHIilzNRVf/VQgEFIdoul78=; b=mXMPOAFN7OGCy0QamkNuB7I2ovavLfhh9iWVd3rmc/Gtp7ZobG8gT84KOu8bxYPo18 2nxHbfEKWSgH/h5nN4HJdaiZPVk0TlcEEg7MXdysHO9zIKMSEYZ4d+U0us/VfYK2O20V lX6OnPYMCQIF8phmOdlWiDHsOCDuyoEwGpSvQPDUYrhZifWDQx2pEF9F50tCrGp5wobR tF9G4Or+GYyqtjIgOAtIIth/yqNE6yDZRsOQBcnsmuDW2kkAFyIPMxjvDkCE+cFW0Dk8 Yv5S7HFMnkvNUu7ZvDYJ/uF4eHYbFeglMmdl8BT86PozuOfG3gCo6VbDo7t7S7qk4pKT DKrQ== X-Forwarded-Encrypted: i=1; AJvYcCV5PZCODEMZyyeM8WQhKbdcDeifQjj0GzpfaCsorfiR1K8HqDeXUze29Ewwan3l5VJ3ZAzNdUEATVhMMMk5@vger.kernel.org, AJvYcCVxJxtmhplyljrQNfPXONir4tHsPcbCTi0FW/w9wdcZYBpTGkIJw/9TDSDmxBCMfgAMTGzC9rmrq9ZF@vger.kernel.org X-Gm-Message-State: AOJu0YxlJCMOHZ9T8TIJdmqQ3kzzoX5m+3odVc+GRppXzlK4b79MLK41 bPpF53S/uinU3x6cAOHRVCpwqzvdeXbgo2my0dmi7XTLCdndD/XJ X-Google-Smtp-Source: AGHT+IEkxF5cW4beSYYEtxHyjAeTnq8ebNdUGgPAh31LieegcmV6+T0Nnx4rqWTO1nnGW7STvmCkOg== X-Received: by 2002:a17:906:d554:b0:a9a:130e:120c with SMTP id a640c23a62f3a-a9de631e898mr229504666b.12.1730039833183; Sun, 27 Oct 2024 07:37:13 -0700 (PDT) Received: from 6c1d2e1f4cf4.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b331b0d44sm281127966b.187.2024.10.27.07.37.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:37:12 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv3 12/22] ARM: dts: socfpga: add Enclustra boot-mode dtsi Date: Sun, 27 Oct 2024 14:36:44 +0000 Message-Id: <20241027143654.28474-13-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241027143654.28474-1-l.rubusch@gmail.com> References: <20241027143654.28474-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add generic boot-mode support to Enclustra Arria10 and Cyclone5 boards. Some Enclustra carrier boards need hardware adjustments specific to the selected boot-mode. Enclustra's Arria10 SoMs allow for booting from different media. By muxing certain IO pins, the media can be selected. This muxing can be done by gpios at runtime e.g. when flashing QSPI from off the bootloader. But also to have statically certain boot media available, certain adjustments to the DT are needed: - SD: QSPI must be disabled - eMMC: QSPI must be disabled, bus width can be doubled to 8 byte - QSPI: any mmc is disabled, QSPI then defaults to be enabled The boot media must be accessible to the bootloader, e.g. to load a bitstream file, but also to the system to mount the rootfs and to use the specific performance. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga_enclustra_mercury_bootmode_emmc.dtsi | 12 ++++++++++++ .../socfpga_enclustra_mercury_bootmode_qspi.dtsi | 8 ++++++++ .../socfpga_enclustra_mercury_bootmode_sdmmc.dtsi | 8 ++++++++ 3 files changed, 28 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_bootmode_emmc.dtsi create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_bootmode_qspi.dtsi create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_bootmode_sdmmc.dtsi diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_boot= mode_emmc.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_= bootmode_emmc.dtsi new file mode 100644 index 000000000..d79cb64da --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_em= mc.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&qspi { + status =3D "disabled"; +}; + +&mmc { + bus-width =3D <8>; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_boot= mode_qspi.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_= bootmode_qspi.dtsi new file mode 100644 index 000000000..5ba21dd8f --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_qs= pi.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&mmc { + status =3D "disabled"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_boot= mode_sdmmc.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury= _bootmode_sdmmc.dtsi new file mode 100644 index 000000000..2b102e0b6 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_sd= mmc.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&qspi { + status =3D "disabled"; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b331b0d44sm281127966b.187.2024.10.27.07.37.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:37:13 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv3 13/22] ARM: dts: socfpga: add Enclustra base-board dtsi Date: Sun, 27 Oct 2024 14:36:45 +0000 Message-Id: <20241027143654.28474-14-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241027143654.28474-1-l.rubusch@gmail.com> References: <20241027143654.28474-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add generic Enclustra base-board support for the Mercury+ PE1, the Mercury+ PE3 and the Mercury+ ST1 board. The carrier boards can be freely combined with the SoMs Mercury+ AA1, Mercury SA1 and Mercury+ SA2. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga_enclustra_mercury_pe1.dtsi | 33 +++++++++++ .../socfpga_enclustra_mercury_pe3.dtsi | 55 +++++++++++++++++++ .../socfpga_enclustra_mercury_st1.dtsi | 15 +++++ 3 files changed, 103 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_pe1.dtsi create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_pe3.dtsi create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_st1.dtsi diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.= dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi new file mode 100644 index 000000000..11f418e88 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + status =3D "okay"; + + 24aa128@57 { + status =3D "okay"; + compatible =3D "microchip,24c128"; + reg =3D <0x57>; + pagesize =3D <64>; + label =3D "user eeprom"; + address-width =3D <16>; + }; + + lm96080@2f { + status =3D "okay"; + compatible =3D "national,lm80"; + reg =3D <0x2f>; + }; + + si5338@70 { + compatible =3D "silabs,si5338"; + reg =3D <0x70>; + }; + +}; + +&i2c_encl_fpga { + status =3D "okay"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.= dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi new file mode 100644 index 000000000..9fbde91ad --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + i2c-mux@74 { + status =3D "okay"; + compatible =3D "nxp,pca9547"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x74>; + + i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + + 24aa128@56 { + status =3D "okay"; + compatible =3D "microchip,24c128"; + reg =3D <0x56>; + pagesize =3D <64>; + label =3D "user eeprom"; + address-width =3D <16>; + }; + + lm96080@2f { + status =3D "okay"; + compatible =3D "national,lm80"; + reg =3D <0x2f>; + }; + + pcal6416@20 { + status =3D "okay"; + compatible =3D "nxp,pcal6416"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + }; + }; + }; +}; + +&i2c_encl_fpga { + status =3D "okay"; + + i2c-mux@75 { + status =3D "okay"; + compatible =3D "nxp,pca9547"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x75>; + }; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.= dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi new file mode 100644 index 000000000..ffcef353e --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + si5338@70 { + compatible =3D "silabs,si5338"; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b331b0d44sm281127966b.187.2024.10.27.07.37.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:37:15 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv3 14/22] ARM: dts: socfpga: add Enclustra Mercury SA1 Date: Sun, 27 Oct 2024 14:36:46 +0000 Message-Id: <20241027143654.28474-15-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241027143654.28474-1-l.rubusch@gmail.com> References: <20241027143654.28474-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce support for Enclustra's Mercury SA1 SoM based on Intel Cyclone5 technology as a .dtsi file. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga/socfpga_cyclone5_mercury_sa1.dtsi | 143 ++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1.dtsi diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1.d= tsi b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1.dtsi new file mode 100644 index 000000000..3eb2c559f --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model =3D "Enclustra Mercury SA1"; + compatible =3D "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + aliases { + ethernet0 =3D &gmac1; + }; + + /* Adjusted the i2c labels to use generic base-board dtsi files for + * Enclustra Arria10 and Cyclone5 SoMs. + * + * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in + * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi + * fragments. Thus define generic labels here to match the correct i2c + * bus in a generic base-board .dtsi file. + */ + soc { + i2c_encl: i2c@ffc04000 { + }; + i2c_encl_fpga: i2c@ffc05000 { + }; + }; + + memory { + name =3D "memory"; + device_type =3D "memory"; + reg =3D <0x0 0x40000000>; /* 1GB */ + }; +}; + +&osc1 { + clock-frequency =3D <50000000>; +}; + +&i2c_encl { + i2c-sda-hold-time-ns =3D <300>; + clock-frequency =3D <100000>; + status =3D "okay"; + + isl12020: isl12020@6f { + compatible =3D "isil,isl12022"; + reg =3D <0x6f>; + }; +}; + +&i2c_encl_fpga { + i2c-sda-hold-time-ns =3D <300>; + status =3D "disabled"; +}; + +&uart0 { + clock-frequency =3D <100000000>; +}; + +&mmc0 { + status =3D "okay"; + /delete-property/ cap-mmc-highspeed; + /delete-property/ cap-sd-highspeed; +}; + +&qspi { + status =3D "okay"; + + flash0: s25fl512s@0 { + u-boot,dm-pre-reloc; + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "spansion,s25fl512s", "jedec,spi-nor"; + reg =3D <0>; + + spi-rx-bus-width =3D <4>; + spi-tx-bus-width =3D <4>; + spi-max-frequency =3D <10000000>; + + cdns,read-delay =3D <4>; + cdns,tshsl-ns =3D <50>; + cdns,tsd2d-ns =3D <50>; + cdns,tchsh-ns =3D <4>; + cdns,tslch-ns =3D <4>; + + partition@raw { + label =3D "Flash Raw"; + reg =3D <0x0 0x4000000>; + }; + }; +}; + +&gpio0 { + status =3D "okay"; +}; + +&gpio1 { + status =3D "okay"; +}; + +&gmac1 { + status =3D "okay"; + /delete-property/ mac-address; + phy-mode =3D "rgmii"; + phy-handle =3D <&phy3>; + + mdio0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + + phy3: ethernet-phy@3 { + reg =3D <3>; + + /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/ + rxc-skew-ps =3D <1680>; + rxd0-skew-ps =3D <420>; + rxd1-skew-ps =3D <420>; + rxd2-skew-ps =3D <420>; + rxd3-skew-ps =3D <420>; + rxdv-skew-ps =3D <420>; + + /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/ + txc-skew-ps =3D <1860>; + txd0-skew-ps =3D <0>; + txd1-skew-ps =3D <0>; + txd2-skew-ps =3D <0>; + txd3-skew-ps =3D <0>; + txen-skew-ps =3D <0>; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b331b0d44sm281127966b.187.2024.10.27.07.37.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:37:16 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCHv3 15/22] dt-bindings: altera: add Enclustra Mercury SA1 Date: Sun, 27 Oct 2024 14:36:47 +0000 Message-Id: <20241027143654.28474-16-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241027143654.28474-1-l.rubusch@gmail.com> References: <20241027143654.28474-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update the DT binding for the Enclustra Mercury+ SA1 SoM Signed-off-by: Lothar Rubusch Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/altera.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentat= ion/devicetree/bindings/arm/altera.yaml index 8c7575455..87a22d2a4 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -51,6 +51,16 @@ properties: - const: altr,socfpga-cyclone5 - const: altr,socfpga =20 + - description: Mercury SA1 boards + items: + - enum: + - enclustra,mercury-sa1-pe1 + - enclustra,mercury-sa1-pe3 + - enclustra,mercury-sa1-st1 + - const: enclustra,mercury-sa1 + - const: altr,socfpga-cyclone5 + - const: altr,socfpga + - description: Stratix 10 boards items: - enum: --=20 2.25.1 From nobody Mon Nov 25 12:17:15 2024 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2282C18A93A; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b331b0d44sm281127966b.187.2024.10.27.07.37.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:37:17 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv3 16/22] ARM: dts: socfpga: add Enclustra Mercury+ SA2 Date: Sun, 27 Oct 2024 14:36:48 +0000 Message-Id: <20241027143654.28474-17-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241027143654.28474-1-l.rubusch@gmail.com> References: <20241027143654.28474-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce Enclustra's Mercury+ SA2 SoM based on Intel Cyclone5 technology as a .dtsi file. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga/socfpga_cyclone5_mercury_sa2.dtsi | 146 ++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2.dtsi diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.d= tsi b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi new file mode 100644 index 000000000..0425520e9 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2"; + compatible =3D "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + aliases { + ethernet0 =3D &gmac1; + }; + + /* Adjusted the i2c labels to use generic base-board dtsi files for + * Enclustra Arria10 and Cyclone5 SoMs. + * + * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in + * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi + * fragments. Thus define generic labels here to match the correct i2c + * bus in a generic base-board .dtsi file. + */ + soc { + i2c_encl: i2c@ffc04000 { + }; + i2c_encl_fpga: i2c@ffc05000 { + }; + }; + + memory { + name =3D "memory"; + device_type =3D "memory"; + reg =3D <0x0 0x80000000>; /* 2GB */ + }; +}; + +&osc1 { + clock-frequency =3D <50000000>; +}; + +&i2c_encl { + i2c-sda-hold-time-ns =3D <300>; + clock-frequency =3D <100000>; + status =3D "okay"; + + isl12020: isl12020@6f { + compatible =3D "isil,isl12022"; + reg =3D <0x6f>; + }; + + atsha204a: atsha204a@64 { + compatible =3D "atmel,atsha204a"; + reg =3D <0x64>; + }; +}; + +&i2c_encl_fpga { + i2c-sda-hold-time-ns =3D <300>; + status =3D "disabled"; +}; + +&uart0 { + clock-frequency =3D <100000000>; +}; + +&mmc0 { + status =3D "okay"; +}; + +&qspi { + status =3D "okay"; + + flash0: s25fl512s@0 { + u-boot,dm-pre-reloc; + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "spansion,s25fl512s", "jedec,spi-nor"; + reg =3D <0>; + + spi-rx-bus-width =3D <4>; + spi-tx-bus-width =3D <4>; + spi-max-frequency =3D <10000000>; + + cdns,read-delay =3D <4>; + cdns,tshsl-ns =3D <50>; + cdns,tsd2d-ns =3D <50>; + cdns,tchsh-ns =3D <4>; + cdns,tslch-ns =3D <4>; + + partition@raw { + label =3D "Flash Raw"; + reg =3D <0x0 0x4000000>; + }; + }; +}; + +&gpio0 { + status =3D "okay"; +}; + +&gpio1 { + status =3D "okay"; +}; + +&gmac1 { + status =3D "okay"; + /delete-property/ mac-address; + phy-mode =3D "rgmii"; + phy-handle =3D <&phy3>; + + mdio0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + + phy3: ethernet-phy@3 { + reg =3D <3>; + + /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/ + rxc-skew-ps =3D <1680>; + rxd0-skew-ps =3D <420>; + rxd1-skew-ps =3D <420>; + rxd2-skew-ps =3D <420>; + rxd3-skew-ps =3D <420>; + rxdv-skew-ps =3D <420>; + + /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/ + txc-skew-ps =3D <1860>; + txd0-skew-ps =3D <0>; + txd1-skew-ps =3D <0>; + txd2-skew-ps =3D <0>; + txd3-skew-ps =3D <0>; + txen-skew-ps =3D <0>; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b331b0d44sm281127966b.187.2024.10.27.07.37.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:37:19 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCHv3 17/22] dt-bindings: altera: add binding for Mercury+ SA2 Date: Sun, 27 Oct 2024 14:36:49 +0000 Message-Id: <20241027143654.28474-18-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241027143654.28474-1-l.rubusch@gmail.com> References: <20241027143654.28474-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update the device-tree binding for the Enclustra Mercury+ SA2 SoM. Signed-off-by: Lothar Rubusch Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/altera.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentat= ion/devicetree/bindings/arm/altera.yaml index 87a22d2a4..31af6859d 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -61,6 +61,16 @@ properties: - const: altr,socfpga-cyclone5 - const: altr,socfpga =20 + - description: Mercury+ SA2 boards + items: + - enum: + - enclustra,mercury-sa2-pe1 + - enclustra,mercury-sa2-pe3 + - enclustra,mercury-sa2-st1 + - const: enclustra,mercury-sa2 + - const: altr,socfpga-cyclone5 + - const: altr,socfpga + - description: Stratix 10 boards items: - enum: --=20 2.25.1 From nobody Mon Nov 25 12:17:15 2024 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BFA218C34C; Sun, 27 Oct 2024 14:37:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039844; cv=none; b=IxFkmsHrILl18uri/FPRasLtAZARiygn3yIKyrVZv+9Kce6re+sl+SAUITHvaYeYUH8bqKTaSLHrB/wQevaTkezzh8XvnOrMSwYHOV7MOJio8ILk6apj4M7T8zZTqkvoyw2U+o7Jqpa3nhdBp1sEIPr1jhJA2SpB0m5bsdFBH/g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039844; c=relaxed/simple; bh=4T4tsGiTu+7Yp74UkjgnnEqk77vW7pHzaOm0tx4xbNo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=AhoRQQt3XJB3KwOlCz8VmRXV6JN0BoTWSDbsKymhQTVbJI3UpIsWb1VYm1IUMAo/0vsK/Q2rh9Rkq/aSBKSyCCuM4eoZ4vXKFFPhzfGYVjev1XY7K1m2sC3jTYMyBB4L6fWvBFmkh7UOEzgSAiF8TMkYg0F+E7dnukumiwGbjZg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=QYj0gGIt; arc=none smtp.client-ip=209.85.218.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="QYj0gGIt" Received: by mail-ej1-f46.google.com with SMTP id a640c23a62f3a-a9a017a382bso55227266b.3; Sun, 27 Oct 2024 07:37:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730039841; x=1730644641; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PoMQoTVDf0EJ7kPt2JC+Fe2z9tRYP9H50/zuHO5yLsU=; b=QYj0gGItALyHAOQ0gKv7Cn5kNsY4QuSJj6Q/ALGRMFpSCZ+r8Y+9HKEcSbyDE5PxLo nxUdq2OMwjkHWCSOIvdTL3gY4VL8uFeJaOTT8t0H67qlKVp0COPDtCTUtiKg5tzYWFqK 0z7GWxVu/UODse3kLFZ7DIz2KilFIY4LWJac8IB25ywniQgoww81CZ/Wb/eC7rarGd9V y6Et8yA8PAZ4ocWKHGuWXA+PNBJ/JAS3pOpAwW2Ni1jTEa84Z53s0M3RoTz2dieTxVDH o1n4Swk8HGg2GZnb21+qqHTg5rTvNApCBEak3JRTNUORqDsLWAUBny8v/5mRj7GYHjRk jXdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730039841; x=1730644641; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PoMQoTVDf0EJ7kPt2JC+Fe2z9tRYP9H50/zuHO5yLsU=; b=Hsr5phwA6H37fNT6uSh/6RI+KNqf6wcKQLZFYQKGr+guHrtdcll7JkYNM/zrx21a+3 MTSTJ4QfyQqRc9/fBOb8HidgDaRZeugQM6klBHobAgfen0DPKrj5RuN6Nwl3l9eXYAUJ Zojq0D3/v0B1J1T9N5f776JhRhB1xrud434Q4/ilPx3wECJ/EgRKb6jXTvPob6tlYY71 btLtj9vDkMcZt3GoCD+BAJI8H80mqtOl8SQnLe8n/klZmOGTki/0q0U1SYFn4/Ne9AIf 4uYHuA1HdiT8zOrCgUlQoA+vaHO1NBP/Nz7QUQ2odJsC27A4wreyET/ZowDP2qFrXXu4 u4kQ== X-Forwarded-Encrypted: i=1; AJvYcCUORuiUk7q3J7AJcI8C6TQRKV7cU8gwUEdPophEpcYsIurCthxcHN/s67Wvy6CQZ9H2BTqk83RqIDEL@vger.kernel.org, AJvYcCVDRf9rLX6Weiww/mwF+ApGZsW3nkr3h11KU00E02St5YPl8zy9ltUu9ZfHqhzIOLaP/SPm9lzD/Z9dsByV@vger.kernel.org X-Gm-Message-State: AOJu0YxkIoNzGg2DpjZl2QnlawPDKa6hATDjFiSwc5rGC4jdxrWK5Ob8 w6ZwB5u4NiN5AQ9kwnaHp2pvzBHx5GDA+BfHJaCpP58FVrf2Uxwx X-Google-Smtp-Source: AGHT+IFQb9UQBKk924s83vklBK5+wQH/yK2bRrf9dj/vuuaSnbzyL2zeJ/f0D2iQ15e7PiGFOXqrxA== X-Received: by 2002:a17:907:7f0e:b0:a9a:147d:fec2 with SMTP id a640c23a62f3a-a9de5f04397mr170842266b.6.1730039840441; Sun, 27 Oct 2024 07:37:20 -0700 (PDT) Received: from 6c1d2e1f4cf4.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b331b0d44sm281127966b.187.2024.10.27.07.37.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:37:20 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv3 18/22] ARM: dts: socfpga: add Mercury AA1 combinations Date: Sun, 27 Oct 2024 14:36:50 +0000 Message-Id: <20241027143654.28474-19-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241027143654.28474-1-l.rubusch@gmail.com> References: <20241027143654.28474-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce support for Enclustra's Mercury+ AA1 SoM, based on Intel Arria10. This is a flexible approach to allow for combining SoM with carrier board .dtsi and boot-mode .dtsi in a device-tree file. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga/socfpga_arria10_mercury_aa1.dtsi | 141 +++++++++++++++--- 1 file changed, 120 insertions(+), 21 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dt= si b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi index 41f865c8c..cdd693cf9 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi @@ -7,12 +7,14 @@ =20 / { =20 - model =3D "Enclustra Mercury AA1"; - compatible =3D "enclustra,mercury-aa1", "altr,socfpga-arria10", "altr,soc= fpga"; + model =3D "Enclustra Mercury+ AA1"; + compatible =3D "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; =20 aliases { ethernet0 =3D &gmac0; serial1 =3D &uart1; + spi0 =3D &qspi; }; =20 memory@0 { @@ -24,52 +26,102 @@ memory@0 { chosen { stdout-path =3D "serial1:115200n8"; }; + + /* Adjusted the i2c labels to use generic base-board dtsi files for + * Enclustra Arria10 and Cyclone5 SoMs. + * + * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in + * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi + * fragments. Thus define generic labels here to match the correct i2c + * bus in a generic base-board .dtsi file. + */ + soc { + i2c_encl: i2c@ffc02300 { + }; + i2c_encl_fpga: i2c@ffc02200 { + }; + }; +}; + +&i2c_encl { + status =3D "okay"; + i2c-sda-hold-time-ns =3D <300>; + clock-frequency =3D <100000>; + + atsha204a: atsha204a@64 { + compatible =3D "atmel,atsha204a"; + reg =3D <0x64>; + }; + + isl12022: isl12022@6f { + compatible =3D "isil,isl12022"; + reg =3D <0x6f>; + }; +}; + +&i2c_encl_fpga { + i2c-sda-hold-time-ns =3D <300>; + status =3D "disabled"; }; =20 &gmac0 { + status =3D "okay"; phy-mode =3D "rgmii"; phy-addr =3D <0xffffffff>; /* probe for phy addr */ - max-frame-size =3D <3800>; - phy-handle =3D <&phy3>; =20 + /delete-property/ mac-address; + mdio { #address-cells =3D <1>; #size-cells =3D <0>; compatible =3D "snps,dwmac-mdio"; phy3: ethernet-phy@3 { - txd0-skew-ps =3D <0>; /* -420ps */ - txd1-skew-ps =3D <0>; /* -420ps */ - txd2-skew-ps =3D <0>; /* -420ps */ - txd3-skew-ps =3D <0>; /* -420ps */ + reg =3D <3>; + + /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/ + rxc-skew-ps =3D <1680>; /* 780ps */ rxd0-skew-ps =3D <420>; /* 0ps */ rxd1-skew-ps =3D <420>; /* 0ps */ rxd2-skew-ps =3D <420>; /* 0ps */ rxd3-skew-ps =3D <420>; /* 0ps */ - txen-skew-ps =3D <0>; /* -420ps */ - txc-skew-ps =3D <1860>; /* 960ps */ rxdv-skew-ps =3D <420>; /* 0ps */ - rxc-skew-ps =3D <1680>; /* 780ps */ - reg =3D <3>; + + /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/ + txc-skew-ps =3D <1860>; /* 960ps */ + txd0-skew-ps =3D <0>; /* -420ps */ + txd1-skew-ps =3D <0>; /* -420ps */ + txd2-skew-ps =3D <0>; /* -420ps */ + txd3-skew-ps =3D <0>; /* -420ps */ + txen-skew-ps =3D <0>; /* -420ps */ }; }; }; =20 -&i2c1 { - atsha204a: crypto@64 { - compatible =3D "atmel,atsha204a"; - reg =3D <0x64>; - }; +&gpio0 { + status =3D "okay"; +}; =20 - isl12022: isl12022@6f { - compatible =3D "isil,isl12022"; - reg =3D <0x6f>; - }; +&gpio1 { + status =3D "okay"; +}; + +&gpio2 { + status =3D "okay"; +}; + +&uart0 { + status =3D "disabled"; +}; + +&uart1 { + status =3D "okay"; }; =20 /* Following mappings are taken from arria10 socdk dts */ &mmc { + status =3D "okay"; cap-sd-highspeed; broken-cd; bus-width =3D <4>; @@ -79,3 +131,50 @@ &mmc { &osc1 { clock-frequency =3D <33330000>; }; + +&eccmgr { + sdmmca-ecc@ff8c2c00 { + compatible =3D "altr,socfpga-sdmmc-ecc"; + reg =3D <0xff8c2c00 0x400>; + altr,ecc-parent =3D <&mmc>; + interrupts =3D <15 IRQ_TYPE_LEVEL_HIGH>, + <47 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>, + <48 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&qspi { + status =3D "okay"; + flash0: s25fl512s@0 { + u-boot,dm-pre-reloc; + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "spansion,s25fl512s", "jedec,spi-nor"; + reg =3D <0>; + + spi-rx-bus-width =3D <4>; + spi-tx-bus-width =3D <4>; + spi-max-frequency =3D <10000000>; + + cdns,read-delay =3D <4>; + cdns,tshsl-ns =3D <50>; + cdns,tsd2d-ns =3D <50>; + cdns,tchsh-ns =3D <4>; + cdns,tslch-ns =3D <4>; + + partition@raw { + label =3D "Flash Raw"; + reg =3D <0x0 0x4000000>; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b331b0d44sm281127966b.187.2024.10.27.07.37.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:37:21 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCHv3 19/22] dt-bindings: altera: add Mercury AA1 combinations Date: Sun, 27 Oct 2024 14:36:51 +0000 Message-Id: <20241027143654.28474-20-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241027143654.28474-1-l.rubusch@gmail.com> References: <20241027143654.28474-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update binding with combined .dts for the Mercury+ PE1, PE3 and ST1 carrier boards with the Mercury+ AA1 SoM. Signed-off-by: Lothar Rubusch Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/altera.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentat= ion/devicetree/bindings/arm/altera.yaml index 31af6859d..51f10ff8e 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -32,6 +32,9 @@ properties: items: - enum: - enclustra,mercury-pe1 + - enclustra,mercury-aa1-pe1 + - enclustra,mercury-aa1-pe3 + - enclustra,mercury-aa1-st1 - google,chameleon-v3 - const: enclustra,mercury-aa1 - const: altr,socfpga-arria10 --=20 2.25.1 From nobody Mon Nov 25 12:17:15 2024 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B842218D658; Sun, 27 Oct 2024 14:37:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039847; cv=none; b=SyTCIcLX4SKFE+HACg7n4Y4XO+kmVlu6H4d+z1OYwMcP538UiPeHrb8WZqnlrptHCiIuk6GqqJj6A8u4ksr++WtG6EL7Wki0v3bfAu1t/3UFUdCYMLFXs8oA+Nd3B+Edj4iOik8A6FQXSU95ElAdO7WUxH5MytvnOCNe8r2ZFBQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039847; c=relaxed/simple; bh=S9k+VQ0WleJZ5GpcYDB2e3SzoRT8QVHAAnec/ufVy8M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=e7Em9S+/qtGdx987HuPWjAS8CSqbrudyO9mSctamLslHnkbrBUiulBCqvEnwi+BVmgk18OO/4axy3zA1SDfVfMTordeOSdT5CvnDDFGW1XuRfsRFcPFOt0MWnQ0VmsPOiKcc1+0XWhiKSWWmssiv8aY9NkEV1zbR7i0WE4zkJO4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=VqqXR/vE; arc=none smtp.client-ip=209.85.218.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="VqqXR/vE" Received: by mail-ej1-f51.google.com with SMTP id a640c23a62f3a-a9a017a382bso55228066b.3; Sun, 27 Oct 2024 07:37:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730039843; x=1730644643; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=p5pESrG6jMEz3xnbtE1/gQgYKtauCE3QcRjN239YnKs=; b=VqqXR/vE4kZrhy5HWNcvwZf9MTYkKJLba3gssFq+lsiuJ+jt5Vkr+lvL6jej2ozkVi XmpUVndN71vJd6LRtV5YZQRtCHJKQ4eu1LbhIhfKrevZU+W55VYPjejpvsfxEKhD7B/l xiEEt20LraY/rKTaPdO3KKvrO8xkR4iMuYoulDHzUhq2r/ilgUSWB1hmgwoK20HUN94E iweLsSXewPFzzuf5AcYtPWvjH8VyERSBKsBsH77Wvaf0rvSJnIECdTBFZ780b5z5bz9L ZYqpRCCLBaq981SzOF/WP5CPVb8KwcDneR9dfxFiICHW5Y1fauwWFGkb1t3TMDhCb0Eu bFnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730039843; x=1730644643; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p5pESrG6jMEz3xnbtE1/gQgYKtauCE3QcRjN239YnKs=; b=ovZMXROilPcXxn8cMUyHX29shH3xCaBSB66lA7qw60bVAGBnfMQPcUFGt6ygHXgHn6 RdrWCoeqeZICODMiAIXKXd6h8OqEWbyMIwqwaWEE+nR6lDeLHSrvr7RX3zVRIRga9nHt YiXw7htYpVuqPKI9WGsuCyt9zo0jJhp/Y/4y7yAfzo2U/mg5LSwB5NdzP5ir9PAAcSXd f+COfHqrqGdkKC+QIJfK+KWJmfygCBTHF12Z+O2d39bMpT8K+xy+IvJnVhllyzVaKM62 7C2jVSVvpxfAtUS7gyU6MX6Rb6RXRQNJWDDnhjU4eLNf13DgLp2uX7AtPe6flPzEQit/ Ej4w== X-Forwarded-Encrypted: i=1; AJvYcCUFC5dV/MlDzUdQAW1qekwylOhBs6FGVdlJ2eXG36a1xx3V5qNzwaqo62lbsbjf9h1Jxd23BUMfDjdB5N8I@vger.kernel.org, AJvYcCULL2FdjfxpRXvq9LE71DRwCSf+RTIX7swPESRKHaiur7s3A8tnrkzvxlKlajE4UyW0r5WoQTLkjIS/@vger.kernel.org X-Gm-Message-State: AOJu0YzwsehWW1OTptYkHz664UWOdWVftPpjgYeWu0773xnFHKauABpn FL09NVrXRD/WTujNPbaquto5+6ix/5cEoITdfMQ9Wm53o7EawyxLgOutFQ== X-Google-Smtp-Source: AGHT+IEM+SKjv0KHRJwA1rCsj1ubf+u3gxyqn9fU+uRHd/8tGzpMooP+afK4cUesdFqimD5jbD7eBw== X-Received: by 2002:a17:907:e8b:b0:a99:d6e1:6056 with SMTP id a640c23a62f3a-a9de61a3ad5mr224242266b.10.1730039842754; Sun, 27 Oct 2024 07:37:22 -0700 (PDT) Received: from 6c1d2e1f4cf4.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b331b0d44sm281127966b.187.2024.10.27.07.37.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:37:22 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv3 20/22] ARM: dts: socfpga: removal of generic PE1 dts Date: Sun, 27 Oct 2024 14:36:52 +0000 Message-Id: <20241027143654.28474-21-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241027143654.28474-1-l.rubusch@gmail.com> References: <20241027143654.28474-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove the older socfpga_arria10_mercury_pe1.dts, since it is duplicate, the hardware is covered by the combination of Enclustra's .dtsi files. The older .dts was limited to only the case of having an Enclustra Mercury+ AA1 on a Mercury+ PE1 base board, booting from sdmmc. This functionality is provided also by the generic Enclustra dtsi and dts files, in particular socfpga_arria10_mercury_aa1_pe1_sdmmc.dts. Since both .dts files cover the same, the older one is to e replaced in favor of the more modularized approach. Signed-off-by: Lothar Rubusch Acked-by: Steffen Trumtrar --- arch/arm/boot/dts/intel/socfpga/Makefile | 1 - .../socfpga/socfpga_arria10_mercury_pe1.dts | 55 ------------------- 2 files changed, 56 deletions(-) delete mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _pe1.dts diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/i= ntel/socfpga/Makefile index c467828ae..d95862e34 100644 --- a/arch/arm/boot/dts/intel/socfpga/Makefile +++ b/arch/arm/boot/dts/intel/socfpga/Makefile @@ -2,7 +2,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) +=3D \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3.dtb \ - socfpga_arria10_mercury_pe1.dtb \ socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dt= s b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts deleted file mode 100644 index cf533f76a..000000000 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2023 Steffen Trumtrar - */ -/dts-v1/; -#include "socfpga_arria10_mercury_aa1.dtsi" - -/ { - model =3D "Enclustra Mercury+ PE1"; - compatible =3D "enclustra,mercury-pe1", "enclustra,mercury-aa1", - "altr,socfpga-arria10", "altr,socfpga"; - - aliases { - ethernet0 =3D &gmac0; - serial0 =3D &uart0; - serial1 =3D &uart1; - }; -}; - -&gmac0 { - status =3D "okay"; -}; - -&gpio0 { - status =3D "okay"; -}; - -&gpio1 { - status =3D "okay"; -}; - -&gpio2 { - status =3D "okay"; -}; - -&i2c1 { - status =3D "okay"; -}; - -&mmc { - status =3D "okay"; -}; - -&uart0 { - status =3D "okay"; -}; - -&uart1 { - status =3D "okay"; -}; - -&usb0 { - status =3D "okay"; - dr_mode =3D "host"; -}; --=20 2.25.1 From nobody Mon Nov 25 12:17:15 2024 Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97AB918DF99; Sun, 27 Oct 2024 14:37:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b331b0d44sm281127966b.187.2024.10.27.07.37.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:37:23 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv3 21/22] dt-bindings: altera: removal of generic PE1 dts Date: Sun, 27 Oct 2024 14:36:53 +0000 Message-Id: <20241027143654.28474-22-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241027143654.28474-1-l.rubusch@gmail.com> References: <20241027143654.28474-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove the binding for the generic Mercury+ AA1 on PE1 carrier board. The removed Mercury+ AA1 on PE1 carrier board is just a particular setup case, which is actually replaced by the set of generic Mercury+ AA1 combinations patch. In other words a combination of a Mercury+ AA1 on a PE1 base board, with boot mode SD card is already covered by the generic AA1 combinations. There is no further reason to keep this particular case now in a redundantly. Thus the redundant DT setup is removed. Signed-off-by: Lothar Rubusch Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/altera.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentat= ion/devicetree/bindings/arm/altera.yaml index 51f10ff8e..1561f0164 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -31,7 +31,6 @@ properties: - description: Mercury+ AA1 boards items: - enum: - - enclustra,mercury-pe1 - enclustra,mercury-aa1-pe1 - enclustra,mercury-aa1-pe3 - enclustra,mercury-aa1-st1 --=20 2.25.1 From nobody Mon Nov 25 12:17:15 2024 Received: from mail-ed1-f47.google.com (mail-ed1-f47.google.com [209.85.208.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45E8D18F2C3; Sun, 27 Oct 2024 14:37:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039852; cv=none; b=dd86212v0OlQ/3W6VKKnPNMRRBQDxwvXNBRxO7VxF6gev4NO4cqKrJ6L/sXLy9Llx2Od+gaGPfSAzaLzbQnP90LV4VJ16Y/XX+YdKefZ0pqdew8ySn8fL8mR0TbtdzDGx6JnKzK3Dty7p9MbDphB68SBZKehYV1jvtlPhGSR1uk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730039852; c=relaxed/simple; bh=BKcROuWUYTw9JhFiD7stJcvz4b+0cKybV+ykIP65zt4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=q+MRlo5+xf9LlXPZbPjF+YyaB1+BVKy5q2ORQFvwMyvjX0BVqL345E3MZXadrbyzappThTP/Aob/O7PvrLR9B54YSBbYJ+OnO0FPf4J0/EQS3n4cSvdXgy3C8fCaAtBi8xjisiM1doN4Fahx4AqHVHRW3BsN0U5/oX9Rdg25gNs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=gahMWV1E; arc=none smtp.client-ip=209.85.208.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gahMWV1E" Received: by mail-ed1-f47.google.com with SMTP id 4fb4d7f45d1cf-5c937982445so527064a12.2; Sun, 27 Oct 2024 07:37:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730039847; x=1730644647; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=58/Yp9z5BeuiNsOYUdEfHyKptWKflHI/Ww9dE/OYykM=; b=gahMWV1EFrctG11dfb+2/bndOWvukvyJJ6mqzLRTHofQsZljmOdjvDZqxWYPDx/vTz JIdh8fkCuglt3TRDBP9sjIWgAZvzeoEOBXdy+xsdVly4UGblVND3Tyv7LEeGAt70womX jJuxJRrGpGHT5dbnm96F4NDYFaAXplxOa0+4RRJQxEESxgL9adUiu4eHdz3MhbLT/4RH 6BbI211p63lYg2U9QXwk6sZPLxtqXzFMhfIQ82/rudMaw9DkIIBJ6GG+XnKefWG4f2dV QyNytpUTIRbBENdtFxdG/UQb5vOKCTuSfAZbYB3CSMJGOoaJ/NBgbPbTfFsz/cCpLPpW ckNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730039847; x=1730644647; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=58/Yp9z5BeuiNsOYUdEfHyKptWKflHI/Ww9dE/OYykM=; b=Um7DVHRv1wCRJvck90QXfsj0i8xoo6Yp50OOmurP1bp4yaVr5WXjiuDjXDCk95cBor tcUI2eWIbAEF+SF+yW6hY4iW+4KONachUbZYeEUdDf8i71LfukVJcbkepXpB/NL0YkYk DP6FuUdc7NGVkUwIXkagkUvi2PljQk8DtobusHmnqMdHvydgakExKcwll8TSw+9N7MIp lnAFIr5l6ejb67oFgL6DOKWe9zapcD0PgraFHaiMjUQ4rdweRq2SdzNS7kDEf5lx6m1a HVCA+5t7c5wFFQsDUXbqEKRH4wHpig/1U4L+qsUyKFhuSMtqBtlviSl1NHSc+ipdi5dc E92A== X-Forwarded-Encrypted: i=1; AJvYcCUv5oVOvKV6+fUsQ+HR6AuRZQ+/+QIBByZgPJV7Y96KGR6DGvnegnw5I0wIM/r6ClnnitfINijQOmH4@vger.kernel.org, AJvYcCWPkqbzcw7rmM75oFAvar3dWudWuiFgz9a32imYyAeWIcjzC2H8rTVASI44F9sk4OViOtu24i3OKQv5UtLF@vger.kernel.org X-Gm-Message-State: AOJu0YwzDNGlCACJOJw3++3mws3iW30WU3qwqWIeeD1eHTMoygJwF5r6 O7iDhPco0PB5Y+kjLEpm9UWMessSrnVRPDMSoCBqWO9a/BoXf3Nr X-Google-Smtp-Source: AGHT+IE+pjGwZzKFkmHylEKCUTmyYa+kJ9yEhD3yJWlDNWJeGM5ifCDRuBS/Pu+XIelNocd5xzrkpg== X-Received: by 2002:a17:906:794a:b0:a9a:2523:b4fa with SMTP id a640c23a62f3a-a9de5ceafaemr234347866b.4.1730039846425; Sun, 27 Oct 2024 07:37:26 -0700 (PDT) Received: from 6c1d2e1f4cf4.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b331b0d44sm281127966b.187.2024.10.27.07.37.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 07:37:25 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv3 22/22] ARM: dts: socfpga: add Enclustra SoM dts files Date: Sun, 27 Oct 2024 14:36:54 +0000 Message-Id: <20241027143654.28474-23-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241027143654.28474-1-l.rubusch@gmail.com> References: <20241027143654.28474-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the approach to set up a combination of Enclustra's SoM on a carrier board and corresponding boot-mode as single device-tree target. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/Makefile | 24 +++++++++++++++++++ .../socfpga_arria10_mercury_aa1_pe1_emmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe1_qspi.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe1_sdmmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe3_emmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe3_qspi.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe3_sdmmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_st1_emmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_st1_qspi.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_st1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe1_emmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe3_emmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe3_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_st1_emmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_st1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa2_pe1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa2_pe3_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa2_st1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts | 16 +++++++++++++ 25 files changed, 408 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe3_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe3_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe3_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_st1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_st1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_st1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe3_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe3_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe3_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_st1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_st1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_st1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_pe1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_pe1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_pe3_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_pe3_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_st1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_st1_sdmmc.dts diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/i= ntel/socfpga/Makefile index d95862e34..861880560 100644 --- a/arch/arm/boot/dts/intel/socfpga/Makefile +++ b/arch/arm/boot/dts/intel/socfpga/Makefile @@ -2,6 +2,30 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) +=3D \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3.dtb \ + socfpga_arria10_mercury_aa1_pe1_emmc.dtb \ + socfpga_arria10_mercury_aa1_pe1_qspi.dtb \ + socfpga_arria10_mercury_aa1_pe1_sdmmc.dtb \ + socfpga_arria10_mercury_aa1_pe3_emmc.dtb \ + socfpga_arria10_mercury_aa1_pe3_qspi.dtb \ + socfpga_arria10_mercury_aa1_pe3_sdmmc.dtb \ + socfpga_arria10_mercury_aa1_st1_emmc.dtb \ + socfpga_arria10_mercury_aa1_st1_qspi.dtb \ + socfpga_arria10_mercury_aa1_st1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb \ + socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe3_emmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe3_qspi.dtb \ + socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa1_st1_emmc.dtb \ + socfpga_cyclone5_mercury_sa1_st1_qspi.dtb \ + socfpga_cyclone5_mercury_sa1_st1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa2_pe1_qspi.dtb \ + socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa2_pe3_qspi.dtb \ + socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa2_st1_qspi.dtb \ + socfpga_cyclone5_mercury_sa2_st1_sdmmc.dtb \ socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_emmc.dts new file mode 100644 index 000000000..b6cca0b5f --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_emmc.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_qspi.dts new file mode 100644 index 000000000..6ad023477 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_qspi.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_p= e1_sdmmc.dts new file mode 100644 index 000000000..653c9a865 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_sdmmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_emmc.dts new file mode 100644 index 000000000..ae9c7c6a2 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_emmc.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_qspi.dts new file mode 100644 index 000000000..c3a0c30a0 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_qspi.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_p= e3_sdmmc.dts new file mode 100644 index 000000000..dc1e1ad20 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_sdmmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_emmc.dts new file mode 100644 index 000000000..61d5e4c85 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_emmc.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_qspi.dts new file mode 100644 index 000000000..a3b99c9b1 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_qspi.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_s= t1_sdmmc.dts new file mode 100644 index 000000000..5deb289e2 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_sdmmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= pe1_emmc.dts new file mode 100644 index 000000000..85d6146da --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= pe1_qspi.dts new file mode 100644 index 000000000..770ab680a --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1= _pe1_sdmmc.dts new file mode 100644 index 000000000..990ca0fec --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e3_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= pe3_emmc.dts new file mode 100644 index 000000000..6c8fd5b0d --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= pe3_qspi.dts new file mode 100644 index 000000000..329242607 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1= _pe3_sdmmc.dts new file mode 100644 index 000000000..1eb10b524 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_s= t1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= st1_emmc.dts new file mode 100644 index 000000000..8c97b5b3a --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_s= t1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= st1_qspi.dts new file mode 100644 index 000000000..e6d14b22e --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_s= t1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1= _st1_sdmmc.dts new file mode 100644 index 000000000..beaeca94d --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_p= e1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_= pe1_qspi.dts new file mode 100644 index 000000000..6f79d9ed1 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa2-pe1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_p= e1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2= _pe1_sdmmc.dts new file mode 100644 index 000000000..b94bd8baf --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa2-pe1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_p= e3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_= pe3_qspi.dts new file mode 100644 index 000000000..51fc4a229 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa2-pe3", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_p= e3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2= _pe3_sdmmc.dts new file mode 100644 index 000000000..e4209209f --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa2-pe3", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_s= t1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_= st1_qspi.dts new file mode 100644 index 000000000..ab4549a0d --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_s= t1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2= _st1_sdmmc.dts new file mode 100644 index 000000000..ebe62879c --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; --=20 2.25.1