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[2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53b2e1c901esm642356e87.219.2024.10.26.18.25.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Oct 2024 18:25:10 -0700 (PDT) From: Dmitry Baryshkov Date: Sun, 27 Oct 2024 03:24:50 +0200 Subject: [PATCH v5 11/11] clk: qcom: add SAR2130P GPU Clock Controller support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241027-sar2130p-clocks-v5-11-ecad2a1432ba@linaro.org> References: <20241027-sar2130p-clocks-v5-0-ecad2a1432ba@linaro.org> In-Reply-To: <20241027-sar2130p-clocks-v5-0-ecad2a1432ba@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Neil Armstrong , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=15866; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=QcqUOxgg/y4ZBn/2Y2/evEjo2y+rRARRfziAJnkVn7s=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnHZZjgTorYcuhiSB2as+xdCexFzt/yJTWeAF1l S/Td0F1lsWJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZx2WYwAKCRAU23LtvoBl uMm9D/9eBOaaBC79ffErFCzmbBIYXnwPw0P99SwsYMX1Jnb1PZ1HkE6dgahQz2E3/erdJOi+gJ7 j8Pg3qjImlZupJ2CiIwKqF0vuQXS1YBptqwjRdczEqEvpMQLU5G509jQVENU06vSOuwFVoh/GwV 4nejfYX2PmUP9BYPlvnNWSf03Y2/AJOUj/2kUXpCOVV8XJKuRcsoz/VjLUbMAn7ZyBIb/18gpuM u4SjVEYYkIiwYa/I1AUNJQsfsVA5E1WbTygg9h+79gW0ETW1wIZXgseQK1VaxL/4GW0og1zqk3o uaLUb/SVTpY7EVDFrdILwcOYd98PKoGI1iXqtmT3PilWgi2x0rEpwnYywYdNLVjt9NFanPATW0y sEQvCqcxWa28p5hJ8tBT924j0mPIfrtocM1nbqZygs7Benq34nbkgZnzfVzYQfxnzVgUJB7Ua5+ 4iXJFQ0gY7p6RhoBPMEWZGD6vZTX+rE0OPW+whG2sx+ewyFiRaOuOfcppfRgNiLaT22Gy1Fwstw CQ24X65MAVLcdke6bi5Sg28rr0OuK850hciojnknth+jGA5DxUBUdWkF7UO/qOVh1RAIsr1B6QP z2ZuNVYd3ybkIj9b9vbA6HRy4e97jzwvvzRXwm4CIDUW3eohikpGKcJcBBHro945zrE12tgPY7q Ri4aRvv3qp+Aj9g== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A From: Konrad Dybcio Add support for the GPU Clock Controller as used on the SAR2130P and SAR1130P platforms. Signed-off-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sar2130p.c | 502 ++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 512 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 77a4139d222ec7dea87d63b24896324973e4838b..678b1ebd9785be066fc202dd786= 5a6c6ff342465 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -574,6 +574,15 @@ config SAR_GCC_2130P Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, SDCC, etc. =20 +config SAR_GPUCC_2130P + tristate "SAR2130P Graphics clock controller" + select QCOM_GDSC + select SAR_GCC_2130P + help + Support for the graphics clock controller on SAR2130P devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SC_GCC_7180 tristate "SC7180 Global Clock Controller" select QCOM_GDSC diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 992192ea231c0b10fe81982c175302a6b782e2fd..c581e65f173c81aafe385a53ea8= a5c07a4c3e32e 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -86,6 +86,7 @@ obj-$(CONFIG_SA_GCC_8775P) +=3D gcc-sa8775p.o obj-$(CONFIG_SA_GPUCC_8775P) +=3D gpucc-sa8775p.o obj-$(CONFIG_SA_VIDEOCC_8775P) +=3D videocc-sa8775p.o obj-$(CONFIG_SAR_GCC_2130P) +=3D gcc-sar2130p.o +obj-$(CONFIG_SAR_GPUCC_2130P) +=3D gpucc-sar2130p.o obj-$(CONFIG_SC_GCC_7180) +=3D gcc-sc7180.o obj-$(CONFIG_SC_GCC_7280) +=3D gcc-sc7280.o obj-$(CONFIG_SC_GCC_8180X) +=3D gcc-sc8180x.o diff --git a/drivers/clk/qcom/gpucc-sar2130p.c b/drivers/clk/qcom/gpucc-sar= 2130p.c new file mode 100644 index 0000000000000000000000000000000000000000..dd72b2a48c42da1e14fb1e87a7d= cd5f17b1a43ad --- /dev/null +++ b/drivers/clk/qcom/gpucc-sar2130p.c @@ -0,0 +1,502 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2024, Linaro Limited + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GPLL0_OUT_MAIN, + DT_GPLL0_OUT_MAIN_DIV, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL1_OUT_MAIN, +}; + +static const struct pll_vco lucid_ole_vco[] =3D { + { 249600000, 2000000000, 0 }, +}; + +/* 470MHz Configuration */ +static const struct alpha_pll_config gpu_cc_pll0_config =3D { + .l =3D 0x18, + .alpha =3D 0x7aaa, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000005, +}; + +static struct clk_alpha_pll gpu_cc_pll0 =3D { + .offset =3D 0x0, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +/* 440MHz Configuration */ +static const struct alpha_pll_config gpu_cc_pll1_config =3D { + .l =3D 0x16, + .alpha =3D 0xeaaa, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000005, +}; + +static struct clk_alpha_pll gpu_cc_pll1 =3D { + .offset =3D 0x1000, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_pll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_GPLL0_OUT_MAIN }, + { .index =3D DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .hw =3D &gpu_cc_pll1.clkr.hw }, + { .index =3D DT_GPLL0_OUT_MAIN }, + { .index =3D DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct parent_map gpu_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpu_cc_pll1.clkr.hw }, + { .index =3D DT_GPLL0_OUT_MAIN }, + { .index =3D DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] =3D { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_ff_clk_src =3D { + .cmd_rcgr =3D 0x9474, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_0, + .freq_tbl =3D ftbl_gpu_cc_ff_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_ff_clk_src", + .parent_data =3D gpu_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(220000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(550000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src =3D { + .cmd_rcgr =3D 0x9318, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_1, + .freq_tbl =3D ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gmu_clk_src", + .parent_data =3D gpu_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src =3D { + .cmd_rcgr =3D 0x93ec, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_2, + .freq_tbl =3D ftbl_gpu_cc_ff_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_clk_src", + .parent_data =3D gpu_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_2), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk =3D { + .halt_reg =3D 0x911c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x911c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk =3D { + .halt_reg =3D 0x9120, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9120, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_crc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_ff_clk =3D { + .halt_reg =3D 0x914c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x914c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_ff_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_ff_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk =3D { + .halt_reg =3D 0x913c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x913c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_gmu_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk =3D { + .halt_reg =3D 0x9004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cxo_aon_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk =3D { + .halt_reg =3D 0x9144, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9144, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cxo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gmu_clk =3D { + .halt_reg =3D 0x90bc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x90bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gx_gmu_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk =3D { + .halt_reg =3D 0x93e8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x93e8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_aon_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk =3D { + .halt_reg =3D 0x9148, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9148, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_cx_int_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_memnoc_gfx_clk =3D { + .halt_reg =3D 0x9150, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9150, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_memnoc_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk =3D { + .halt_reg =3D 0x7000, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk =3D { + .halt_reg =3D 0x9134, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9134, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cx_gdsc =3D { + .gdscr =3D 0x9108, + .gds_hw_ctrl =3D 0x953c, + .clk_dis_wait_val =3D 8, + .pd =3D { + .name =3D "gpu_cx_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE | RETAIN_FF_ENABLE, +}; + +static struct gdsc gpu_gx_gdsc =3D { + .gdscr =3D 0x905c, + .clamp_io_ctrl =3D 0x9504, + .resets =3D (unsigned int []){ GPUCC_GPU_CC_GX_BCR, + GPUCC_GPU_CC_ACD_BCR, + GPUCC_GPU_CC_GX_ACD_IROOT_BCR }, + .reset_count =3D 3, + .pd =3D { + .name =3D "gpu_gx_gdsc", + .power_on =3D gdsc_gx_do_nothing_enable, + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D CLAMP_IO | AON_RESET | SW_RESET, +}; + +static struct clk_regmap *gpu_cc_sar2130p_clocks[] =3D { + [GPU_CC_AHB_CLK] =3D &gpu_cc_ahb_clk.clkr, + [GPU_CC_CRC_AHB_CLK] =3D &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_FF_CLK] =3D &gpu_cc_cx_ff_clk.clkr, + [GPU_CC_CX_GMU_CLK] =3D &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CXO_AON_CLK] =3D &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] =3D &gpu_cc_cxo_clk.clkr, + [GPU_CC_FF_CLK_SRC] =3D &gpu_cc_ff_clk_src.clkr, + [GPU_CC_GMU_CLK_SRC] =3D &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_GMU_CLK] =3D &gpu_cc_gx_gmu_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] =3D &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, + [GPU_CC_HUB_AON_CLK] =3D &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] =3D &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] =3D &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_MEMNOC_GFX_CLK] =3D &gpu_cc_memnoc_gfx_clk.clkr, + [GPU_CC_PLL0] =3D &gpu_cc_pll0.clkr, + [GPU_CC_PLL1] =3D &gpu_cc_pll1.clkr, + [GPU_CC_SLEEP_CLK] =3D &gpu_cc_sleep_clk.clkr, +}; + +static const struct qcom_reset_map gpu_cc_sar2130p_resets[] =3D { + [GPUCC_GPU_CC_ACD_BCR] =3D { 0x9358 }, + [GPUCC_GPU_CC_GX_ACD_IROOT_BCR] =3D { 0x958c }, + [GPUCC_GPU_CC_GX_BCR] =3D { 0x9058 }, +}; + +static struct gdsc *gpu_cc_sar2130p_gdscs[] =3D { + [GPU_CX_GDSC] =3D &gpu_cx_gdsc, + [GPU_GX_GDSC] =3D &gpu_gx_gdsc, +}; + +static const struct regmap_config gpu_cc_sar2130p_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xa000, + .fast_io =3D true, +}; + +static const struct qcom_cc_desc gpu_cc_sar2130p_desc =3D { + .config =3D &gpu_cc_sar2130p_regmap_config, + .clks =3D gpu_cc_sar2130p_clocks, + .num_clks =3D ARRAY_SIZE(gpu_cc_sar2130p_clocks), + .resets =3D gpu_cc_sar2130p_resets, + .num_resets =3D ARRAY_SIZE(gpu_cc_sar2130p_resets), + .gdscs =3D gpu_cc_sar2130p_gdscs, + .num_gdscs =3D ARRAY_SIZE(gpu_cc_sar2130p_gdscs), +}; + +static const struct of_device_id gpu_cc_sar2130p_match_table[] =3D { + { .compatible =3D "qcom,sar2130p-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sar2130p_match_table); + +static int gpu_cc_sar2130p_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct regmap *regmap; + + regmap =3D qcom_cc_map(pdev, &gpu_cc_sar2130p_desc); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "Couldn't map GPU_CC\n"); + + clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); + clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); + + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x900c); /* GPU_CC_DEMET_CLK */ + + return qcom_cc_really_probe(dev, &gpu_cc_sar2130p_desc, regmap); +} + +static struct platform_driver gpu_cc_sar2130p_driver =3D { + .probe =3D gpu_cc_sar2130p_probe, + .driver =3D { + .name =3D "gpu_cc-sar2130p", + .of_match_table =3D gpu_cc_sar2130p_match_table, + }, +}; +module_platform_driver(gpu_cc_sar2130p_driver); + +MODULE_DESCRIPTION("QTI GPU_CC SAR2130P Driver"); +MODULE_LICENSE("GPL"); --=20 2.39.5