From nobody Sat Feb 7 21:40:39 2026 Received: from mx.treblig.org (mx.treblig.org [46.235.229.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A54C101C8 for ; Sat, 26 Oct 2024 22:00:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.229.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729980033; cv=none; b=fKNW0vV0KDnSBty7JGd6FnDBLaqxcGpmxxGtQLtaH4zrDJfI8uiUMk0LemJUGZydZTkL+Pp90FCeqcfdA2TgwyrK3oqs4X1DLOxFKxpIN9kD1X+4lTyxdu+hqQdxZcfi7Y4bfAyO3pkfsIQiRcjTyHunceB5myhWwW9BKWVxVug= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729980033; c=relaxed/simple; bh=lTdgo/ISQQnx/IA94CRiHfEF7Ima0TMv3qQ+vM6PUKE=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=Md4smUsxLJAoohB7zeQ9uAMAUqIcjDr4NyNrW/UFCrwSunXLCfzPLC1aUxN3IWXdv00ArOnLM4rLIWJiB9EoQcm6qxpHjdqAevAqJ65CoJR8gtaU4HnPRv7ghTbCZv1+mxIoGXOdmi4FHAzv6S3TSZDGXQZW4dCPpGDqp+L0A/w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=treblig.org; spf=pass smtp.mailfrom=treblig.org; dkim=pass (2048-bit key) header.d=treblig.org header.i=@treblig.org header.b=huPsk1e/; arc=none smtp.client-ip=46.235.229.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=treblig.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=treblig.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=treblig.org header.i=@treblig.org header.b="huPsk1e/" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=treblig.org ; s=bytemarkmx; h=MIME-Version:Message-ID:Date:Subject:From:Content-Type:From :Subject; bh=v8HoMq4531jF00RJXMw2xIWyQpbKLYJOPjHbtvEZNF0=; b=huPsk1e/0Jtaey5E b3BLMp7507U79Tvukvaf42QI91uzvBas1ztGwyCrqLSSumUYBrx9o0dhusTrc48omKiv/46Wfx7IF GikcMR47m+Sn7G5A1Lxp+QDp1V09F54xHzISVBYNjZni/b1lX2lEp9JFUf+W5FQlZgutFl+T/6p7X 5GupH1STIfG2cBg8grHovWGIseC+nzCMzK2S/g6zlrjgin+vwNceSYT58Et17xkwK43DGWic7BRXY PCNhHNJCSGtMIIEG0PDqhDw52E/bnpWcMwWzScZskP5suakpjl1W26Aqo5vrdgcerLon9OAtPmVQy x4nbWxCwlnxVqfuEAg==; Received: from localhost ([127.0.0.1] helo=dalek.home.treblig.org) by mx.treblig.org with esmtp (Exim 4.96) (envelope-from ) id 1t4opP-00DjmR-1v; Sat, 26 Oct 2024 22:00:11 +0000 From: linux@treblig.org To: tomi.valkeinen@ideasonboard.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, "Dr. David Alan Gilbert" Subject: [PATCH] drm/omap: Clean up deadcode functions Date: Sat, 26 Oct 2024 23:00:10 +0100 Message-ID: <20241026220010.93773-1-linux@treblig.org> X-Mailer: git-send-email 2.47.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "Dr. David Alan Gilbert" dispc_enable_fifomerge() last use was removed by 2012's commit 85099f11bd03 ("Revert "OMAPDSS: APPLY: add fifo merge support funcs"") dispc_has_writeback(), dispc_wb_get_framedone_irq(), dispc_wb_go(), dispc_wb_go_busy() and dispc_wb_setup() were changed from statics to public symbols and unwired from a structure by 2020's commit dac62bcafeaa ("drm/omap: remove dispc_ops") but didn't have any users. dispc_mgr_get_clock_div() got renamed from dispc_get_clock_div() and it's last use was removed in 2011 by commit 42c9dee82129 ("OMAP: DSS2: Remove FB_OMAP_BOOTLOADER_INIT support") Remove them. Signed-off-by: Dr. David Alan Gilbert --- drivers/gpu/drm/omapdrm/dss/dispc.c | 146 ---------------------------- drivers/gpu/drm/omapdrm/dss/dss.h | 13 --- 2 files changed, 159 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/= dss/dispc.c index 993691b3cc7e..9344855c4887 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -691,11 +691,6 @@ u32 dispc_mgr_get_sync_lost_irq(struct dispc_device *d= ispc, return mgr_desc[channel].sync_lost_irq; } =20 -u32 dispc_wb_get_framedone_irq(struct dispc_device *dispc) -{ - return DISPC_IRQ_FRAMEDONEWB; -} - void dispc_mgr_enable(struct dispc_device *dispc, enum omap_channel channel, bool enable) { @@ -726,30 +721,6 @@ void dispc_mgr_go(struct dispc_device *dispc, enum oma= p_channel channel) mgr_fld_write(dispc, channel, DISPC_MGR_FLD_GO, 1); } =20 -bool dispc_wb_go_busy(struct dispc_device *dispc) -{ - return REG_GET(dispc, DISPC_CONTROL2, 6, 6) =3D=3D 1; -} - -void dispc_wb_go(struct dispc_device *dispc) -{ - enum omap_plane_id plane =3D OMAP_DSS_WB; - bool enable, go; - - enable =3D REG_GET(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 0) =3D=3D 1; - - if (!enable) - return; - - go =3D REG_GET(dispc, DISPC_CONTROL2, 6, 6) =3D=3D 1; - if (go) { - DSSERR("GO bit not down for WB\n"); - return; - } - - REG_FLD_MOD(dispc, DISPC_CONTROL2, 1, 6, 6); -} - static void dispc_ovl_write_firh_reg(struct dispc_device *dispc, enum omap_plane_id plane, int reg, u32 value) @@ -1498,17 +1469,6 @@ void dispc_ovl_set_fifo_threshold(struct dispc_devic= e *dispc, min(high, 0xfffu)); } =20 -void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable) -{ - if (!dispc_has_feature(dispc, FEAT_FIFO_MERGE)) { - WARN_ON(enable); - return; - } - - DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled"); - REG_FLD_MOD(dispc, DISPC_CONFIG, enable ? 1 : 0, 14, 14); -} - void dispc_ovl_compute_fifo_thresholds(struct dispc_device *dispc, enum omap_plane_id plane, u32 *fifo_low, u32 *fifo_high, @@ -2814,95 +2774,6 @@ int dispc_ovl_setup(struct dispc_device *dispc, return r; } =20 -int dispc_wb_setup(struct dispc_device *dispc, - const struct omap_dss_writeback_info *wi, - bool mem_to_mem, const struct videomode *vm, - enum dss_writeback_channel channel_in) -{ - int r; - u32 l; - enum omap_plane_id plane =3D OMAP_DSS_WB; - const int pos_x =3D 0, pos_y =3D 0; - const u8 zorder =3D 0, global_alpha =3D 0; - const bool replication =3D true; - bool truncation; - int in_width =3D vm->hactive; - int in_height =3D vm->vactive; - enum omap_overlay_caps caps =3D - OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA; - - if (vm->flags & DISPLAY_FLAGS_INTERLACED) - in_height /=3D 2; - - DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, " - "rot %d\n", wi->paddr, wi->p_uv_addr, in_width, - in_height, wi->width, wi->height, wi->fourcc, wi->rotation); - - r =3D dispc_ovl_setup_common(dispc, plane, caps, wi->paddr, wi->p_uv_addr, - wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width, - wi->height, wi->fourcc, wi->rotation, zorder, - wi->pre_mult_alpha, global_alpha, wi->rotation_type, - replication, vm, mem_to_mem, DRM_COLOR_YCBCR_BT601, - DRM_COLOR_YCBCR_LIMITED_RANGE); - if (r) - return r; - - switch (wi->fourcc) { - case DRM_FORMAT_RGB565: - case DRM_FORMAT_RGB888: - case DRM_FORMAT_ARGB4444: - case DRM_FORMAT_RGBA4444: - case DRM_FORMAT_RGBX4444: - case DRM_FORMAT_ARGB1555: - case DRM_FORMAT_XRGB1555: - case DRM_FORMAT_XRGB4444: - truncation =3D true; - break; - default: - truncation =3D false; - break; - } - - /* setup extra DISPC_WB_ATTRIBUTES */ - l =3D dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); - l =3D FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */ - l =3D FLD_MOD(l, channel_in, 18, 16); /* CHANNELIN */ - l =3D FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */ - if (mem_to_mem) - l =3D FLD_MOD(l, 1, 26, 24); /* CAPTUREMODE */ - else - l =3D FLD_MOD(l, 0, 26, 24); /* CAPTUREMODE */ - dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l); - - if (mem_to_mem) { - /* WBDELAYCOUNT */ - REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0); - } else { - u32 wbdelay; - - if (channel_in =3D=3D DSS_WB_TV_MGR) - wbdelay =3D vm->vsync_len + vm->vback_porch; - else - wbdelay =3D vm->vfront_porch + vm->vsync_len + - vm->vback_porch; - - if (vm->flags & DISPLAY_FLAGS_INTERLACED) - wbdelay /=3D 2; - - wbdelay =3D min(wbdelay, 255u); - - /* WBDELAYCOUNT */ - REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0); - } - - return 0; -} - -bool dispc_has_writeback(struct dispc_device *dispc) -{ - return dispc->feat->has_writeback; -} - int dispc_ovl_enable(struct dispc_device *dispc, enum omap_plane_id plane, bool enable) { @@ -3742,23 +3613,6 @@ void dispc_mgr_set_clock_div(struct dispc_device *di= spc, cinfo->pck_div); } =20 -int dispc_mgr_get_clock_div(struct dispc_device *dispc, - enum omap_channel channel, - struct dispc_clock_info *cinfo) -{ - unsigned long fck; - - fck =3D dispc_fclk_rate(dispc); - - cinfo->lck_div =3D REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); - cinfo->pck_div =3D REG_GET(dispc, DISPC_DIVISORo(channel), 7, 0); - - cinfo->lck =3D fck / cinfo->lck_div; - cinfo->pck =3D cinfo->lck / cinfo->pck_div; - - return 0; -} - u32 dispc_read_irqstatus(struct dispc_device *dispc) { return dispc_read_reg(dispc, DISPC_IRQSTATUS); diff --git a/drivers/gpu/drm/omapdrm/dss/dss.h b/drivers/gpu/drm/omapdrm/ds= s/dss.h index 4ff02fbc0e71..a8b231ed4f4b 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss.h +++ b/drivers/gpu/drm/omapdrm/dss/dss.h @@ -416,7 +416,6 @@ u32 dispc_mgr_get_framedone_irq(struct dispc_device *di= spc, enum omap_channel channel); u32 dispc_mgr_get_sync_lost_irq(struct dispc_device *dispc, enum omap_channel channel); -u32 dispc_wb_get_framedone_irq(struct dispc_device *dispc); =20 u32 dispc_get_memory_bandwidth_limit(struct dispc_device *dispc); =20 @@ -458,20 +457,11 @@ int dispc_ovl_setup(struct dispc_device *dispc, int dispc_ovl_enable(struct dispc_device *dispc, enum omap_plane_id plane, bool enable); =20 -bool dispc_has_writeback(struct dispc_device *dispc); -int dispc_wb_setup(struct dispc_device *dispc, - const struct omap_dss_writeback_info *wi, - bool mem_to_mem, const struct videomode *vm, - enum dss_writeback_channel channel_in); -bool dispc_wb_go_busy(struct dispc_device *dispc); -void dispc_wb_go(struct dispc_device *dispc); - void dispc_enable_sidle(struct dispc_device *dispc); void dispc_disable_sidle(struct dispc_device *dispc); =20 void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable); void dispc_pck_free_enable(struct dispc_device *dispc, bool enable); -void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable); =20 typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck, unsigned long pck, void *data); @@ -494,9 +484,6 @@ void dispc_ovl_compute_fifo_thresholds(struct dispc_dev= ice *dispc, void dispc_mgr_set_clock_div(struct dispc_device *dispc, enum omap_channel channel, const struct dispc_clock_info *cinfo); -int dispc_mgr_get_clock_div(struct dispc_device *dispc, - enum omap_channel channel, - struct dispc_clock_info *cinfo); void dispc_set_tv_pclk(struct dispc_device *dispc, unsigned long pclk); =20 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS --=20 2.47.0