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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL02EPF0001A0FF.mail.protection.outlook.com (10.167.242.106) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8093.14 via Frontend Transport; Sat, 26 Oct 2024 07:54:14 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Sat, 26 Oct 2024 02:54:12 -0500 Received: from xhdakumarma40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Sat, 26 Oct 2024 02:54:07 -0500 From: Amit Kumar Mahapatra To: , , , , , , , , , CC: , , , , , , , , , , , , , , Amit Kumar Mahapatra Subject: [RFC PATCH 2/2] dt-bindings: spi: Update stacked and parallel bindings Date: Sat, 26 Oct 2024 13:23:47 +0530 Message-ID: <20241026075347.580858-3-amit.kumar-mahapatra@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241026075347.580858-1-amit.kumar-mahapatra@amd.com> References: <20241026075347.580858-1-amit.kumar-mahapatra@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Oct 2024 07:54:14.1289 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7da072c1-1097-459b-0c34-08dcf5936289 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5733 For implementing the proposed solution the current 'stacked-memories' & 'parallel-memories' bindings need to be updated as follow. stacked-memories binding changes: - Each flash will have its own flash node. This approach allows flashes of different makes and sizes to be stacked together, as each flash will be probed individually. - Each of the flash node will have its own =E2=80=9Creg=E2=80=9D property t= hat will contain its physical CS. - Remove the size information from the bindings as it can be retrived drirectly from the flash. - The stacked-memories DT bindings will contain the phandles of the flash nodes connected in stacked mode. The new layer will update the mtd->size and other mtd_info parameters after both the flashes are probed and will call mtd_device_register with the combined information. spi@0 { ... flash@0 { compatible =3D "jedec,spi-nor" reg =3D <0x00>; stacked-memories =3D <&flash@0 &flash@1>; spi-max-frequency =3D <50000000>; ... partitions { compatible =3D "fixed-partitions"; concat-partition =3D <&flash0_partition &fl= ash1_partition>; flash0_partition: partition@0 { label =3D "part0_0"; reg =3D <0x0 0x800000>; } } } flash@1 { compatible =3D "jedec,spi-nor" reg =3D <0x01>; stacked-memories =3D <&flash@0 &flash@1>; spi-max-frequency =3D <50000000>; ... partitions { compatible =3D "fixed-partitions"; concat-partition =3D <&flash0_partition &fl= ash1_partition>; flash1_partition: partition@0 { label =3D "part0_1"; reg =3D <0x0 0x800000>; } } } } parallel-memories binding changes: - Remove the size information from the bindings and change the type to boolen. - Each flash connected in parallel mode should be identical and will have one flash node for both the flash devices. - The =E2=80=9Creg=E2=80=9D prop will contain the physical CS number for bo= th the connected flashes. The new layer will double the mtd-> size and register it with the mtd layer. spi@1 { ... flash@3 { compatible =3D "jedec,spi-nor" reg =3D <0x00 0x01>; paralle-memories ; spi-max-frequency =3D <50000000>; ... partitions { compatible =3D "fixed-partitions"; flash0_partition: partition@0 { label =3D "part0_0"; reg =3D <0x0 0x800000>; } } } } Signed-off-by: Amit Kumar Mahapatra --- .../bindings/spi/spi-controller.yaml | 23 +++++++++++++++++-- .../bindings/spi/spi-peripheral-props.yaml | 9 +++----- 2 files changed, 24 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/spi-controller.yaml b/Do= cumentation/devicetree/bindings/spi/spi-controller.yaml index 093150c0cb87..2d300f98dd72 100644 --- a/Documentation/devicetree/bindings/spi/spi-controller.yaml +++ b/Documentation/devicetree/bindings/spi/spi-controller.yaml @@ -185,7 +185,26 @@ examples: flash@2 { compatible =3D "jedec,spi-nor"; spi-max-frequency =3D <50000000>; - reg =3D <2>, <3>; - stacked-memories =3D /bits/ 64 <0x10000000 0x10000000>; + reg =3D <2>; + stacked-memories =3D <&flash0 &flash1>; }; + }; + + - | + spi@90010000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "fsl,imx28-spi"; + reg =3D <0x90010000 0x2000>; + interrupts =3D <96>; + dmas =3D <&dma_apbh 0>; + dma-names =3D "rx-tx"; + + flash@0 { + compatible =3D "jedec,spi-nor"; + spi-max-frequency =3D <50000000>; + reg =3D <0>, <1>; + parallel-memories; + }; + }; diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yam= l b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 15938f81fdce..2a014160d701 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -96,7 +96,7 @@ properties: space with only a single additional wire, while still needing to repeat the commands when crossing a chip boundary. The size of each chip should be provided as members of the array. - $ref: /schemas/types.yaml#/definitions/uint64-array + $ref: /schemas/types.yaml#/definitions/phandle-array minItems: 2 maxItems: 4 =20 @@ -107,11 +107,8 @@ properties: different memories (eg. even bits are stored in one memory, odd bits in the other). This basically doubles the address space and the throughput while greatly complexifying the wiring because as - many busses as devices must be wired. The size of each chip should - be provided as members of the array. - $ref: /schemas/types.yaml#/definitions/uint64-array - minItems: 2 - maxItems: 4 + many busses as devices must be wired. + $ref: /schemas/types.yaml#/definitions/flag =20 st,spi-midi-ns: description: | --=20 2.34.1