From nobody Mon Nov 25 13:21:00 2024 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7732C16FF26 for ; Sat, 26 Oct 2024 06:36:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729924562; cv=none; b=i++O97zTKwg84tD+I5YDIQolCiirfthIDEtmyQQ+N0mooLQF4pnq4PZuEUpdheOi0zsYNKqOeoBb94oaUHB5C1ol2VqTjls60Bb7gHKEkfiT7NVHR59eEubkxMiXeRMV1mrtCZeq2l8UTOR660mY4q3yLPh3xL9L07QDZRialtc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729924562; c=relaxed/simple; bh=XhhlPW5HdHIUc2ZkO1pDx1e70v9CbBmfAAPQ/paIVbQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XKdQJmTsggBCQJlndJP9tmIpDArzsuxw5L60HkH+7jnpB3CcuU6xAgT2PlDy+vry+HIX9MJpXGESdfpx9z20xvahouJoXKA/N3QUSngOV3W61NE5XCzBi2Qbgs7SUxlUQJvCUiNQbSbMitnV8SeZzp9IWauqrSIq/kXqfslz7Mw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1t4aOj-0006kA-1m; Sat, 26 Oct 2024 08:35:41 +0200 Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac]) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1t4aOh-000UfL-0I; Sat, 26 Oct 2024 08:35:39 +0200 Received: from ore by dude04.red.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1t4aOh-00AVyJ-00; Sat, 26 Oct 2024 08:35:39 +0200 From: Oleksij Rempel To: "David S. Miller" , Andrew Lunn , Eric Dumazet , Florian Fainelli , Jakub Kicinski , Paolo Abeni , Vladimir Oltean , Woojung Huh , Arun Ramadoss , Conor Dooley , Krzysztof Kozlowski , Rob Herring Cc: Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, UNGLinuxDriver@microchip.com, "Russell King (Oracle)" , devicetree@vger.kernel.org Subject: [PATCH net-next v1 1/5] dt-bindings: net: dsa: ksz: add internal MDIO bus description Date: Sat, 26 Oct 2024 08:35:34 +0200 Message-Id: <20241026063538.2506143-2-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241026063538.2506143-1-o.rempel@pengutronix.de> References: <20241026063538.2506143-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add description for the internal MDIO bus, including integrated PHY nodes, to ksz DSA bindings. Signed-off-by: Oleksij Rempel Reviewed-by: Andrew Lunn Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/net/dsa/microchip,ksz.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml b= /Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml index 30c0c3e6f37a4..a4e463819d4d7 100644 --- a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml +++ b/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml @@ -81,6 +81,17 @@ properties: interrupts: maxItems: 1 =20 + mdio: + $ref: /schemas/net/mdio.yaml# + unevaluatedProperties: false + patternProperties: + "^ethernet-phy@[0-9a-f]$": + type: object + $ref: /schemas/net/ethernet-phy.yaml# + unevaluatedProperties: false + description: + Integrated PHY node + required: - compatible - reg --=20 2.39.5 From nobody Mon Nov 25 13:21:00 2024 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 258BE166F29 for ; Sat, 26 Oct 2024 06:35:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729924561; cv=none; b=mk1hd0Oa6UNoyCRpDnkIhzOr8yFG6eXapOlgqA08dfWBWoXkDFd1RWjMMBpQ+e6VkaceHg9MoZpNie9OxtnOKn6krFGjLTlPRxJ+7Mjcz3qZYcdjTvIxlgliwzADEJRvA/s+yU4Gg2kXp19LkoIujgmF9K4MJD1pvCYV4zSX62Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729924561; c=relaxed/simple; bh=KnM1jkiNDNi+pT5UhL74vYUlzz9wd7posbbyo5VAvbk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=I6IKK17wYEycXn3gQ6Kl0cqrJft5x55rE9giFWOThxX2LgT2GoNdRQX1C9NL9okY6cPsWeybEdweiYRwN4lkz4lBUCrnzjgK7wsmCwEyuD2cHmIQRoyc7aMVcx2jXGBNOzrJppO26DIelhDvgFXaQqznOy992UATQPcIszRwXOs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1t4aOj-0006kB-1m; Sat, 26 Oct 2024 08:35:41 +0200 Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac]) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1t4aOh-000UfM-0M; Sat, 26 Oct 2024 08:35:39 +0200 Received: from ore by dude04.red.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1t4aOh-00AVyT-05; Sat, 26 Oct 2024 08:35:39 +0200 From: Oleksij Rempel To: "David S. Miller" , Andrew Lunn , Eric Dumazet , Florian Fainelli , Jakub Kicinski , Paolo Abeni , Vladimir Oltean , Woojung Huh , Arun Ramadoss , Conor Dooley , Krzysztof Kozlowski , Rob Herring Cc: Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, UNGLinuxDriver@microchip.com, "Russell King (Oracle)" , devicetree@vger.kernel.org Subject: [PATCH net-next v1 2/5] dt-bindings: net: dsa: ksz: add mdio-parent-bus property for internal MDIO Date: Sat, 26 Oct 2024 08:35:35 +0200 Message-Id: <20241026063538.2506143-3-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241026063538.2506143-1-o.rempel@pengutronix.de> References: <20241026063538.2506143-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce `mdio-parent-bus` property in the ksz DSA bindings to reference the parent MDIO bus when the internal MDIO bus is attached to it, bypassing the main management interface. Signed-off-by: Oleksij Rempel Reviewed-by: Andrew Lunn Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/net/dsa/microchip,ksz.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml b= /Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml index a4e463819d4d7..121a4bbd147be 100644 --- a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml +++ b/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml @@ -84,6 +84,15 @@ properties: mdio: $ref: /schemas/net/mdio.yaml# unevaluatedProperties: false + properties: + mdio-parent-bus: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle pointing to the MDIO bus controller connected to the + secondary MDIO interface. This property should be used when + the internal MDIO bus is accessed via a secondary MDIO + interface rather than the primary management interface. + patternProperties: "^ethernet-phy@[0-9a-f]$": type: object --=20 2.39.5 From nobody Mon Nov 25 13:21:00 2024 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 563C616E87D for ; Sat, 26 Oct 2024 06:36:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729924562; cv=none; b=bTRtOLZOdpbAhlKn+HCWKzhiD4SjiOxy4SdjUSUEzt4CKOC5NtaB+Fu5CGsaV98Lc8wyCUroOPy6jmvr4Clfu7BxtnzTi5AAxFmq3JSuaUwp7GenyUNqBAmGVpQqCRZxUrjdEV4GetDknEfFXy07tzK1SeJg08KeHKST1JUhgFw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729924562; c=relaxed/simple; bh=DkhzQojUdHucqaY2ayRjdwzYLFQMrQzPbHSW2ueFK3Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BtmYKxCABINzAHhPT+y8Me16lp9bLJ269dqvw21GT2HBqdARpGY1iVQ4JJqudkKr81dgvCpqGZcXKuPqSwiFaqZqk1U+YRHEEuyrdReQTE+hgTiUdzL++7Fdm/uHZ42QS5dn2NGwQ9U9m6aT0rl2elmwLzbhks9DCLSsfWNyP98= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1t4aOj-0006kC-1n; Sat, 26 Oct 2024 08:35:41 +0200 Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac]) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1t4aOh-000UfN-0P; Sat, 26 Oct 2024 08:35:39 +0200 Received: from ore by dude04.red.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1t4aOh-00AVyd-0A; Sat, 26 Oct 2024 08:35:39 +0200 From: Oleksij Rempel To: "David S. Miller" , Andrew Lunn , Eric Dumazet , Florian Fainelli , Jakub Kicinski , Paolo Abeni , Vladimir Oltean , Woojung Huh , Arun Ramadoss , Conor Dooley , Krzysztof Kozlowski , Rob Herring Cc: Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, UNGLinuxDriver@microchip.com, "Russell King (Oracle)" , devicetree@vger.kernel.org Subject: [PATCH net-next v1 3/5] net: dsa: microchip: Refactor MDIO handling for side MDIO access Date: Sat, 26 Oct 2024 08:35:36 +0200 Message-Id: <20241026063538.2506143-4-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241026063538.2506143-1-o.rempel@pengutronix.de> References: <20241026063538.2506143-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for accessing PHYs via a side MDIO interface in LAN937x switches. The existing code already supports accessing PHYs via main management interfaces, which can be SPI, I2C, or MDIO, depending on the chip variant. This patch enables using a side MDIO bus, where SPI is used for the main switch configuration and MDIO for managing the integrated PHYs. On LAN937x, this is optional, allowing them to operate in both configurations: SPI only, or SPI + MDIO. Typically, the SPI interface is used for switch configuration, while MDIO handles PHY management. Additionally, update interrupt controller code to support non-linear port to PHY address mapping, enabling correct interrupt handling for configurations where PHY addresses do not directly correspond to port indexes. This change ensures that the interrupt mechanism properly aligns with the new, flexible PHY address mappings introduced by side MDIO support. Signed-off-by: Oleksij Rempel --- drivers/net/dsa/microchip/ksz_common.c | 102 ++++++++++++++++++++++--- drivers/net/dsa/microchip/ksz_common.h | 7 ++ 2 files changed, 99 insertions(+), 10 deletions(-) diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/micro= chip/ksz_common.c index 5290f5ad98f39..bcd963191cb25 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -2238,16 +2238,51 @@ static int ksz_sw_mdio_write(struct mii_bus *bus, i= nt addr, int regnum, return dev->dev_ops->w_phy(dev, addr, regnum, val); } =20 +static int ksz_parent_mdio_read(struct mii_bus *bus, int addr, int regnum) +{ + struct ksz_device *dev =3D bus->priv; + + return mdiobus_read_nested(dev->parent_mdio_bus, addr, regnum); +} + +static int ksz_parent_mdio_write(struct mii_bus *bus, int addr, int regnum, + u16 val) +{ + struct ksz_device *dev =3D bus->priv; + + return mdiobus_write_nested(dev->parent_mdio_bus, addr, regnum, val); +} + +static int ksz_phy_addr_to_port(struct ksz_device *dev, int addr) +{ + struct dsa_switch *ds =3D dev->ds; + struct dsa_port *dp; + + dsa_switch_for_each_user_port(dp, ds) { + if (dev->info->internal_phy[dp->index] && + dev->phy_addr_map[dp->index] =3D=3D addr) + return dp->index; + } + + return -EINVAL; +} + static int ksz_irq_phy_setup(struct ksz_device *dev) { struct dsa_switch *ds =3D dev->ds; - int phy; + int phy, port; int irq; int ret; =20 - for (phy =3D 0; phy < KSZ_MAX_NUM_PORTS; phy++) { + for (phy =3D 0; phy < PHY_MAX_ADDR; phy++) { if (BIT(phy) & ds->phys_mii_mask) { - irq =3D irq_find_mapping(dev->ports[phy].pirq.domain, + port =3D ksz_phy_addr_to_port(dev, phy); + if (port < 0) { + ret =3D port; + goto out; + } + + irq =3D irq_find_mapping(dev->ports[port].pirq.domain, PORT_SRC_PHY_INT); if (irq < 0) { ret =3D irq; @@ -2270,35 +2305,81 @@ static void ksz_irq_phy_free(struct ksz_device *dev) struct dsa_switch *ds =3D dev->ds; int phy; =20 - for (phy =3D 0; phy < KSZ_MAX_NUM_PORTS; phy++) + for (phy =3D 0; phy < PHY_MAX_ADDR; phy++) if (BIT(phy) & ds->phys_mii_mask) irq_dispose_mapping(ds->user_mii_bus->irq[phy]); } =20 static int ksz_mdio_register(struct ksz_device *dev) { + struct device_node *parent_bus_node; + struct mii_bus *parent_bus =3D NULL; struct dsa_switch *ds =3D dev->ds; struct device_node *mdio_np; struct mii_bus *bus; - int ret; + struct dsa_port *dp; + int ret, i; =20 mdio_np =3D of_get_child_by_name(dev->dev->of_node, "mdio"); if (!mdio_np) return 0; =20 + parent_bus_node =3D of_parse_phandle(mdio_np, "mdio-parent-bus", 0); + if (parent_bus_node && !dev->info->phy_side_mdio_supported) { + dev_warn(dev->dev, "Side MDIO bus is not supported for this HW, ignoring= 'mdio-parent-bus' property.\n"); + } else if (parent_bus_node) { + parent_bus =3D of_mdio_find_bus(parent_bus_node); + if (!parent_bus) { + of_node_put(parent_bus_node); + return -EPROBE_DEFER; + } + + dev->parent_mdio_bus =3D parent_bus; + } + bus =3D devm_mdiobus_alloc(ds->dev); if (!bus) { of_node_put(mdio_np); return -ENOMEM; } =20 + if (dev->dev_ops->mdio_bus_preinit) { + ret =3D dev->dev_ops->mdio_bus_preinit(dev, !!parent_bus); + if (ret) + goto put_mdio_node; + } + + if (dev->dev_ops->create_phy_addr_map) { + ret =3D dev->dev_ops->create_phy_addr_map(dev, !!parent_bus); + if (ret) + goto put_mdio_node; + } else { + for (i =3D 0; i < dev->info->port_cnt; i++) + dev->phy_addr_map[i] =3D i; + } + bus->priv =3D dev; - bus->read =3D ksz_sw_mdio_read; - bus->write =3D ksz_sw_mdio_write; - bus->name =3D "ksz user smi"; - snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); + if (parent_bus) { + bus->read =3D ksz_parent_mdio_read; + bus->write =3D ksz_parent_mdio_write; + bus->name =3D "KSZ side MDIO"; + snprintf(bus->id, MII_BUS_ID_SIZE, "ksz-side-mdio-%d", + ds->index); + } else { + bus->read =3D ksz_sw_mdio_read; + bus->write =3D ksz_sw_mdio_write; + bus->name =3D "ksz user smi"; + snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); + } + + dsa_switch_for_each_user_port(dp, dev->ds) { + if (dev->info->internal_phy[dp->index] && + dev->phy_addr_map[dp->index] < PHY_MAX_ADDR) + bus->phy_mask |=3D BIT(dev->phy_addr_map[dp->index]); + } + + ds->phys_mii_mask =3D bus->phy_mask; bus->parent =3D ds->dev; - bus->phy_mask =3D ~ds->phys_mii_mask; =20 ds->user_mii_bus =3D bus; =20 @@ -2318,6 +2399,7 @@ static int ksz_mdio_register(struct ksz_device *dev) ksz_irq_phy_free(dev); } =20 +put_mdio_node: of_node_put(mdio_np); =20 return ret; diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/micro= chip/ksz_common.h index bec846e20682f..fdfb624d3ff6a 100644 --- a/drivers/net/dsa/microchip/ksz_common.h +++ b/drivers/net/dsa/microchip/ksz_common.h @@ -65,6 +65,8 @@ struct ksz_chip_data { u8 num_tx_queues; u8 num_ipms; /* number of Internal Priority Maps */ bool tc_cbs_supported; + /* PHYs can be accessed via side MDIO channel */ + bool phy_side_mdio_supported; const struct ksz_dev_ops *ops; const struct phylink_mac_ops *phylink_mac_ops; bool phy_errata_9477; @@ -191,6 +193,9 @@ struct ksz_device { struct ksz_switch_macaddr *switch_macaddr; struct net_device *hsr_dev; /* HSR */ u8 hsr_ports; + + u8 phy_addr_map[KSZ_MAX_NUM_PORTS]; + struct mii_bus *parent_mdio_bus; }; =20 /* List of supported models */ @@ -326,6 +331,8 @@ struct ksz_dev_ops { void (*port_cleanup)(struct ksz_device *dev, int port); void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); + int (*mdio_bus_preinit)(struct ksz_device *dev, bool side_mdio); + int (*create_phy_addr_map)(struct ksz_device *dev, bool side_mdio); int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, --=20 2.39.5 From nobody Mon Nov 25 13:21:00 2024 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1230813792B for ; Sat, 26 Oct 2024 06:35:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1t4aOj-0006kD-1l; Sat, 26 Oct 2024 08:35:41 +0200 Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac]) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1t4aOh-000UfO-0Y; Sat, 26 Oct 2024 08:35:39 +0200 Received: from ore by dude04.red.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1t4aOh-00AVyn-0E; Sat, 26 Oct 2024 08:35:39 +0200 From: Oleksij Rempel To: "David S. Miller" , Andrew Lunn , Eric Dumazet , Florian Fainelli , Jakub Kicinski , Paolo Abeni , Vladimir Oltean , Woojung Huh , Arun Ramadoss , Conor Dooley , Krzysztof Kozlowski , Rob Herring Cc: Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, UNGLinuxDriver@microchip.com, "Russell King (Oracle)" , devicetree@vger.kernel.org Subject: [PATCH net-next v1 4/5] net: dsa: microchip: cleanup error handling in ksz_mdio_register Date: Sat, 26 Oct 2024 08:35:37 +0200 Message-Id: <20241026063538.2506143-5-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241026063538.2506143-1-o.rempel@pengutronix.de> References: <20241026063538.2506143-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Replace repeated cleanup code with a single error path using a label. Signed-off-by: Oleksij Rempel Reviewed-by: Andrew Lunn --- drivers/net/dsa/microchip/ksz_common.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/micro= chip/ksz_common.c index bcd963191cb25..f08fa52dd1387 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -2339,8 +2339,8 @@ static int ksz_mdio_register(struct ksz_device *dev) =20 bus =3D devm_mdiobus_alloc(ds->dev); if (!bus) { - of_node_put(mdio_np); - return -ENOMEM; + ret =3D -ENOMEM; + goto put_mdio_node; } =20 if (dev->dev_ops->mdio_bus_preinit) { @@ -2385,10 +2385,8 @@ static int ksz_mdio_register(struct ksz_device *dev) =20 if (dev->irq > 0) { ret =3D ksz_irq_phy_setup(dev); - if (ret) { - of_node_put(mdio_np); - return ret; - } + if (ret) + goto put_mdio_node; } =20 ret =3D devm_of_mdiobus_register(ds->dev, bus, mdio_np); --=20 2.39.5 From nobody Mon Nov 25 13:21:00 2024 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1234814D2B1 for ; Sat, 26 Oct 2024 06:35:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729924562; cv=none; b=E1AeoP7X4npIVCoWp0MPcrH9pa5Xiu6pgYvEw6458kuVWNG8Y5GEzZTEG7DgjEJJKJZSchMD6QOOVIIwY+KA3hbmjB2cQ3eX1/GzMNlVqwEecqn1Rd85Xbq5ZxS7NDlwlWhK4XugNYVu/rURDVzeG5QEJvRxZpy6575+lNM2SC8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729924562; c=relaxed/simple; bh=f+V8MPT6QmFLdLw9T1LU0D9qdTas18Y6uUgw6VeBuI0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QcsdD/pncAJm6/Bo+3ouE7HozX7XKkGRKQV0r6iV1qwCqgsH3A/xvfTDIeXG27dT2HKezg8W+peCVuqWAKdm5FlErPcK8Yomqyy5UStBp4/0Y/o9xUPrgVlCnUy2Uv028qBZvdCOVu9JkqanmQdCTAwxoZqS+jRNQpkNe1F5Juw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1t4aOj-0006kE-1m; Sat, 26 Oct 2024 08:35:41 +0200 Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac]) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1t4aOh-000UfQ-0Y; Sat, 26 Oct 2024 08:35:39 +0200 Received: from ore by dude04.red.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1t4aOh-00AVyx-0H; Sat, 26 Oct 2024 08:35:39 +0200 From: Oleksij Rempel To: "David S. Miller" , Andrew Lunn , Eric Dumazet , Florian Fainelli , Jakub Kicinski , Paolo Abeni , Vladimir Oltean , Woojung Huh , Arun Ramadoss , Conor Dooley , Krzysztof Kozlowski , Rob Herring Cc: Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, UNGLinuxDriver@microchip.com, "Russell King (Oracle)" , devicetree@vger.kernel.org Subject: [PATCH net-next v1 5/5] net: dsa: microchip: add support for side MDIO interface in LAN937x Date: Sat, 26 Oct 2024 08:35:38 +0200 Message-Id: <20241026063538.2506143-6-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241026063538.2506143-1-o.rempel@pengutronix.de> References: <20241026063538.2506143-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Implement side MDIO channel support for LAN937x switches, providing an alternative to SPI for PHY management alongside existing SPI-based switch configuration. This is needed to reduce SPI load, as SPI can be relatively expensive for small packets compared to MDIO support. Also, implemented static mappings for PHY addresses for various LAN937x models to support different internal PHY configurations. Since the PHY address mappings are not equal to the port indexes, this patch also provides PHY address calculation based on hardware strapping configuration. Signed-off-by: Oleksij Rempel --- drivers/net/dsa/microchip/ksz_common.c | 7 ++ drivers/net/dsa/microchip/lan937x.h | 2 + drivers/net/dsa/microchip/lan937x_main.c | 139 ++++++++++++++++++++--- drivers/net/dsa/microchip/lan937x_reg.h | 4 + 4 files changed, 136 insertions(+), 16 deletions(-) diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/micro= chip/ksz_common.c index f08fa52dd1387..303f1342e6cc2 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -411,6 +411,8 @@ static const struct ksz_dev_ops lan937x_dev_ops =3D { .flush_dyn_mac_table =3D ksz9477_flush_dyn_mac_table, .port_setup =3D lan937x_port_setup, .set_ageing_time =3D lan937x_set_ageing_time, + .mdio_bus_preinit =3D lan937x_mdio_bus_preinit, + .create_phy_addr_map =3D lan937x_create_phy_addr_map, .r_phy =3D lan937x_r_phy, .w_phy =3D lan937x_w_phy, .r_mib_cnt =3D ksz9477_r_mib_cnt, @@ -1762,6 +1764,7 @@ const struct ksz_chip_data ksz_switch_chips[] =3D { .num_tx_queues =3D 8, .num_ipms =3D 8, .tc_cbs_supported =3D true, + .phy_side_mdio_supported =3D true, .ops =3D &lan937x_dev_ops, .phylink_mac_ops =3D &lan937x_phylink_mac_ops, .mib_names =3D ksz9477_mib_names, @@ -1790,6 +1793,7 @@ const struct ksz_chip_data ksz_switch_chips[] =3D { .num_tx_queues =3D 8, .num_ipms =3D 8, .tc_cbs_supported =3D true, + .phy_side_mdio_supported =3D true, .ops =3D &lan937x_dev_ops, .phylink_mac_ops =3D &lan937x_phylink_mac_ops, .mib_names =3D ksz9477_mib_names, @@ -1818,6 +1822,7 @@ const struct ksz_chip_data ksz_switch_chips[] =3D { .num_tx_queues =3D 8, .num_ipms =3D 8, .tc_cbs_supported =3D true, + .phy_side_mdio_supported =3D true, .ops =3D &lan937x_dev_ops, .phylink_mac_ops =3D &lan937x_phylink_mac_ops, .mib_names =3D ksz9477_mib_names, @@ -1850,6 +1855,7 @@ const struct ksz_chip_data ksz_switch_chips[] =3D { .num_tx_queues =3D 8, .num_ipms =3D 8, .tc_cbs_supported =3D true, + .phy_side_mdio_supported =3D true, .ops =3D &lan937x_dev_ops, .phylink_mac_ops =3D &lan937x_phylink_mac_ops, .mib_names =3D ksz9477_mib_names, @@ -1882,6 +1888,7 @@ const struct ksz_chip_data ksz_switch_chips[] =3D { .num_tx_queues =3D 8, .num_ipms =3D 8, .tc_cbs_supported =3D true, + .phy_side_mdio_supported =3D true, .ops =3D &lan937x_dev_ops, .phylink_mac_ops =3D &lan937x_phylink_mac_ops, .mib_names =3D ksz9477_mib_names, diff --git a/drivers/net/dsa/microchip/lan937x.h b/drivers/net/dsa/microchi= p/lan937x.h index 3388d91dbc44e..df13ebbd356f9 100644 --- a/drivers/net/dsa/microchip/lan937x.h +++ b/drivers/net/dsa/microchip/lan937x.h @@ -13,6 +13,8 @@ void lan937x_port_setup(struct ksz_device *dev, int port,= bool cpu_port); void lan937x_config_cpu_port(struct dsa_switch *ds); int lan937x_switch_init(struct ksz_device *dev); void lan937x_switch_exit(struct ksz_device *dev); +int lan937x_mdio_bus_preinit(struct ksz_device *dev, bool side_mdio); +int lan937x_create_phy_addr_map(struct ksz_device *dev, bool side_mdio); int lan937x_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data); int lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val); int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu); diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/mic= rochip/lan937x_main.c index 824d9309a3d35..7dfd21d0d2843 100644 --- a/drivers/net/dsa/microchip/lan937x_main.c +++ b/drivers/net/dsa/microchip/lan937x_main.c @@ -18,6 +18,47 @@ #include "ksz9477.h" #include "lan937x.h" =20 +static const u8 lan9370_phy_addr[] =3D { + [0] =3D 2, /* Port 1, T1 AFE0 */ + [1] =3D 3, /* Port 2, T1 AFE1 */ + [2] =3D 5, /* Port 3, T1 AFE3 */ + [3] =3D 6, /* Port 4, T1 AFE4 */ + [4] =3D U8_MAX, /* Port 5, RGMII 2 */ +}; + +static const u8 lan9372_phy_addr[] =3D { + [0] =3D 2, /* Port 1, T1 AFE0 */ + [1] =3D 3, /* Port 2, T1 AFE1 */ + [2] =3D 5, /* Port 3, T1 AFE3 */ + [3] =3D 8, /* Port 4, TX PHY */ + [4] =3D U8_MAX, /* Port 5, RGMII 2 */ + [5] =3D U8_MAX, /* Port 6, RGMII 1 */ + [6] =3D 6, /* Port 7, T1 AFE4 */ + [7] =3D 4, /* Port 8, T1 AFE2 */ +}; + +static const u8 lan9373_phy_addr[] =3D { + [0] =3D 2, /* Port 1, T1 AFE0 */ + [1] =3D 3, /* Port 2, T1 AFE1 */ + [2] =3D 5, /* Port 3, T1 AFE3 */ + [3] =3D U8_MAX, /* Port 4, SGMII */ + [4] =3D U8_MAX, /* Port 5, RGMII 2 */ + [5] =3D U8_MAX, /* Port 6, RGMII 1 */ + [6] =3D 6, /* Port 7, T1 AFE4 */ + [7] =3D 4, /* Port 8, T1 AFE2 */ +}; + +static const u8 lan9374_phy_addr[] =3D { + [0] =3D 2, /* Port 1, T1 AFE0 */ + [1] =3D 3, /* Port 2, T1 AFE1 */ + [2] =3D 5, /* Port 3, T1 AFE3 */ + [3] =3D 7, /* Port 4, T1 AFE5 */ + [4] =3D U8_MAX, /* Port 5, RGMII 2 */ + [5] =3D U8_MAX, /* Port 6, RGMII 1 */ + [6] =3D 6, /* Port 7, T1 AFE4 */ + [7] =3D 4, /* Port 8, T1 AFE2 */ +}; + static int lan937x_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) { return regmap_update_bits(ksz_regmap_8(dev), addr, bits, set ? bits : 0); @@ -30,24 +71,97 @@ static int lan937x_port_cfg(struct ksz_device *dev, int= port, int offset, bits, set ? bits : 0); } =20 -static int lan937x_enable_spi_indirect_access(struct ksz_device *dev) +int lan937x_create_phy_addr_map(struct ksz_device *dev, bool side_mdio) +{ + static const u8 *phy_addr_map; + u32 strap_val; + u8 offset =3D 0; + size_t size; + int ret, i; + + if (!side_mdio) { + /* simple direct mapping */ + for (i =3D 0; i < dev->info->port_cnt; i++) + dev->phy_addr_map[i] =3D i; + + return 0; + } + + ret =3D ksz_read32(dev, REG_SW_CFG_STRAP_VAL, &strap_val); + if (ret < 0) + return ret; + + if (!(strap_val & SW_CASCADE_ID_CFG) && !(strap_val & SW_VPHY_ADD_CFG)) + offset =3D 0; + else if (!(strap_val & SW_CASCADE_ID_CFG) && (strap_val & SW_VPHY_ADD_CFG= )) + offset =3D 7; + else if ((strap_val & SW_CASCADE_ID_CFG) && !(strap_val & SW_VPHY_ADD_CFG= )) + offset =3D 15; + else + offset =3D 22; + + switch (dev->info->chip_id) { + case LAN9370_CHIP_ID: + phy_addr_map =3D lan9370_phy_addr; + size =3D ARRAY_SIZE(lan9370_phy_addr); + break; + case LAN9372_CHIP_ID: + phy_addr_map =3D lan9372_phy_addr; + size =3D ARRAY_SIZE(lan9372_phy_addr); + break; + case LAN9373_CHIP_ID: + phy_addr_map =3D lan9373_phy_addr; + size =3D ARRAY_SIZE(lan9373_phy_addr); + break; + case LAN9374_CHIP_ID: + phy_addr_map =3D lan9374_phy_addr; + size =3D ARRAY_SIZE(lan9374_phy_addr); + break; + default: + return -EINVAL; + } + + if (size < dev->info->port_cnt) + return -EINVAL; + + for (i =3D 0; i < dev->info->port_cnt; i++) { + if (phy_addr_map[i] =3D=3D U8_MAX) + dev->phy_addr_map[i] =3D phy_addr_map[i]; + else + dev->phy_addr_map[i] =3D phy_addr_map[i] + offset; + } + + return 0; +} + +int lan937x_mdio_bus_preinit(struct ksz_device *dev, bool side_mdio) { u16 data16; int ret; =20 - /* Enable Phy access through SPI */ + /* Unlock access to the PHYs, needed for SPI and side MDIO access */ ret =3D lan937x_cfg(dev, REG_GLOBAL_CTRL_0, SW_PHY_REG_BLOCK, false); if (ret < 0) - return ret; + goto print_error; =20 - ret =3D ksz_read16(dev, REG_VPHY_SPECIAL_CTRL__2, &data16); - if (ret < 0) - return ret; + if (side_mdio) + /* Allow access to internal PHYs over MDIO bus */ + data16 =3D VPHY_MDIO_INTERNAL_ENABLE; + else + /* Enable SPI indirect access to address clock domain crossing + * issue + */ + data16 =3D VPHY_SPI_INDIRECT_ENABLE; + + ret =3D ksz_rmw16(dev, REG_VPHY_SPECIAL_CTRL__2, + VPHY_SPI_INDIRECT_ENABLE | VPHY_MDIO_INTERNAL_ENABLE, + data16); =20 - /* Allow SPI access */ - data16 |=3D VPHY_SPI_INDIRECT_ENABLE; +print_error: + if (ret < 0) + dev_err(dev->dev, "failed to enable spi indirect access"); =20 - return ksz_write16(dev, REG_VPHY_SPECIAL_CTRL__2, data16); + return ret; } =20 static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int = reg) @@ -363,13 +477,6 @@ int lan937x_setup(struct dsa_switch *ds) struct ksz_device *dev =3D ds->priv; int ret; =20 - /* enable Indirect Access from SPI to the VPHY registers */ - ret =3D lan937x_enable_spi_indirect_access(dev); - if (ret < 0) { - dev_err(dev->dev, "failed to enable spi indirect access"); - return ret; - } - /* The VLAN aware is a global setting. Mixed vlan * filterings are not supported. */ diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/micr= ochip/lan937x_reg.h index 2f22a9d01de36..4ec93e421da45 100644 --- a/drivers/net/dsa/microchip/lan937x_reg.h +++ b/drivers/net/dsa/microchip/lan937x_reg.h @@ -37,6 +37,10 @@ #define SW_CLK125_ENB BIT(1) #define SW_CLK25_ENB BIT(0) =20 +#define REG_SW_CFG_STRAP_VAL 0x0200 +#define SW_CASCADE_ID_CFG BIT(15) +#define SW_VPHY_ADD_CFG BIT(0) + /* 2 - PHY Control */ #define REG_SW_CFG_STRAP_OVR 0x0214 #define SW_VPHY_DISABLE BIT(31) --=20 2.39.5