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[2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53b2e10a47asm534934e87.1.2024.10.26.08.43.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Oct 2024 08:43:41 -0700 (PDT) From: Dmitry Baryshkov Date: Sat, 26 Oct 2024 18:43:33 +0300 Subject: [PATCH v3 3/3] soc: qcom: llcc: add support for SAR2130P and SAR1130P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241026-sar2130p-llcc-v3-3-2a58fa1b4d12@linaro.org> References: <20241026-sar2130p-llcc-v3-0-2a58fa1b4d12@linaro.org> In-Reply-To: <20241026-sar2130p-llcc-v3-0-2a58fa1b4d12@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Conor Dooley , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=13833; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=6j1ZmmWE0y4ED+Jm+F82mZmRwPap4+5uKPBK9BjftWM=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnHQ4oP8z/Nxs7vzQVbc9kvP0mIk7EG6XhsH3b0 hsyKIj+qeSJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZx0OKAAKCRAU23LtvoBl uCYPD/9puMk74o0KHpdX1w6RVULvVbXbqDJmQYekBzp6NAaKwBx4rI6ZWsZCzclGCJk3x00KL9/ 0AF/NFqaJaJzwb4/7oJd+iZ0b+KQ9Igti0U4CB9QR0IJnz0Z/THoKrzjmTHX02W1izVqDbYJFI1 6ABmi4XeS6t3QCdmlX+WIvXnfYfr4dOUCV6mvQLUAm0hH+D1DbDw1wWK/nmXr+5S4o9NuE/1ve6 uJSAzFJv467YuDD6Kw8ZplAH+7woR6yIxBUHQS0NV7NSahhH4r2O/wmYrIfd2qCYelDDOblMLZu JRZayZ7jylrhmthDR6hbhATJN4C/u5NKFTLE8WpdAZ8L4fSLkbgEYVwtCEHMiOsWZ2QibrWdpB3 0GSLljZ9EwMzAMEA+0EAB8NPcNexONEbfBS+ZTSJKjtrveWzNXozhHIrfcE7ggZVssDNUTrTX/s ttnoBXanZFv5tyzUJbaK3CLtxjqEXgCLwDE8E3OtzMXlE/sAOTWrj9VEKHX+m48PD+WtBpgtPxK 93iCh8be3guO0wgVPux2dcm0hwaFngyGRvtVgh+BZGzx1g1RTR0rOwzDhmpZ6rt8M/AET/DRx1w 1Ha+JLKVFnvnn+320qJHDgkZ2sOebZLgigHCmQ4+MxuID32sqyQ+YSGrm1la94XQ6nYoNYY0vRg yi2cNBb/gDH+4qw== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Implement necessary support for the LLCC control on the SAR1130P and SAR2130P platforms. These two platforms use different ATTR1_MAX_CAP shift and also require manual override for num_banks. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/soc/qcom/llcc-qcom.c | 460 +++++++++++++++++++++++++++++++++= +++- include/linux/soc/qcom/llcc-qcom.h | 12 + 2 files changed, 466 insertions(+), 6 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 891efd008b8e3d8b851ccf19d91e508b7a7bff40..783545b22aaab1b6037abd14727= f9a835aa0b4cc 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -136,6 +136,8 @@ struct qcom_llcc_config { const struct llcc_slice_config *sct_data; const u32 *reg_offset; const struct llcc_edac_reg_offset *edac_reg_offset; + u32 max_cap_shift; /* instead of ATTR1_MAX_CAP_SHIFT */ + u32 num_banks; int size; bool need_llcc_cfg; bool no_edac; @@ -298,6 +300,408 @@ static const struct llcc_slice_config sa8775p_data[] = =3D { }, }; =20 +static const struct llcc_slice_config sar1130p_data[] =3D { + { + .usecase_id =3D LLCC_CPUSS, + .slice_id =3D 1, + .max_cap =3D 4096, + .priority =3D 1, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + .activate_on_init =3D true, + }, { + .usecase_id =3D LLCC_VIDSC0, + .slice_id =3D 2, + .max_cap =3D 512, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_AUDIO, + .slice_id =3D 6, + .max_cap =3D 1024, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_CMPT, + .slice_id =3D 10, + .max_cap =3D 1024, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_GPUHTW, + .slice_id =3D 11, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_GPU, + .slice_id =3D 12, + .max_cap =3D 3072, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + .write_scid_en =3D true, + }, { + .usecase_id =3D LLCC_MMUHWT, + .slice_id =3D 13, + .max_cap =3D 512, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + }, { + .usecase_id =3D LLCC_DISP, + .slice_id =3D 16, + .max_cap =3D 12800, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_CVP, + .slice_id =3D 28, + .max_cap =3D 256, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_APTCM, + .slice_id =3D 26, + .max_cap =3D 2048, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x3, + .cache_mode =3D true, + .dis_cap_alloc =3D true, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_WRCACHE, + .slice_id =3D 31, + .max_cap =3D 256, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .activate_on_init =3D true, + }, { + .usecase_id =3D LLCC_AENPU, + .slice_id =3D 30, + .max_cap =3D 3072, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_DISP_LEFT, + .slice_id =3D 17, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_DISP_RIGHT, + .slice_id =3D 18, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_EVCS_LEFT, + .slice_id =3D 22, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_EVCS_RIGHT, + .slice_id =3D 23, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, +}; + +static const struct llcc_slice_config sar2130p_data[] =3D { + { + .usecase_id =3D LLCC_CPUSS, + .slice_id =3D 1, + .max_cap =3D 6144, + .priority =3D 1, + .fixed_size =3D 0, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + .activate_on_init =3D true, + }, { + .usecase_id =3D LLCC_VIDSC0, + .slice_id =3D 2, + .max_cap =3D 128, + .priority =3D 2, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_AUDIO, + .slice_id =3D 6, + .max_cap =3D 1024, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_CMPT, + .slice_id =3D 10, + .max_cap =3D 1024, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_GPUHTW, + .slice_id =3D 11, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_GPU, + .slice_id =3D 12, + .max_cap =3D 1536, + .priority =3D 2, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + .write_scid_en =3D true, + }, { + .usecase_id =3D LLCC_MMUHWT, + .slice_id =3D 13, + .max_cap =3D 1024, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .activate_on_init =3D true, + }, { + .usecase_id =3D LLCC_DISP, + .slice_id =3D 16, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_APTCM, + .slice_id =3D 26, + .max_cap =3D 2048, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x3, + .cache_mode =3D true, + .dis_cap_alloc =3D true, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_WRCACHE, + .slice_id =3D 31, + .max_cap =3D 256, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .activate_on_init =3D true, + }, { + .usecase_id =3D LLCC_VIEYE, + .slice_id =3D 7, + .max_cap =3D 7168, + .priority =3D 4, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_VIDPTH, + .slice_id =3D 8, + .max_cap =3D 7168, + .priority =3D 4, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_GPUMV, + .slice_id =3D 9, + .max_cap =3D 2048, + .priority =3D 2, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_EVA_LEFT, + .slice_id =3D 20, + .max_cap =3D 7168, + .priority =3D 5, + .fixed_size =3D true, + .bonus_ways =3D 0x3ffffffc, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_EVA_RIGHT, + .slice_id =3D 21, + .max_cap =3D 7168, + .priority =3D 5, + .fixed_size =3D true, + .bonus_ways =3D 0x3ffffffc, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_EVAGAIN, + .slice_id =3D 25, + .max_cap =3D 1024, + .priority =3D 2, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_AENPU, + .slice_id =3D 30, + .max_cap =3D 3072, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_VIPTH, + .slice_id =3D 29, + .max_cap =3D 1024, + .priority =3D 4, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_DISP_LEFT, + .slice_id =3D 17, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_DISP_RIGHT, + .slice_id =3D 18, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_EVCS_LEFT, + .slice_id =3D 22, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_EVCS_RIGHT, + .slice_id =3D 23, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_SPAD, + .slice_id =3D 24, + .max_cap =3D 7168, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, +}; + static const struct llcc_slice_config sc7180_data[] =3D { { .usecase_id =3D LLCC_CPUSS, @@ -2687,6 +3091,30 @@ static const struct qcom_llcc_config sa8775p_cfg[] = =3D { }, }; =20 +static const struct qcom_llcc_config sar1130p_cfg[] =3D { + { + .sct_data =3D sar1130p_data, + .size =3D ARRAY_SIZE(sar1130p_data), + .need_llcc_cfg =3D true, + .reg_offset =3D llcc_v2_1_reg_offset, + .edac_reg_offset =3D &llcc_v2_1_edac_reg_offset, + .max_cap_shift =3D 14, + .num_banks =3D 2, + }, +}; + +static const struct qcom_llcc_config sar2130p_cfg[] =3D { + { + .sct_data =3D sar2130p_data, + .size =3D ARRAY_SIZE(sar2130p_data), + .need_llcc_cfg =3D true, + .reg_offset =3D llcc_v2_1_reg_offset, + .edac_reg_offset =3D &llcc_v2_1_edac_reg_offset, + .max_cap_shift =3D 14, + .num_banks =3D 2, + }, +}; + static const struct qcom_llcc_config sc7180_cfg[] =3D { { .sct_data =3D sc7180_data, @@ -2839,6 +3267,16 @@ static const struct qcom_sct_config sa8775p_cfgs =3D= { .num_config =3D ARRAY_SIZE(sa8775p_cfg), }; =20 +static const struct qcom_sct_config sar1130p_cfgs =3D { + .llcc_config =3D sar1130p_cfg, + .num_config =3D ARRAY_SIZE(sar1130p_cfg), +}; + +static const struct qcom_sct_config sar2130p_cfgs =3D { + .llcc_config =3D sar2130p_cfg, + .num_config =3D ARRAY_SIZE(sar2130p_cfg), +}; + static const struct qcom_sct_config sc7180_cfgs =3D { .llcc_config =3D sc7180_cfg, .num_config =3D ARRAY_SIZE(sc7180_cfg), @@ -3146,7 +3584,10 @@ static int _qcom_llcc_cfg_program(const struct llcc_= slice_config *config, */ max_cap_cacheline =3D max_cap_cacheline / drv_data->num_banks; max_cap_cacheline >>=3D CACHE_LINE_SIZE_SHIFT; - attr1_val |=3D max_cap_cacheline << ATTR1_MAX_CAP_SHIFT; + if (cfg->max_cap_shift) + attr1_val |=3D max_cap_cacheline << cfg->max_cap_shift; + else + attr1_val |=3D max_cap_cacheline << ATTR1_MAX_CAP_SHIFT; =20 attr1_cfg =3D LLCC_TRP_ATTR1_CFGn(config->slice_id); =20 @@ -3383,12 +3824,17 @@ static int qcom_llcc_probe(struct platform_device *= pdev) goto err; cfg =3D &cfgs->llcc_config[cfg_index]; =20 - ret =3D regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_ba= nks); - if (ret) - goto err; + if (cfg->num_banks) { + num_banks =3D cfg->num_banks; + } else { + ret =3D regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_b= anks); + if (ret) + goto err; + + num_banks &=3D LLCC_LB_CNT_MASK; + num_banks >>=3D LLCC_LB_CNT_SHIFT; + } =20 - num_banks &=3D LLCC_LB_CNT_MASK; - num_banks >>=3D LLCC_LB_CNT_SHIFT; drv_data->num_banks =3D num_banks; =20 drv_data->regmaps =3D devm_kcalloc(dev, num_banks, sizeof(*drv_data->regm= aps), GFP_KERNEL); @@ -3486,6 +3932,8 @@ static int qcom_llcc_probe(struct platform_device *pd= ev) static const struct of_device_id qcom_llcc_of_match[] =3D { { .compatible =3D "qcom,qdu1000-llcc", .data =3D &qdu1000_cfgs}, { .compatible =3D "qcom,sa8775p-llcc", .data =3D &sa8775p_cfgs }, + { .compatible =3D "qcom,sar1130p-llcc", .data =3D &sar1130p_cfgs }, + { .compatible =3D "qcom,sar2130p-llcc", .data =3D &sar2130p_cfgs }, { .compatible =3D "qcom,sc7180-llcc", .data =3D &sc7180_cfgs }, { .compatible =3D "qcom,sc7280-llcc", .data =3D &sc7280_cfgs }, { .compatible =3D "qcom,sc8180x-llcc", .data =3D &sc8180x_cfgs }, diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/ll= cc-qcom.h index 2f20281d4ad4352ef59e7b19148cd324c7991012..8e5d78fb4847a232ab17a66c277= 5552dcb287752 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -54,7 +54,19 @@ #define LLCC_CAMEXP4 52 #define LLCC_DISP_WB 53 #define LLCC_DISP_1 54 +#define LLCC_VIEYE 57 +#define LLCC_VIDPTH 58 +#define LLCC_GPUMV 59 +#define LLCC_EVA_LEFT 60 +#define LLCC_EVA_RIGHT 61 +#define LLCC_EVAGAIN 62 +#define LLCC_VIPTH 63 #define LLCC_VIDVSP 64 +#define LLCC_DISP_LEFT 65 +#define LLCC_DISP_RIGHT 66 +#define LLCC_EVCS_LEFT 67 +#define LLCC_EVCS_RIGHT 68 +#define LLCC_SPAD 69 =20 /** * struct llcc_slice_desc - Cache slice descriptor --=20 2.39.5