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Fri, 25 Oct 2024 21:51:05 +0000 From: =?UTF-8?q?Micha=C5=82=20Winiarski?= To: , , , , "Bjorn Helgaas" , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= CC: Rodrigo Vivi , Michal Wajdeczko , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Matt Roper , =?UTF-8?q?Micha=C5=82=20Winiarski?= Subject: [PATCH v4 1/7] PCI/IOV: Restore VF resizable BAR state after reset Date: Fri, 25 Oct 2024 23:50:32 +0200 Message-ID: <20241025215038.3125626-2-michal.winiarski@intel.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241025215038.3125626-1-michal.winiarski@intel.com> References: <20241025215038.3125626-1-michal.winiarski@intel.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: WA0P291CA0012.POLP291.PROD.OUTLOOK.COM (2603:10a6:1d0:1::7) To DM4PR11MB5373.namprd11.prod.outlook.com (2603:10b6:5:394::7) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM4PR11MB5373:EE_|DS0PR11MB7682:EE_ X-MS-Office365-Filtering-Correlation-Id: 87a0a3e0-998c-449f-8c04-08dcf53f200c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016; 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Add the capability ID and restore it as a part of IOV state. See PCIe r4.0, sec 9.3.7.4. Signed-off-by: Micha=C5=82 Winiarski Reviewed-by: Ilpo J=C3=A4rvinen Reviewed-by: Christian K=C3=B6nig --- drivers/pci/iov.c | 29 ++++++++++++++++++++++++++++- include/uapi/linux/pci_regs.h | 1 + 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index aaa33e8dc4c97..6bdc9950b9787 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -7,6 +7,7 @@ * Copyright (C) 2009 Intel Corporation, Yu Zhao */ =20 +#include #include #include #include @@ -862,6 +863,30 @@ static void sriov_release(struct pci_dev *dev) dev->sriov =3D NULL; } =20 +static void sriov_restore_vf_rebar_state(struct pci_dev *dev) +{ + unsigned int pos, nbars, i; + u32 ctrl; + + pos =3D pci_find_ext_capability(dev, PCI_EXT_CAP_ID_VF_REBAR); + if (!pos) + return; + + pci_read_config_dword(dev, pos + PCI_REBAR_CTRL, &ctrl); + nbars =3D FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl); + + for (i =3D 0; i < nbars; i++, pos +=3D 8) { + int bar_idx, size; + + pci_read_config_dword(dev, pos + PCI_REBAR_CTRL, &ctrl); + bar_idx =3D FIELD_GET(PCI_REBAR_CTRL_BAR_IDX, ctrl); + size =3D pci_rebar_bytes_to_size(dev->sriov->barsz[bar_idx]); + ctrl &=3D ~PCI_REBAR_CTRL_BAR_SIZE; + ctrl |=3D FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size); + pci_write_config_dword(dev, pos + PCI_REBAR_CTRL, ctrl); + } +} + static void sriov_restore_state(struct pci_dev *dev) { int i; @@ -1021,8 +1046,10 @@ resource_size_t pci_sriov_resource_alignment(struct = pci_dev *dev, int resno) */ void pci_restore_iov_state(struct pci_dev *dev) { - if (dev->is_physfn) + if (dev->is_physfn) { + sriov_restore_vf_rebar_state(dev); sriov_restore_state(dev); + } } =20 /** diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 12323b3334a9c..a0cf701c4c3af 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -740,6 +740,7 @@ #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ +#define PCI_EXT_CAP_ID_VF_REBAR 0x24 /* VF Resizable BAR */ #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ --=20 2.47.0 From nobody Mon Nov 25 14:25:11 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89C6E217F52; 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Fri, 25 Oct 2024 21:51:09 +0000 From: =?UTF-8?q?Micha=C5=82=20Winiarski?= To: , , , , "Bjorn Helgaas" , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= CC: Rodrigo Vivi , Michal Wajdeczko , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Matt Roper , =?UTF-8?q?Micha=C5=82=20Winiarski?= Subject: [PATCH v4 2/7] PCI: Add a helper to identify IOV resources Date: Fri, 25 Oct 2024 23:50:33 +0200 Message-ID: <20241025215038.3125626-3-michal.winiarski@intel.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241025215038.3125626-1-michal.winiarski@intel.com> References: <20241025215038.3125626-1-michal.winiarski@intel.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MI1P293CA0017.ITAP293.PROD.OUTLOOK.COM (2603:10a6:290:3::13) To DM4PR11MB5373.namprd11.prod.outlook.com (2603:10b6:5:394::7) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM4PR11MB5373:EE_|DS0PR11MB7682:EE_ X-MS-Office365-Filtering-Correlation-Id: 78d1cde8-6918-44f5-4c6f-08dcf53f2279 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016; 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Extract it to pci_resource_is_iov() helper and drop a few ifdefs. Signed-off-by: Micha=C5=82 Winiarski Reviewed-by: Ilpo J=C3=A4rvinen Reviewed-by: Christian K=C3=B6nig --- drivers/pci/pci.h | 19 +++++++++++++++---- drivers/pci/setup-bus.c | 7 +++---- drivers/pci/setup-res.c | 4 +--- 3 files changed, 19 insertions(+), 11 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 14d00ce45bfa9..48d345607e57e 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -580,6 +580,10 @@ void pci_iov_update_resource(struct pci_dev *dev, int = resno); resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resn= o); void pci_restore_iov_state(struct pci_dev *dev); int pci_iov_bus_range(struct pci_bus *bus); +static inline bool pci_resource_is_iov(int resno) +{ + return resno >=3D PCI_IOV_RESOURCES && resno <=3D PCI_IOV_RESOURCE_END; +} extern const struct attribute_group sriov_pf_dev_attr_group; extern const struct attribute_group sriov_vf_dev_attr_group; #else @@ -589,12 +593,21 @@ static inline int pci_iov_init(struct pci_dev *dev) } static inline void pci_iov_release(struct pci_dev *dev) { } static inline void pci_iov_remove(struct pci_dev *dev) { } +static inline void pci_iov_update_resource(struct pci_dev *dev, int resno)= { } +static inline resource_size_t pci_sriov_resource_alignment(struct pci_dev = *dev, + int resno) +{ + return 0; +} static inline void pci_restore_iov_state(struct pci_dev *dev) { } static inline int pci_iov_bus_range(struct pci_bus *bus) { return 0; } - +static inline bool pci_resource_is_iov(int resno) +{ + return false; +} #endif /* CONFIG_PCI_IOV */ =20 #ifdef CONFIG_PCIE_PTM @@ -616,12 +629,10 @@ unsigned long pci_cardbus_resource_alignment(struct r= esource *); static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, struct resource *res) { -#ifdef CONFIG_PCI_IOV int resno =3D res - dev->resource; =20 - if (resno >=3D PCI_IOV_RESOURCES && resno <=3D PCI_IOV_RESOURCE_END) + if (pci_resource_is_iov(resno)) return pci_sriov_resource_alignment(dev, resno); -#endif if (dev->class >> 8 =3D=3D PCI_CLASS_BRIDGE_CARDBUS) return pci_cardbus_resource_alignment(res); return resource_alignment(res); diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 23082bc0ca37a..ba293df10c050 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1093,17 +1093,16 @@ static int pbus_size_mem(struct pci_bus *bus, unsig= ned long mask, (r->flags & mask) !=3D type3)) continue; r_size =3D resource_size(r); -#ifdef CONFIG_PCI_IOV + /* Put SRIOV requested res to the optional list */ - if (realloc_head && i >=3D PCI_IOV_RESOURCES && - i <=3D PCI_IOV_RESOURCE_END) { + if (realloc_head && pci_resource_is_iov(i)) { add_align =3D max(pci_resource_alignment(dev, r), add_align); r->end =3D r->start - 1; add_to_list(realloc_head, dev, r, r_size, 0 /* Don't care */); children_add_size +=3D r_size; continue; } -#endif + /* * aligns[0] is for 1MB (since bridge memory * windows are always at least 1MB aligned), so diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index c6d933ddfd464..e2cf79253ebda 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -127,10 +127,8 @@ void pci_update_resource(struct pci_dev *dev, int resn= o) { if (resno <=3D PCI_ROM_RESOURCE) pci_std_update_resource(dev, resno); -#ifdef CONFIG_PCI_IOV - else if (resno >=3D PCI_IOV_RESOURCES && resno <=3D PCI_IOV_RESOURCE_END) + else if (pci_resource_is_iov(resno)) pci_iov_update_resource(dev, resno); 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Fri, 25 Oct 2024 21:51:13 +0000 Received: from DM4PR11MB5373.namprd11.prod.outlook.com ([fe80::927a:9c08:26f7:5b39]) by DM4PR11MB5373.namprd11.prod.outlook.com ([fe80::927a:9c08:26f7:5b39%5]) with mapi id 15.20.8093.018; Fri, 25 Oct 2024 21:51:13 +0000 From: =?UTF-8?q?Micha=C5=82=20Winiarski?= To: , , , , "Bjorn Helgaas" , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= CC: Rodrigo Vivi , Michal Wajdeczko , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Matt Roper , =?UTF-8?q?Micha=C5=82=20Winiarski?= Subject: [PATCH v4 3/7] PCI: Add a helper to convert between standard and IOV resources Date: Fri, 25 Oct 2024 23:50:34 +0200 Message-ID: <20241025215038.3125626-4-michal.winiarski@intel.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241025215038.3125626-1-michal.winiarski@intel.com> References: <20241025215038.3125626-1-michal.winiarski@intel.com> Content-Type: text/plain; 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Extract the logic to pci_resource_to_iov() and pci_resource_from_iov() helpers. Suggested-by: Ilpo J=C3=A4rvinen Signed-off-by: Micha=C5=82 Winiarski --- drivers/pci/iov.c | 20 ++++++++++---------- drivers/pci/pci.h | 18 ++++++++++++++++++ drivers/pci/setup-bus.c | 2 +- 3 files changed, 29 insertions(+), 11 deletions(-) diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 6bdc9950b9787..eedc1df56c49e 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -151,7 +151,7 @@ resource_size_t pci_iov_resource_size(struct pci_dev *d= ev, int resno) if (!dev->is_physfn) return 0; =20 - return dev->sriov->barsz[resno - PCI_IOV_RESOURCES]; + return dev->sriov->barsz[pci_resource_from_iov(resno)]; } =20 static void pci_read_vf_config_common(struct pci_dev *virtfn) @@ -322,12 +322,12 @@ int pci_iov_add_virtfn(struct pci_dev *dev, int id) virtfn->multifunction =3D 0; =20 for (i =3D 0; i < PCI_SRIOV_NUM_BARS; i++) { - res =3D &dev->resource[i + PCI_IOV_RESOURCES]; + res =3D &dev->resource[pci_resource_to_iov(i)]; if (!res->parent) continue; virtfn->resource[i].name =3D pci_name(virtfn); virtfn->resource[i].flags =3D res->flags; - size =3D pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); + size =3D pci_iov_resource_size(dev, pci_resource_to_iov(i)); virtfn->resource[i].start =3D res->start + size * id; virtfn->resource[i].end =3D virtfn->resource[i].start + size - 1; rc =3D request_resource(res, &virtfn->resource[i]); @@ -624,8 +624,8 @@ static int sriov_enable(struct pci_dev *dev, int nr_vir= tfn) =20 nres =3D 0; for (i =3D 0; i < PCI_SRIOV_NUM_BARS; i++) { - bars |=3D (1 << (i + PCI_IOV_RESOURCES)); - res =3D &dev->resource[i + PCI_IOV_RESOURCES]; + bars |=3D (1 << pci_resource_to_iov(i)); + res =3D &dev->resource[pci_resource_to_iov(i)]; if (res->parent) nres++; } @@ -786,8 +786,8 @@ static int sriov_init(struct pci_dev *dev, int pos) =20 nres =3D 0; for (i =3D 0; i < PCI_SRIOV_NUM_BARS; i++) { - res =3D &dev->resource[i + PCI_IOV_RESOURCES]; - res_name =3D pci_resource_name(dev, i + PCI_IOV_RESOURCES); + res =3D &dev->resource[pci_resource_to_iov(i)]; + res_name =3D pci_resource_name(dev, pci_resource_to_iov(i)); =20 /* * If it is already FIXED, don't change it, something @@ -844,7 +844,7 @@ static int sriov_init(struct pci_dev *dev, int pos) dev->is_physfn =3D 0; failed: for (i =3D 0; i < PCI_SRIOV_NUM_BARS; i++) { - res =3D &dev->resource[i + PCI_IOV_RESOURCES]; + res =3D &dev->resource[pci_resource_to_iov(i)]; res->flags =3D 0; } =20 @@ -906,7 +906,7 @@ static void sriov_restore_state(struct pci_dev *dev) pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, ctrl); =20 for (i =3D 0; i < PCI_SRIOV_NUM_BARS; i++) - pci_update_resource(dev, i + PCI_IOV_RESOURCES); + pci_update_resource(dev, pci_resource_to_iov(i)); =20 pci_write_config_dword(dev, iov->pos + PCI_SRIOV_SYS_PGSIZE, iov->pgsz); pci_iov_set_numvfs(dev, iov->num_VFs); @@ -972,7 +972,7 @@ void pci_iov_update_resource(struct pci_dev *dev, int r= esno) { struct pci_sriov *iov =3D dev->is_physfn ? dev->sriov : NULL; struct resource *res =3D dev->resource + resno; - int vf_bar =3D resno - PCI_IOV_RESOURCES; + int vf_bar =3D pci_resource_from_iov(resno); struct pci_bus_region region; u16 cmd; u32 new; diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 48d345607e57e..1f8d88f0243b7 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -584,6 +584,15 @@ static inline bool pci_resource_is_iov(int resno) { return resno >=3D PCI_IOV_RESOURCES && resno <=3D PCI_IOV_RESOURCE_END; } +static inline int pci_resource_to_iov(int resno) +{ + return resno + PCI_IOV_RESOURCES; +} + +static inline int pci_resource_from_iov(int resno) +{ + return resno - PCI_IOV_RESOURCES; +} extern const struct attribute_group sriov_pf_dev_attr_group; extern const struct attribute_group sriov_vf_dev_attr_group; #else @@ -608,6 +617,15 @@ static inline bool pci_resource_is_iov(int resno) { return false; } +static inline int pci_resource_to_iov(int resno) +{ + return -ENODEV; +} + +static inline int pci_resource_from_iov(int resno) +{ + return -ENODEV; +} #endif /* CONFIG_PCI_IOV */ =20 #ifdef CONFIG_PCIE_PTM diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index ba293df10c050..c5ad7c4ad6eb1 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1778,7 +1778,7 @@ static int iov_resources_unassigned(struct pci_dev *d= ev, void *data) bool *unassigned =3D data; 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The structures are very similar, which means we can reuse most of the implementation. Extend the pci_resize_resource() function to accept IOV resources. See PCIe r4.0, sec 9.3.7.4. Signed-off-by: Micha=C5=82 Winiarski --- drivers/pci/iov.c | 21 +++++++++++++++++++++ drivers/pci/pci.c | 10 +++++++++- drivers/pci/pci.h | 10 +++++++++- drivers/pci/setup-res.c | 36 +++++++++++++++++++++++++++++++----- 4 files changed, 70 insertions(+), 7 deletions(-) diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index eedc1df56c49e..79143c1bc7bb4 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -154,6 +154,27 @@ resource_size_t pci_iov_resource_size(struct pci_dev *= dev, int resno) return dev->sriov->barsz[pci_resource_from_iov(resno)]; } =20 +void pci_iov_resource_set_size(struct pci_dev *dev, int resno, + resource_size_t size) +{ + if (!pci_resource_is_iov(resno)) { + pci_warn(dev, "%s is not an IOV resource\n", + pci_resource_name(dev, resno)); + return; + } + + dev->sriov->barsz[pci_resource_from_iov(resno)] =3D size; +} + +bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev) +{ + u16 cmd; + + pci_read_config_word(dev, dev->sriov->pos + PCI_SRIOV_CTRL, &cmd); + + return cmd & PCI_SRIOV_CTRL_MSE; +} + static void pci_read_vf_config_common(struct pci_dev *virtfn) { struct pci_dev *physfn =3D virtfn->physfn; diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 7d85c04fbba2a..905a533807b32 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3720,8 +3720,16 @@ static int pci_rebar_find_pos(struct pci_dev *pdev, = int bar) { unsigned int pos, nbars, i; u32 ctrl; + int cap; =20 - pos =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); + if (pci_resource_is_iov(bar)) { + cap =3D PCI_EXT_CAP_ID_VF_REBAR; + bar =3D pci_resource_from_iov(bar); + } else { + cap =3D PCI_EXT_CAP_ID_REBAR; + } + + pos =3D pci_find_ext_capability(pdev, cap); if (!pos) return -ENOTSUPP; =20 diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 1f8d88f0243b7..4347858007145 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -580,6 +580,9 @@ void pci_iov_update_resource(struct pci_dev *dev, int r= esno); resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resn= o); void pci_restore_iov_state(struct pci_dev *dev); int pci_iov_bus_range(struct pci_bus *bus); +void pci_iov_resource_set_size(struct pci_dev *dev, int resno, + resource_size_t size); +bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev); static inline bool pci_resource_is_iov(int resno) { return resno >=3D PCI_IOV_RESOURCES && resno <=3D PCI_IOV_RESOURCE_END; @@ -613,6 +616,12 @@ static inline int pci_iov_bus_range(struct pci_bus *bu= s) { return 0; } +static inline void pci_iov_resource_set_size(struct pci_dev *dev, int resn= o, + resource_size_t size) { } +static inline bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev) +{ + return false; +} static inline bool pci_resource_is_iov(int resno) { return false; @@ -621,7 +630,6 @@ static inline int pci_resource_to_iov(int resno) { return -ENODEV; } - static inline int pci_resource_from_iov(int resno) { return -ENODEV; diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index e2cf79253ebda..cec8f684b7c70 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -425,13 +425,40 @@ void pci_release_resource(struct pci_dev *dev, int re= sno) } EXPORT_SYMBOL(pci_release_resource); =20 +static bool pci_resize_is_memory_decoding_enabled(struct pci_dev *dev, + int resno) +{ + u16 cmd; + + if (pci_resource_is_iov(resno)) + return pci_iov_is_memory_decoding_enabled(dev); + + pci_read_config_word(dev, PCI_COMMAND, &cmd); + + return cmd & PCI_COMMAND_MEMORY; +} + +static void pci_resize_resource_set_size(struct pci_dev *dev, int resno, + int size) +{ + resource_size_t res_size =3D pci_rebar_size_to_bytes(size); + struct resource *res =3D dev->resource + resno; + + if (!pci_resource_is_iov(resno)) { + res->end =3D res->start + res_size - 1; + } else { + res->end =3D res->start + + res_size * pci_sriov_get_totalvfs(dev) - 1; + pci_iov_resource_set_size(dev, resno, res_size); + } +} + int pci_resize_resource(struct pci_dev *dev, int resno, int size) { struct resource *res =3D dev->resource + resno; struct pci_host_bridge *host; int old, ret; u32 sizes; - u16 cmd; =20 /* Check if we must preserve the firmware's resource assignment */ host =3D pci_find_host_bridge(dev->bus); @@ -442,8 +469,7 @@ int pci_resize_resource(struct pci_dev *dev, int resno,= int size) if (!(res->flags & IORESOURCE_UNSET)) return -EBUSY; =20 - pci_read_config_word(dev, PCI_COMMAND, &cmd); - if (cmd & PCI_COMMAND_MEMORY) + if (pci_resize_is_memory_decoding_enabled(dev, resno)) return -EBUSY; =20 sizes =3D pci_rebar_get_possible_sizes(dev, resno); @@ -461,7 +487,7 @@ int pci_resize_resource(struct pci_dev *dev, int resno,= int size) if (ret) return ret; =20 - res->end =3D res->start + pci_rebar_size_to_bytes(size) - 1; + pci_resize_resource_set_size(dev, resno, size); =20 /* Check if the new config works by trying to assign everything. */ if (dev->bus->self) { @@ -473,7 +499,7 @@ int pci_resize_resource(struct pci_dev *dev, int resno,= int size) =20 error_resize: pci_rebar_set_size(dev, resno, old); - res->end =3D res->start + pci_rebar_size_to_bytes(old) - 1; + pci_resize_resource_set_size(dev, resno, old); return ret; } EXPORT_SYMBOL(pci_resize_resource); --=20 2.47.0 From nobody Mon Nov 25 14:25:11 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D230321440C; 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However, that assumption only holds in an environment where VF BAR size can't be modified. Add an additional check that verifies that VF BAR for all enabled VFs fits within the underlying reservation resource. Signed-off-by: Micha=C5=82 Winiarski --- drivers/pci/iov.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 79143c1bc7bb4..5de828e5a26ea 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -645,10 +645,14 @@ static int sriov_enable(struct pci_dev *dev, int nr_v= irtfn) =20 nres =3D 0; for (i =3D 0; i < PCI_SRIOV_NUM_BARS; i++) { + int vf_bar_sz =3D pci_iov_resource_size(dev, + pci_resource_to_iov(i)); bars |=3D (1 << pci_resource_to_iov(i)); res =3D &dev->resource[pci_resource_to_iov(i)]; - if (res->parent) - nres++; + if (!res->parent || vf_bar_sz * nr_virtfn > resource_size(res)) + continue; + + nres++; } if (nres !=3D iov->nres) { pci_err(dev, "not enough MMIO resources for SR-IOV\n"); --=20 2.47.0 From nobody Mon Nov 25 14:25:11 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E80A120F3C9; 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Fri, 25 Oct 2024 21:51:25 +0000 From: =?UTF-8?q?Micha=C5=82=20Winiarski?= To: , , , , "Bjorn Helgaas" , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= CC: Rodrigo Vivi , Michal Wajdeczko , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Matt Roper , =?UTF-8?q?Micha=C5=82=20Winiarski?= Subject: [PATCH v4 6/7] PCI: Allow drivers to control VF BAR size Date: Fri, 25 Oct 2024 23:50:37 +0200 Message-ID: <20241025215038.3125626-7-michal.winiarski@intel.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241025215038.3125626-1-michal.winiarski@intel.com> References: <20241025215038.3125626-1-michal.winiarski@intel.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: WA1P291CA0007.POLP291.PROD.OUTLOOK.COM (2603:10a6:1d0:19::11) To DM4PR11MB5373.namprd11.prod.outlook.com (2603:10b6:5:394::7) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM4PR11MB5373:EE_|CY8PR11MB7745:EE_ X-MS-Office365-Filtering-Correlation-Id: f46ff9bf-6247-4a52-050f-08dcf53f2c21 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|366016|1800799024|376014; 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Add a pci_iov_vf_bar_set_size() function to control the size and a pci_iov_vf_bar_get_sizes() helper to get the VF BAR sizes that will allow up to num_vfs to be successfully enabled with the current underlying reservation size. Signed-off-by: Micha=C5=82 Winiarski --- drivers/pci/iov.c | 80 +++++++++++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 6 ++++ 2 files changed, 86 insertions(+) diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 5de828e5a26ea..de8d473459440 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -1281,3 +1281,83 @@ int pci_sriov_configure_simple(struct pci_dev *dev, = int nr_virtfn) return nr_virtfn; } EXPORT_SYMBOL_GPL(pci_sriov_configure_simple); + +/** + * pci_iov_vf_bar_set_size - set a new size for a VF BAR + * @dev: the PCI device + * @resno: the resource number + * @size: new size as defined in the spec (0=3D1MB, 19=3D512GB) + * + * Set the new size of a VF BAR that supports VF resizable BAR capability. + * Unlike pci_resize_resource(), this does not cause the resource that + * reserves the MMIO space (originally up to total_VFs) to be resized, whi= ch + * means that following calls to pci_enable_sriov() can fail if the resour= ces + * no longer fit. + * + * Returns 0 on success, or negative on failure. + * + */ +int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size) +{ + int ret; + u32 sizes; + + if (!pci_resource_is_iov(resno)) + return -EINVAL; + + if (pci_iov_is_memory_decoding_enabled(dev)) + return -EBUSY; + + sizes =3D pci_rebar_get_possible_sizes(dev, resno); + if (!sizes) + return -ENOTSUPP; + + if (!(sizes & BIT(size))) + return -EINVAL; + + ret =3D pci_rebar_set_size(dev, resno, size); + if (ret) + return ret; + + pci_iov_resource_set_size(dev, resno, pci_rebar_size_to_bytes(size)); + + return 0; +} +EXPORT_SYMBOL_GPL(pci_iov_vf_bar_set_size); + +/** + * pci_iov_vf_bar_get_sizes - get VF BAR sizes that allow to create up to = num_vfs + * @dev: the PCI device + * @resno: the resource number + * @num_vfs: number of VFs + * + * Get the sizes of a VF resizable BAR that can fit up to num_vfs within t= he + * resource that reserves the MMIO space (originally up to total_VFs) the = as + * bitmask defined in the spec (bit 0=3D1MB, bit 19=3D512GB). + * + * Returns 0 if BAR isn't resizable. + * + */ +u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs) +{ + resource_size_t size; + u32 sizes; + int i; + + sizes =3D pci_rebar_get_possible_sizes(dev, resno); + if (!sizes) + return 0; + + while (sizes > 0) { + i =3D __fls(sizes); + size =3D pci_rebar_size_to_bytes(i); + + if (size * num_vfs <=3D pci_resource_len(dev, resno)) + break; + + sizes &=3D ~BIT(i); + } + + return sizes; +} +EXPORT_SYMBOL_GPL(pci_iov_vf_bar_get_sizes); diff --git a/include/linux/pci.h b/include/linux/pci.h index 573b4c4c2be61..1b9e7e3cab0ce 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -2371,6 +2371,8 @@ int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 n= umvfs); int pci_sriov_get_totalvfs(struct pci_dev *dev); int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); +int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size); +u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs); void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); =20 /* Arch may override these (weak) */ @@ -2423,6 +2425,10 @@ static inline int pci_sriov_get_totalvfs(struct pci_= dev *dev) #define pci_sriov_configure_simple NULL static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, i= nt resno) { return 0; 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This means that we can achieve full LMEM BAR access without the need to attempt full VF LMEM BAR resize via pci_resize_resource(). Always set the largest possible BAR size that allows to fit the number of enabled VFs. Signed-off-by: Micha=C5=82 Winiarski --- drivers/gpu/drm/xe/regs/xe_bars.h | 1 + drivers/gpu/drm/xe/xe_pci_sriov.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/xe/regs/xe_bars.h b/drivers/gpu/drm/xe/regs/xe= _bars.h index ce05b6ae832f1..880140d6ccdca 100644 --- a/drivers/gpu/drm/xe/regs/xe_bars.h +++ b/drivers/gpu/drm/xe/regs/xe_bars.h @@ -7,5 +7,6 @@ =20 #define GTTMMADR_BAR 0 /* MMIO + GTT */ #define LMEM_BAR 2 /* VRAM */ +#define VF_LMEM_BAR 9 /* VF VRAM */ =20 #endif diff --git a/drivers/gpu/drm/xe/xe_pci_sriov.c b/drivers/gpu/drm/xe/xe_pci_= sriov.c index aaceee748287e..57cdeb41ef1d9 100644 --- a/drivers/gpu/drm/xe/xe_pci_sriov.c +++ b/drivers/gpu/drm/xe/xe_pci_sriov.c @@ -3,6 +3,10 @@ * Copyright =C2=A9 2023-2024 Intel Corporation */ =20 +#include +#include + +#include "regs/xe_bars.h" #include "xe_assert.h" #include "xe_device.h" #include "xe_gt_sriov_pf_config.h" @@ -62,6 +66,18 @@ static void pf_reset_vfs(struct xe_device *xe, unsigned = int num_vfs) xe_gt_sriov_pf_control_trigger_flr(gt, n); } =20 +static int resize_vf_vram_bar(struct xe_device *xe, int num_vfs) +{ + struct pci_dev *pdev =3D to_pci_dev(xe->drm.dev); + u32 sizes; + + sizes =3D pci_iov_vf_bar_get_sizes(pdev, VF_LMEM_BAR, num_vfs); + if (!sizes) + return 0; + + return pci_iov_vf_bar_set_size(pdev, VF_LMEM_BAR, __fls(sizes)); +} + static int pf_enable_vfs(struct xe_device *xe, int num_vfs) { struct pci_dev *pdev =3D to_pci_dev(xe->drm.dev); @@ -88,6 +104,12 @@ static int pf_enable_vfs(struct xe_device *xe, int num_= vfs) if (err < 0) goto failed; =20 + if (IS_DGFX(xe)) { + err =3D resize_vf_vram_bar(xe, num_vfs); + if (err) + xe_sriov_info(xe, "Failed to set VF LMEM BAR size: %d\n", err); + } + err =3D pci_enable_sriov(pdev, num_vfs); if (err < 0) goto failed; --=20 2.47.0