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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000044F7.mail.protection.outlook.com (10.167.241.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8137.0 via Frontend Transport; Fri, 25 Oct 2024 21:05:45 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 25 Oct 2024 16:05:44 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 14/14] cxl/pci: Add support to assign and clear pci_driver::cxl_err_handlers Date: Fri, 25 Oct 2024 16:03:05 -0500 Message-ID: <20241025210305.27499-15-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025210305.27499-1-terry.bowman@amd.com> References: <20241025210305.27499-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F7:EE_|CH2PR12MB4327:EE_ X-MS-Office365-Filtering-Correlation-Id: 6a0fa4dc-03c6-4606-2fce-08dcf538cb79 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|36860700013|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 21:05:45.8583 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6a0fa4dc-03c6-4606-2fce-08dcf538cb79 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F7.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4327 Content-Type: text/plain; charset="utf-8" pci_driver::cxl_err_handlers are not currrently assigned handler callbacks. The handlers can't be set in the pci_driver static definition because the CXL PCIe port devices are bound to the portdrv driver which is not CXL driver aware. Add cxl_assign_port_error_handlers() in the cxl_core module. This function will assign the default handlers for a CXL PCIe port device. When the CXL port (cxl_port or cxl_dport) is destroyed the CXL PCIe port device's pci_driver::cxl_err_handlers must be set to NULL to prevent future use. Create cxl_clear_port_error_handlers() and register it to be called when the CXL port device (cxl_port or cxl_dport) is destroyed. Signed-off-by: Terry Bowman --- drivers/cxl/core/pci.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index eeb4a64ba5b5..5f7570c6173c 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -839,8 +839,36 @@ static bool cxl_port_error_detected(struct pci_dev *pd= ev) return ue; } =20 +static const struct cxl_error_handlers cxl_port_error_handlers =3D { + .error_detected =3D cxl_port_error_detected, + .cor_error_detected =3D cxl_port_cor_error_detected, +}; + +static void cxl_assign_port_error_handlers(struct pci_dev *pdev) +{ + struct pci_driver *pdrv =3D pdev->driver; + + if (!pdrv) + return; + + pdrv->cxl_err_handler =3D &cxl_port_error_handlers; +} + +static void cxl_clear_port_error_handlers(void *data) +{ + struct pci_dev *pdev =3D data; + struct pci_driver *pdrv =3D pdev->driver; + + if (!pdrv) + return; + + pdrv->cxl_err_handler =3D NULL; +} + void cxl_uport_init_ras_reporting(struct cxl_port *port) { + struct pci_dev *pdev =3D to_pci_dev(port->uport_dev); + /* uport may have more than 1 downstream EP. Check if already mapped. */ if (port->uport_regs.ras) { dev_warn(&port->dev, "RAS is already mapped\n"); @@ -853,6 +881,9 @@ void cxl_uport_init_ras_reporting(struct cxl_port *port) dev_err(&port->dev, "Failed to map RAS capability.\n"); return; } + + cxl_assign_port_error_handlers(pdev); + devm_add_action_or_reset(port->uport_dev, cxl_clear_port_error_handlers, = pdev); } EXPORT_SYMBOL_NS_GPL(cxl_uport_init_ras_reporting, CXL); =20 @@ -865,6 +896,7 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dpo= rt) { struct device *dport_dev =3D dport->dport_dev; struct pci_host_bridge *host_bridge =3D to_pci_host_bridge(dport_dev); + struct pci_dev *pdev =3D to_pci_dev(dport_dev); =20 if (dport->rch && host_bridge->native_aer) { cxl_dport_map_rch_aer(dport); @@ -883,6 +915,9 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dpo= rt) dev_err(dport_dev, "Failed to map RAS capability.\n"); return; } + + cxl_assign_port_error_handlers(pdev); + devm_add_action_or_reset(dport_dev, cxl_clear_port_error_handlers, pdev); } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, CXL); =20 --=20 2.34.1