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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 21:03:22.8113 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 205b2065-1b38-41f8-f38a-08dcf5387635 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F7.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7645 Content-Type: text/plain; charset="utf-8" CXL.io provides PCIe like protocol error implementation, but CXL.io and PCIe have different handling requirements. The PCIe AER service driver may attempt recovering PCIe devices with uncorrectable errors while recovery is not used for CXL.io. Recovery is not used in the CXL.io recovery because of the potential for corruption on what can be system memory. Create pci_driver::cxl_err_handlers similar to pci_driver::error_handler. Create handlers for correctable and uncorrectable CXL.io error handling. The CXL error handlers will be used in future patches adding CXL PCIe port protocol error handling. Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Fan Ni Reviewed-by: Jonathan Cameron --- include/linux/pci.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/linux/pci.h b/include/linux/pci.h index 573b4c4c2be6..106ac83e3a7b 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -886,6 +886,14 @@ struct pci_error_handlers { void (*cor_error_detected)(struct pci_dev *dev); }; =20 +/* CXL bus error event callbacks */ +struct cxl_error_handlers { + /* CXL bus error detected on this device */ + bool (*error_detected)(struct pci_dev *dev); + + /* Allow device driver to record more details of a correctable error */ + void (*cor_error_detected)(struct pci_dev *dev); +}; =20 struct module; =20 @@ -956,6 +964,7 @@ struct pci_driver { int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count);= /* On PF */ u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf); const struct pci_error_handlers *err_handler; + const struct cxl_error_handlers *cxl_err_handler; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 21:03:33.9873 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7b013aa2-16b4-4eed-e49b-08dcf5387cdc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FD.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7650 Content-Type: text/plain; charset="utf-8" The AER service driver already includes support for CXL restricted host (RCH) downstream port error handling. The current implementation is based on CXL1.1 using a root complex event collector. Rename function interfaces and parameters where necessary to include virtual hierarchy (VH) mode CXL PCIe port error handling alongside the RCH handling.[1] The CXL PCIe port error handling will be added in a future patch. Limit changes to renaming variable and function names. No functional changes are added. [1] CXL 3.1 Spec, 9.12.2 CXL Virtual Hierarchy Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Fan Ni Reviewed-by: Jonathan Cameron --- drivers/pci/pcie/aer.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 13b8586924ea..fe6edf26279e 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1029,7 +1029,7 @@ static int cxl_rch_handle_error_iter(struct pci_dev *= dev, void *data) return 0; } =20 -static void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info = *info) +static void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *inf= o) { /* * Internal errors of an RCEC indicate an AER error in an @@ -1052,30 +1052,30 @@ static int handles_cxl_error_iter(struct pci_dev *d= ev, void *data) return *handles_cxl; } =20 -static bool handles_cxl_errors(struct pci_dev *rcec) +static bool handles_cxl_errors(struct pci_dev *dev) { bool handles_cxl =3D false; =20 - if (pci_pcie_type(rcec) =3D=3D PCI_EXP_TYPE_RC_EC && - pcie_aer_is_native(rcec)) - pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl); + if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC && + pcie_aer_is_native(dev)) + pcie_walk_rcec(dev, handles_cxl_error_iter, &handles_cxl); =20 return handles_cxl; } =20 -static void cxl_rch_enable_rcec(struct pci_dev *rcec) +static void cxl_enable_internal_errors(struct pci_dev *dev) { - if (!handles_cxl_errors(rcec)) + if (!handles_cxl_errors(dev)) return; =20 - pci_aer_unmask_internal_errors(rcec); - pci_info(rcec, "CXL: Internal errors unmasked"); + pci_aer_unmask_internal_errors(dev); + pci_info(dev, "CXL: Internal errors unmasked"); } =20 #else -static inline void cxl_rch_enable_rcec(struct pci_dev *dev) { } -static inline void cxl_rch_handle_error(struct pci_dev *dev, - struct aer_err_info *info) { } +static inline void cxl_enable_internal_errors(struct pci_dev *dev) { } +static inline void cxl_handle_error(struct pci_dev *dev, + struct aer_err_info *info) { } #endif =20 /** @@ -1113,7 +1113,7 @@ static void pci_aer_handle_error(struct pci_dev *dev,= struct aer_err_info *info) =20 static void handle_error_source(struct pci_dev *dev, struct aer_err_info *= info) { - cxl_rch_handle_error(dev, info); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 21:03:44.8879 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 57500060-5194-4f1d-92be-08dcf538835e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FC.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9087 Content-Type: text/plain; charset="utf-8" CXL and AER drivers need the ability to identify CXL devices and CXL port devices. First, add set_pcie_cxl() with logic checking for CXL Flexbus DVSEC presence. The CXL Flexbus DVSEC presence is used because it is required for all the CXL PCIe devices.[1] Add boolean 'struct pci_dev::is_cxl' with the purpose to cache the CXL Flexbus presence. Add pcie_is_cxl() as a macro to return 'struct pci_dev::is_cxl', Add pcie_is_cxl_port() to check if a device is a CXL root port, CXL upstream switch port, or CXL downstream switch port. Also, verify the CXL extensions DVSEC for port is present.[1] [1] CXL 3.1 Spec, 8.1.1 PCIe Designated Vendor-Specific Extended Capability (DVSEC) ID Assignment, Table 8-2 Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Fan Ni Reviewed-by: Jonathan Cameron --- drivers/pci/pci.c | 14 ++++++++++++++ drivers/pci/probe.c | 10 ++++++++++ include/linux/pci.h | 4 ++++ include/uapi/linux/pci_regs.h | 3 ++- 4 files changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 7d85c04fbba2..c1b243aec61c 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5034,6 +5034,20 @@ static u16 cxl_port_dvsec(struct pci_dev *dev) PCI_DVSEC_CXL_PORT); } =20 +bool pcie_is_cxl_port(struct pci_dev *dev) +{ + if (!pcie_is_cxl(dev)) + return false; + + if ((pci_pcie_type(dev) !=3D PCI_EXP_TYPE_ROOT_PORT) && + (pci_pcie_type(dev) !=3D PCI_EXP_TYPE_UPSTREAM) && + (pci_pcie_type(dev) !=3D PCI_EXP_TYPE_DOWNSTREAM)) + return false; + + return cxl_port_dvsec(dev); +} +EXPORT_SYMBOL_GPL(pcie_is_cxl_port); + static bool cxl_sbr_masked(struct pci_dev *dev) { u16 dvsec, reg; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 4f68414c3086..9324eb345f11 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1631,6 +1631,14 @@ static void set_pcie_thunderbolt(struct pci_dev *dev) dev->is_thunderbolt =3D 1; } =20 +static void set_pcie_cxl(struct pci_dev *dev) +{ + u16 dvsec =3D pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL, + PCI_DVSEC_CXL_FLEXBUS); + if (dvsec) + dev->is_cxl =3D 1; +} + static void set_pcie_untrusted(struct pci_dev *dev) { struct pci_dev *parent; @@ -1945,6 +1953,8 @@ int pci_setup_device(struct pci_dev *dev) /* Need to have dev->cfg_size ready */ set_pcie_thunderbolt(dev); =20 + set_pcie_cxl(dev); + set_pcie_untrusted(dev); =20 /* "Unknown power state" */ diff --git a/include/linux/pci.h b/include/linux/pci.h index 106ac83e3a7b..d3b1af9fb273 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -443,6 +443,7 @@ struct pci_dev { unsigned int is_hotplug_bridge:1; unsigned int shpc_managed:1; /* SHPC owned by shpchp */ unsigned int is_thunderbolt:1; /* Thunderbolt controller */ + unsigned int is_cxl:1; /* CXL alternate protocol */ /* * Devices marked being untrusted are the ones that can potentially * execute DMA attacks and similar. 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Fri, 25 Oct 2024 16:03:54 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 04/14] PCI/AER: Modify AER driver logging to report CXL or PCIe bus error type Date: Fri, 25 Oct 2024 16:02:55 -0500 Message-ID: <20241025210305.27499-5-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025210305.27499-1-terry.bowman@amd.com> References: <20241025210305.27499-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FB:EE_|CYYPR12MB8656:EE_ X-MS-Office365-Filtering-Correlation-Id: 7d177634-f314-4e7c-0da0-08dcf53889f1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|1800799024|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 21:03:55.9299 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7d177634-f314-4e7c-0da0-08dcf53889f1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FB.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8656 Content-Type: text/plain; charset="utf-8" The AER driver and aer_event tracing currently log 'PCIe Bus Type' for all errors. Update the driver and aer_event tracing to log 'CXL Bus Type' for CXL devic= es. Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Fan Ni Reviewed-by: Jonathan Cameron --- drivers/pci/pcie/aer.c | 14 ++++++++------ include/ras/ras_event.h | 9 ++++++--- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index fe6edf26279e..53e9a11f6c0f 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -699,13 +699,14 @@ static void __aer_print_error(struct pci_dev *dev, =20 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) { + const char *bus_type =3D pcie_is_cxl(dev) ? "CXL" : "PCIe"; int layer, agent; int id =3D pci_dev_id(dev); const char *level; =20 if (!info->status) { - pci_err(dev, "PCIe Bus Error: severity=3D%s, type=3DInaccessible, (Unreg= istered Agent ID)\n", - aer_error_severity_string[info->severity]); + pci_err(dev, "%s Bus Error: severity=3D%s, type=3DInaccessible, (Unregis= tered Agent ID)\n", + bus_type, aer_error_severity_string[info->severity]); goto out; } =20 @@ -714,8 +715,8 @@ void aer_print_error(struct pci_dev *dev, struct aer_er= r_info *info) =20 level =3D (info->severity =3D=3D AER_CORRECTABLE) ? KERN_WARNING : KERN_E= RR; =20 - pci_printk(level, dev, "PCIe Bus Error: severity=3D%s, type=3D%s, (%s)\n", - aer_error_severity_string[info->severity], + pci_printk(level, dev, "%s Bus Error: severity=3D%s, type=3D%s, (%s)\n", + bus_type, aer_error_severity_string[info->severity], aer_error_layer[layer], aer_agent_string[agent]); =20 pci_printk(level, dev, " device [%04x:%04x] error status/mask=3D%08x/%08= x\n", @@ -730,7 +731,7 @@ void aer_print_error(struct pci_dev *dev, struct aer_er= r_info *info) if (info->id && info->error_dev_num > 1 && info->id =3D=3D id) pci_err(dev, " Error of this Agent is reported first\n"); =20 - trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask), + trace_aer_event(dev_name(&dev->dev), bus_type, (info->status & ~info->mas= k), info->severity, info->tlp_header_valid, &info->tlp); } =20 @@ -764,6 +765,7 @@ EXPORT_SYMBOL_GPL(cper_severity_to_aer); void pci_print_aer(struct pci_dev *dev, int aer_severity, struct aer_capability_regs *aer) { + const char *bus_type =3D pcie_is_cxl(dev) ? "CXL" : "PCIe"; int layer, agent, tlp_header_valid =3D 0; u32 status, mask; struct aer_err_info info; @@ -798,7 +800,7 @@ void pci_print_aer(struct pci_dev *dev, int aer_severit= y, if (tlp_header_valid) __print_tlp_header(dev, &aer->header_log); =20 - trace_aer_event(dev_name(&dev->dev), (status & ~mask), + trace_aer_event(dev_name(&dev->dev), bus_type, (status & ~mask), aer_severity, tlp_header_valid, &aer->header_log); } EXPORT_SYMBOL_NS_GPL(pci_print_aer, CXL); diff --git a/include/ras/ras_event.h b/include/ras/ras_event.h index e5f7ee0864e7..1bf8e7050ba8 100644 --- a/include/ras/ras_event.h +++ b/include/ras/ras_event.h @@ -297,15 +297,17 @@ TRACE_EVENT(non_standard_event, =20 TRACE_EVENT(aer_event, TP_PROTO(const char *dev_name, + const char *bus_type, const u32 status, const u8 severity, const u8 tlp_header_valid, struct pcie_tlp_log *tlp), =20 - TP_ARGS(dev_name, status, severity, tlp_header_valid, tlp), + TP_ARGS(dev_name, bus_type, status, severity, tlp_header_valid, tlp), =20 TP_STRUCT__entry( __string( dev_name, dev_name ) + __string( bus_type, bus_type ) __field( u32, status ) __field( u8, severity ) __field( u8, tlp_header_valid) @@ -314,6 +316,7 @@ TRACE_EVENT(aer_event, =20 TP_fast_assign( __assign_str(dev_name); + __assign_str(bus_type); __entry->status =3D status; __entry->severity =3D severity; __entry->tlp_header_valid =3D tlp_header_valid; @@ -325,8 +328,8 @@ TRACE_EVENT(aer_event, } ), =20 - TP_printk("%s PCIe Bus Error: severity=3D%s, %s, TLP Header=3D%s\n", - __get_str(dev_name), + TP_printk("%s %s Bus Error: severity=3D%s, %s, TLP Header=3D%s\n", + __get_str(dev_name), __get_str(bus_type), __entry->severity =3D=3D AER_CORRECTABLE ? "Corrected" : __entry->severity =3D=3D AER_FATAL ? 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000044FB.mail.protection.outlook.com (10.167.241.201) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8137.0 via Frontend Transport; Fri, 25 Oct 2024 21:04:07 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 25 Oct 2024 16:04:05 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 05/14] PCI/AER: Add CXL PCIe port correctable error support in AER service driver Date: Fri, 25 Oct 2024 16:02:56 -0500 Message-ID: <20241025210305.27499-6-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025210305.27499-1-terry.bowman@amd.com> References: <20241025210305.27499-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FB:EE_|DM6PR12MB4041:EE_ X-MS-Office365-Filtering-Correlation-Id: 64bcb1cf-5133-4ab8-0c85-08dcf53890a8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|36860700013|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 21:04:07.1798 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 64bcb1cf-5133-4ab8-0c85-08dcf53890a8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FB.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4041 Content-Type: text/plain; charset="utf-8" The AER service driver doesn't currently handle CXL protocol errors reported by CXL root ports, CXL upstream switch ports, and CXL downstream switch ports. Consequently, RAS protocol errors from CXL PCIe port devices are not properly logged or handled. These errors are reported to the OS via the root port's AER correctable and uncorrectable internal error fields. While the AER driver supports handling downstream port protocol errors in restricted CXL host (RCH) mode also known as CXL1.1, it lacks the same functionality for CXL PCIe ports operating in virtual hierarchy (VH) mode. To address this gap, update the AER driver to handle CXL PCIe port device protocol correctable errors (CE). Make this update alongside the existing downstream port RCH error handling logic, extending support to CXL PCIe ports in VH mode. is_internal_error() is currently limited by CONFIG_PCIEAER_CXL kernel config. Update is_internal_error()'s function declaration such that it is always available regardless if CONFIG_PCIEAER_CXL kernel config is enabled or disabled. The uncorrectable error (UCE) handling will be added in a future patch. [1] CXL 3.1 Spec, 12.2.2 CXL Root Ports, Downstream Switch Ports, and Upstream Switch Ports Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron --- drivers/pci/pcie/aer.c | 59 ++++++++++++++++++++++++++++-------------- 1 file changed, 39 insertions(+), 20 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 53e9a11f6c0f..1d3e5b929661 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -941,8 +941,15 @@ static bool find_source_device(struct pci_dev *parent, return true; } =20 -#ifdef CONFIG_PCIEAER_CXL +static bool is_internal_error(struct aer_err_info *info) +{ + if (info->severity =3D=3D AER_CORRECTABLE) + return info->status & PCI_ERR_COR_INTERNAL; =20 + return info->status & PCI_ERR_UNC_INTN; +} + +#ifdef CONFIG_PCIEAER_CXL /** * pci_aer_unmask_internal_errors - unmask internal errors * @dev: pointer to the pcie_dev data structure @@ -994,14 +1001,6 @@ static bool cxl_error_is_native(struct pci_dev *dev) return (pcie_ports_native || host->native_aer); } =20 -static bool is_internal_error(struct aer_err_info *info) -{ - if (info->severity =3D=3D AER_CORRECTABLE) - return info->status & PCI_ERR_COR_INTERNAL; - - return info->status & PCI_ERR_UNC_INTN; -} - static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) { struct aer_err_info *info =3D (struct aer_err_info *)data; @@ -1033,14 +1032,23 @@ static int cxl_rch_handle_error_iter(struct pci_dev= *dev, void *data) =20 static void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *inf= o) { - /* - * Internal errors of an RCEC indicate an AER error in an - * RCH's downstream port. Check and handle them in the CXL.mem - * device driver. - */ - if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC && - is_internal_error(info)) + if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC) pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info); + + if (info->severity =3D=3D AER_CORRECTABLE) { + struct pci_driver *pdrv =3D dev->driver; + int aer =3D dev->aer_cap; + + if (aer) + pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, + info->status); + + if (pdrv && pdrv->cxl_err_handler && + pdrv->cxl_err_handler->cor_error_detected) + pdrv->cxl_err_handler->cor_error_detected(dev); + + pcie_clear_device_status(dev); + } } =20 static int handles_cxl_error_iter(struct pci_dev *dev, void *data) @@ -1058,9 +1066,13 @@ static bool handles_cxl_errors(struct pci_dev *dev) { bool handles_cxl =3D false; =20 - if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC && - pcie_aer_is_native(dev)) + if (!pcie_aer_is_native(dev)) + return false; + + if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC) pcie_walk_rcec(dev, handles_cxl_error_iter, &handles_cxl); + else + handles_cxl =3D pcie_is_cxl_port(dev); =20 return handles_cxl; } @@ -1078,6 +1090,10 @@ static void cxl_enable_internal_errors(struct pci_de= v *dev) static inline void cxl_enable_internal_errors(struct pci_dev *dev) { } static inline void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *info) { } +static bool handles_cxl_errors(struct pci_dev *dev) +{ + return false; +} #endif =20 /** @@ -1115,8 +1131,11 @@ static void pci_aer_handle_error(struct pci_dev *dev= , struct aer_err_info *info) =20 static void handle_error_source(struct pci_dev *dev, struct aer_err_info *= info) { - cxl_handle_error(dev, info); - pci_aer_handle_error(dev, info); + if (is_internal_error(info) && handles_cxl_errors(dev)) + cxl_handle_error(dev, info); + else + pci_aer_handle_error(dev, info); + pci_dev_put(dev); } =20 --=20 2.34.1 From nobody Mon Nov 25 14:54:12 2024 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2056.outbound.protection.outlook.com [40.107.94.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9CAB217443; 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Fri, 25 Oct 2024 16:04:16 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 06/14] PCI/AER: Change AER driver to read UCE fatal status for all CXL PCIe port devices Date: Fri, 25 Oct 2024 16:02:57 -0500 Message-ID: <20241025210305.27499-7-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025210305.27499-1-terry.bowman@amd.com> References: <20241025210305.27499-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F7:EE_|MN2PR12MB4240:EE_ X-MS-Office365-Filtering-Correlation-Id: 517d4d12-5a8a-40b3-71a1-08dcf5389705 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|1800799024|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 21:04:17.8739 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 517d4d12-5a8a-40b3-71a1-08dcf5389705 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F7.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4240 Content-Type: text/plain; charset="utf-8" The AER service driver's aer_get_device_error_info() function doesn't read uncorrectable (UCE) fatal error status from PCIe upstream port devices, including CXL upstream switch ports. As a result, fatal errors are not logged or handled as needed for CXL PCIe upstream switch port devices. Update the aer_get_device_error_info() function to read the UCE fatal status for all CXL PCIe port devices. The fatal error status will be used in future patches implementing CXL PCIe port uncorrectable error handling and logging. Signed-off-by: Terry Bowman --- drivers/pci/pcie/aer.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 1d3e5b929661..d772f123c6a2 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1250,6 +1250,7 @@ int aer_get_device_error_info(struct pci_dev *dev, st= ruct aer_err_info *info) } else if (type =3D=3D PCI_EXP_TYPE_ROOT_PORT || type =3D=3D PCI_EXP_TYPE_RC_EC || type =3D=3D PCI_EXP_TYPE_DOWNSTREAM || + type =3D=3D PCI_EXP_TYPE_UPSTREAM || info->severity =3D=3D AER_NONFATAL) { =20 /* Link is still healthy for IO reads */ --=20 2.34.1 From nobody Mon Nov 25 14:54:12 2024 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2067.outbound.protection.outlook.com [40.107.212.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DB151B21B1; Fri, 25 Oct 2024 21:04:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 25 Oct 2024 16:04:27 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 07/14] PCI/AER: Add CXL PCIe port uncorrectable error recovery in AER service driver Date: Fri, 25 Oct 2024 16:02:58 -0500 Message-ID: <20241025210305.27499-8-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025210305.27499-1-terry.bowman@amd.com> References: <20241025210305.27499-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FD:EE_|CYXPR12MB9442:EE_ X-MS-Office365-Filtering-Correlation-Id: c66c381b-a2a5-428e-108c-08dcf5389d9e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|1800799024|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 21:04:28.8935 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c66c381b-a2a5-428e-108c-08dcf5389d9e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FD.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9442 Content-Type: text/plain; charset="utf-8" Existing recovery procedure for PCIe uncorrectable errors (UCE) does not apply to CXL devices. Recovery can not be used for CXL devices because of the potential for corruption on what can be system memory. Also, current PCIe UCE recovery does not begin at the bridge but begins at the bridge's first downstream device. This will miss handling CXL protocol errors in a CXL root port. A separate CXL recovery is needed because of the different handling requirements Add a new function, cxl_do_recovery() using the following. Add cxl_walk_bridge() to iterate the detected error's sub-topology. cxl_walk_bridge() is similar to pci_walk_bridge() but the CXL flavor will begin iteration at the bridge rather than beginning at the bridge's first downstream child. Add cxl_report_error_detected() as an analog to report_error_detected(). It will call pci_driver::cxl_err_handlers for each iterated downstream child. The pci_driver::cxl_err_handlers UCE handler returns a boolean indicating if there was a UCE error detected during handling. cxl_do_recovery() uses the status from cxl_report_error_detected() to determine how to proceed. Non-fatal CXL UCE errors will be treated as fatal. If a UCE was present during handling then cxl_do_recovery() will kernel panic. Signed-off-by: Terry Bowman --- drivers/pci/pci.h | 3 +++ drivers/pci/pcie/aer.c | 5 +++- drivers/pci/pcie/err.c | 54 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 61 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 14d00ce45bfa..5a67e41919d8 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -658,6 +658,9 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, pci_channel_state_t state, pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); =20 +/* CXL error reporting and handling */ +void cxl_do_recovery(struct pci_dev *dev); + bool pcie_wait_for_link(struct pci_dev *pdev, bool active); int pcie_retrain_link(struct pci_dev *pdev, bool use_lt); =20 diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index d772f123c6a2..19432ab2cfb6 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1048,7 +1048,10 @@ static void cxl_handle_error(struct pci_dev *dev, st= ruct aer_err_info *info) pdrv->cxl_err_handler->cor_error_detected(dev); =20 pcie_clear_device_status(dev); - } + } else if (info->severity =3D=3D AER_NONFATAL) + cxl_do_recovery(dev); + else if (info->severity =3D=3D AER_FATAL) + cxl_do_recovery(dev); } =20 static int handles_cxl_error_iter(struct pci_dev *dev, void *data) diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c index 31090770fffc..3785f4ca5103 100644 --- a/drivers/pci/pcie/err.c +++ b/drivers/pci/pcie/err.c @@ -276,3 +276,57 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, =20 return status; } + +static void cxl_walk_bridge(struct pci_dev *bridge, + int (*cb)(struct pci_dev *, void *), + void *userdata) +{ + bool *status =3D userdata; + + cb(bridge, status); + if (bridge->subordinate && !*status) + pci_walk_bus(bridge->subordinate, cb, status); +} + +static int cxl_report_error_detected(struct pci_dev *dev, void *data) +{ + struct pci_driver *pdrv =3D dev->driver; + bool *status =3D data; + + device_lock(&dev->dev); + if (pdrv && pdrv->cxl_err_handler && + pdrv->cxl_err_handler->error_detected) { + const struct cxl_error_handlers *cxl_err_handler =3D + pdrv->cxl_err_handler; + *status |=3D cxl_err_handler->error_detected(dev); + } + device_unlock(&dev->dev); + return *status; +} + +void cxl_do_recovery(struct pci_dev *dev) +{ + struct pci_host_bridge *host =3D pci_find_host_bridge(dev->bus); + int type =3D pci_pcie_type(dev); + struct pci_dev *bridge; + int status; + + if (type =3D=3D PCI_EXP_TYPE_ROOT_PORT || + type =3D=3D PCI_EXP_TYPE_DOWNSTREAM || + type =3D=3D PCI_EXP_TYPE_UPSTREAM || + type =3D=3D PCI_EXP_TYPE_ENDPOINT) + bridge =3D dev; + else + bridge =3D pci_upstream_bridge(dev); + + cxl_walk_bridge(bridge, cxl_report_error_detected, &status); + if (status) + panic("CXL cachemem error. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 21:04:40.0498 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d060fb99-2f41-4fdb-9a81-08dcf538a43f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FD.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB9070 Content-Type: text/plain; charset="utf-8" CXL PCIe port protocol error support will be added in the future. This requires searching for a CXL PCIe port device in the CXL topology as provided by find_cxl_port(). But, find_cxl_port() is defined static and as a result is not callable outside of this source file. Update the find_cxl_port() declaration to be non-static. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron --- drivers/cxl/core/core.h | 3 +++ drivers/cxl/core/port.c | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 0c62b4069ba0..d81e5ee25f58 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -110,4 +110,7 @@ bool cxl_need_node_perf_attrs_update(int nid); int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port, struct access_coordinate *c); =20 +struct cxl_port *find_cxl_port(struct device *dport_dev, + struct cxl_dport **dport); + #endif /* __CXL_CORE_H__ */ diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index e666ec6a9085..2ac835cd4f1b 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1342,8 +1342,8 @@ static struct cxl_port *__find_cxl_port(struct cxl_fi= nd_port_ctx *ctx) return NULL; } =20 -static struct cxl_port *find_cxl_port(struct device *dport_dev, - struct cxl_dport **dport) +struct cxl_port *find_cxl_port(struct device *dport_dev, + struct cxl_dport **dport) { struct cxl_find_port_ctx ctx =3D { .dport_dev =3D dport_dev, --=20 2.34.1 From nobody Mon Nov 25 14:54:12 2024 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2066.outbound.protection.outlook.com [40.107.244.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 516AB21441D; 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Fri, 25 Oct 2024 16:04:49 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 09/14] cxl/pci: Map CXL PCIe root port and downstream switch port RAS registers Date: Fri, 25 Oct 2024 16:03:00 -0500 Message-ID: <20241025210305.27499-10-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025210305.27499-1-terry.bowman@amd.com> References: <20241025210305.27499-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FA:EE_|DM4PR12MB6327:EE_ X-MS-Office365-Filtering-Correlation-Id: 571f49ff-d336-4644-2ed2-08dcf538ab0e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|36860700013|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 21:04:51.4699 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 571f49ff-d336-4644-2ed2-08dcf538ab0e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FA.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6327 Content-Type: text/plain; charset="utf-8" Map RAS registers for CXL PCIe root port and downstream RAS registers. Refactor and rename cxl_setup_parent_dport() to be cxl_init_ep_ports_aer(). Update the function to iterate an endpoint's parent downstream switch ports and parent root ports. It maps the RAS registers for each CXL downstream switch port and CXL root port iterated. Move the RAS register map logic from cxl_dport_map_regs() into cxl_dport_init_ras_reporting(). This eliminates an unnecessary helper. cxl_dport_map_regs() can be removed. cxl_dport_init_ras_reporting() must check for previously mapped registers within the topology, particularly with CXL switches. Endpoints under a CXL switch may share parent ports or downstream ports, ensure the ports' registers are only mapped once. Signed-off-by: Terry Bowman --- drivers/cxl/core/pci.c | 38 +++++++++++++++++--------------------- drivers/cxl/cxl.h | 6 ++---- drivers/cxl/mem.c | 26 ++++++++++++++++++++++++-- 3 files changed, 43 insertions(+), 27 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 5b46bc46aaa9..0bb61e39cf8f 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -749,18 +749,6 @@ static void cxl_dport_map_rch_aer(struct cxl_dport *dp= ort) } } =20 -static void cxl_dport_map_ras(struct cxl_dport *dport) -{ - struct cxl_register_map *map =3D &dport->reg_map; - struct device *dev =3D dport->dport_dev; - - if (!map->component_map.ras.valid) - dev_dbg(dev, "RAS registers not found\n"); - else if (cxl_map_component_regs(map, &dport->regs.component, - BIT(CXL_CM_CAP_CAP_ID_RAS))) - dev_dbg(dev, "Failed to map RAS capability.\n"); -} - static void cxl_disable_rch_root_ints(struct cxl_dport *dport) { void __iomem *aer_base =3D dport->regs.dport_aer; @@ -790,20 +778,28 @@ static void cxl_disable_rch_root_ints(struct cxl_dpor= t *dport) * @dport: the cxl_dport that needs to be initialized * @host: host device for devm operations */ -void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host) +void cxl_dport_init_ras_reporting(struct cxl_dport *dport) { - dport->reg_map.host =3D host; - cxl_dport_map_ras(dport); - - if (dport->rch) { - struct pci_host_bridge *host_bridge =3D to_pci_host_bridge(dport->dport_= dev); - - if (!host_bridge->native_aer) - return; + struct device *dport_dev =3D dport->dport_dev; + struct pci_host_bridge *host_bridge =3D to_pci_host_bridge(dport_dev); =20 + if (dport->rch && host_bridge->native_aer) { cxl_dport_map_rch_aer(dport); cxl_disable_rch_root_ints(dport); } + + /* dport may have more than 1 downstream EP. Check if already mapped. */ + if (dport->regs.ras) { + dev_warn(dport_dev, "RAS is already mapped\n"); + return; + } + + dport->reg_map.host =3D dport_dev; + if (cxl_map_component_regs(&dport->reg_map, &dport->regs.component, + BIT(CXL_CM_CAP_CAP_ID_RAS))) { + dev_err(dport_dev, "Failed to map RAS capability.\n"); + return; + } } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, CXL); =20 diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 0d8b810a51f0..787688e81602 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -762,11 +762,9 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_po= rt *port, resource_size_t rcrb); =20 #ifdef CONFIG_PCIEAER_CXL -void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport); -void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host); +void cxl_dport_init_ras_reporting(struct cxl_dport *dport); #else -static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport, - struct device *host) { } +static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport) {= } #endif =20 struct cxl_decoder *to_cxl_decoder(struct device *dev); diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index a9fd5cd5a0d2..240d54b22a8c 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -45,6 +45,29 @@ static int cxl_mem_dpa_show(struct seq_file *file, void = *data) return 0; } =20 +static bool dev_is_cxl_pci(struct device *dev, u32 pcie_type) +{ + struct pci_dev *pdev; + + if (!dev_is_pci(dev)) + return false; + + pdev =3D to_pci_dev(dev); + if (!pcie_is_cxl_port(pdev)) + return false; + + return (pci_pcie_type(pdev) =3D=3D pcie_type); +} + +static void cxl_init_ep_ports_aer(struct cxl_ep *ep) +{ + struct cxl_dport *dport =3D ep->dport; + + if (dev_is_cxl_pci(dport->dport_dev, PCI_EXP_TYPE_DOWNSTREAM) || + dev_is_cxl_pci(dport->dport_dev, PCI_EXP_TYPE_ROOT_PORT)) + cxl_dport_init_ras_reporting(dport); +} + static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *c= xlmd, struct cxl_dport *parent_dport) { @@ -62,6 +85,7 @@ static int devm_cxl_add_endpoint(struct device *host, str= uct cxl_memdev *cxlmd, =20 ep =3D cxl_ep_load(iter, cxlmd); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 21:05:01.9872 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c9018107-609b-4da9-fee8-08dcf538b152 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FD.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7936 Content-Type: text/plain; charset="utf-8" Add logic to map CXL PCIe upstream switch port (USP) RAS registers. Introduce 'struct cxl_regs' member into 'struct cxl_port' to store a pointer to the upstream port's mapped RAS registers. The upstream port may have multiple downstream endpoints. Before mapping AER registers check if the registers are already mapped. Signed-off-by: Terry Bowman --- drivers/cxl/core/pci.c | 17 +++++++++++++++++ drivers/cxl/cxl.h | 4 ++++ drivers/cxl/mem.c | 3 +++ 3 files changed, 24 insertions(+) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 0bb61e39cf8f..53ca773557f3 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -773,6 +773,23 @@ static void cxl_disable_rch_root_ints(struct cxl_dport= *dport) writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); } =20 +void cxl_uport_init_ras_reporting(struct cxl_port *port) +{ + /* uport may have more than 1 downstream EP. Check if already mapped. */ + if (port->uport_regs.ras) { + dev_warn(&port->dev, "RAS is already mapped\n"); + return; + } + + port->reg_map.host =3D &port->dev; + if (cxl_map_component_regs(&port->reg_map, &port->uport_regs, + BIT(CXL_CM_CAP_CAP_ID_RAS))) { + dev_err(&port->dev, "Failed to map RAS capability.\n"); + return; + } +} +EXPORT_SYMBOL_NS_GPL(cxl_uport_init_ras_reporting, CXL); + /** * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport * @dport: the cxl_dport that needs to be initialized diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 787688e81602..ded6a343c05e 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -592,6 +592,7 @@ struct cxl_dax_region { * @parent_dport: dport that points to this port in the parent * @decoder_ida: allocator for decoder ids * @reg_map: component and ras register mapping parameters + * @uport_regs: mapped component registers * @nr_dports: number of entries in @dports * @hdm_end: track last allocated HDM decoder instance for allocation orde= ring * @commit_end: cursor to track highest committed decoder for commit order= ing @@ -612,6 +613,7 @@ struct cxl_port { struct cxl_dport *parent_dport; struct ida decoder_ida; struct cxl_register_map reg_map; + struct cxl_component_regs uport_regs; int nr_dports; int hdm_end; int commit_end; @@ -763,8 +765,10 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_po= rt *port, =20 #ifdef CONFIG_PCIEAER_CXL void cxl_dport_init_ras_reporting(struct cxl_dport *dport); +void cxl_uport_init_ras_reporting(struct cxl_port *port); #else static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport) {= } +static inline void cxl_uport_init_ras_reporting(struct cxl_port *port) { } #endif =20 struct cxl_decoder *to_cxl_decoder(struct device *dev); diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 240d54b22a8c..067fd6389562 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -66,6 +66,9 @@ static void cxl_init_ep_ports_aer(struct cxl_ep *ep) if (dev_is_cxl_pci(dport->dport_dev, PCI_EXP_TYPE_DOWNSTREAM) || dev_is_cxl_pci(dport->dport_dev, PCI_EXP_TYPE_ROOT_PORT)) cxl_dport_init_ras_reporting(dport); + + if (dev_is_cxl_pci(dport->port->uport_dev, PCI_EXP_TYPE_UPSTREAM)) + cxl_uport_init_ras_reporting(dport->port); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 21:05:12.3427 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 744991a9-6ced-440b-1af6-08dcf538b77f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F7.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5680 Content-Type: text/plain; charset="utf-8" CXL PCIe port protocol error handling support will be added to the CXL drivers in the future. In preparation, rename the existing interfaces to support handling all CXL PCIe port protocol errors. The driver's RAS support functions currently rely on a 'struct cxl_dev_state' type parameter, which is not available for CXL port devices. However, since the same CXL RAS capability structure is needed across most CXL components and devices, a common handling approach should be adopted. To accommodate this, update the __cxl_handle_cor_ras() and __cxl_handle_ras() functions to use a `struct device` instead of `struct cxl_dev_state`. No functional changes are introduced. [1] CXL 3.1 Spec, 8.2.4 CXL.cache and CXL.mem Registers Signed-off-by: Terry Bowman --- drivers/cxl/core/pci.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 53ca773557f3..bb2fd7d04c4f 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -650,7 +650,7 @@ void read_cdat_data(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL); =20 -static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds, +static void __cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) { void __iomem *addr; @@ -663,13 +663,13 @@ static void __cxl_handle_cor_ras(struct cxl_dev_state= *cxlds, status =3D readl(addr); if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); - trace_cxl_aer_correctable_error(cxlds->cxlmd, status); + trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status); } } =20 static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds) { - return __cxl_handle_cor_ras(cxlds, cxlds->regs.ras); + return __cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->regs.ras); } =20 /* CXL spec rev3.0 8.2.4.16.1 */ @@ -693,8 +693,7 @@ static void header_log_copy(void __iomem *ras_base, u32= *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -static bool __cxl_handle_ras(struct cxl_dev_state *cxlds, - void __iomem *ras_base) +static bool __cxl_handle_ras(struct device *dev, void __iomem *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; @@ -721,7 +720,7 @@ static bool __cxl_handle_ras(struct cxl_dev_state *cxld= s, } =20 header_log_copy(ras_base, hl); - trace_cxl_aer_uncorrectable_error(cxlds->cxlmd, status, fe, hl); + trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); =20 return true; @@ -729,7 +728,7 @@ static bool __cxl_handle_ras(struct cxl_dev_state *cxld= s, =20 static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds) { - return __cxl_handle_ras(cxlds, cxlds->regs.ras); + return __cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->regs.ras); } =20 #ifdef CONFIG_PCIEAER_CXL @@ -823,13 +822,13 @@ EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, CX= L); static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { - return __cxl_handle_cor_ras(cxlds, dport->regs.ras); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 21:05:23.9403 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 52d1acc1-700b-4a2c-c5cb-08dcf538be68 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FD.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8339 Content-Type: text/plain; charset="utf-8" Introduce correctable and uncorrectable CXL PCIe port handlers. Use the PCIe port's device object to find the matching port or downstream port in the CXL topology. The matching port or downstream port will include the cached RAS register block. Invoke the existing __cxl_handle_ras() with the RAS registers as a parameter. __cxl_handle_ras() will log the RAS errors (if present) and clear the RAS status. Signed-off-by: Terry Bowman --- drivers/cxl/core/pci.c | 59 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index bb2fd7d04c4f..adb184d346ae 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -772,6 +772,65 @@ static void cxl_disable_rch_root_ints(struct cxl_dport= *dport) writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); } =20 +static int match_uport(struct device *dev, const void *data) +{ + struct device *uport_dev =3D (struct device *)data; + struct cxl_port *port; + + if (!is_cxl_port(dev)) + return 0; + + port =3D to_cxl_port(dev); + + return port->uport_dev =3D=3D uport_dev; +} + +static void __iomem *cxl_pci_port_ras(struct pci_dev *pdev) +{ + struct cxl_port *port __free(put_cxl_port) =3D NULL; + void __iomem *ras_base =3D NULL; + + if (!pdev) + return NULL; + + if ((pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_ROOT_PORT) || + (pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_DOWNSTREAM)) { + struct cxl_dport *dport; + + port =3D find_cxl_port(&pdev->dev, &dport); + ras_base =3D dport ? dport->regs.ras : NULL; + } else if (pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_UPSTREAM) { + struct device *port_dev; + + port_dev =3D bus_find_device(&cxl_bus_type, NULL, &pdev->dev, + match_uport); + if (!port_dev) + return NULL; + + port =3D to_cxl_port(port_dev); + ras_base =3D port ? port->uport_regs.ras : NULL; + } + + return ras_base; +} + +static void cxl_port_cor_error_detected(struct pci_dev *pdev) +{ + void __iomem *ras_base =3D cxl_pci_port_ras(pdev); + + __cxl_handle_cor_ras(&pdev->dev, ras_base); +} + +static bool cxl_port_error_detected(struct pci_dev *pdev) +{ + void __iomem *ras_base =3D cxl_pci_port_ras(pdev); + bool ue; + + ue =3D __cxl_handle_ras(&pdev->dev, ras_base); + + return ue; +} + void cxl_uport_init_ras_reporting(struct cxl_port *port) { /* uport may have more than 1 downstream EP. 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000044F6.mail.protection.outlook.com (10.167.241.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8137.0 via Frontend Transport; Fri, 25 Oct 2024 21:05:37 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 25 Oct 2024 16:05:33 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 13/14] cxl/pci: Add trace logging for CXL PCIe port RAS errors Date: Fri, 25 Oct 2024 16:03:04 -0500 Message-ID: <20241025210305.27499-14-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025210305.27499-1-terry.bowman@amd.com> References: <20241025210305.27499-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F6:EE_|PH7PR12MB8039:EE_ X-MS-Office365-Filtering-Correlation-Id: 970caabe-ae17-4867-221e-08dcf538c689 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|36860700013|1800799024|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 21:05:37.5742 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 970caabe-ae17-4867-221e-08dcf538c689 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F6.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8039 Content-Type: text/plain; charset="utf-8" The CXL drivers use kernel trace functions for logging endpoint and RCH downstream port RAS errors. Similar functionality is required for CXL root ports, CXL downstream switch ports, and CXL upstream switch ports. Introduce trace logging functions for both RAS correctable and uncorrectable errors specific to CXL PCIe ports. Additionally, update the PCIe port error handlers to invoke these new trace functions. Signed-off-by: Terry Bowman --- drivers/cxl/core/pci.c | 16 ++++++++++---- drivers/cxl/core/trace.h | 47 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+), 4 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index adb184d346ae..eeb4a64ba5b5 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -661,10 +661,14 @@ static void __cxl_handle_cor_ras(struct device *dev, =20 addr =3D ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; status =3D readl(addr); - if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { - writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); + if (!(status & CXL_RAS_CORRECTABLE_STATUS_MASK)) + return; + writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); + + if (is_cxl_memdev(dev)) trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status); - } + else if (dev_is_pci(dev)) + trace_cxl_port_aer_correctable_error(dev, status); } =20 static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds) @@ -720,7 +724,11 @@ static bool __cxl_handle_ras(struct device *dev, void = __iomem *ras_base) } =20 header_log_copy(ras_base, hl); - trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); + if (is_cxl_memdev(dev)) + trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); + else if (dev_is_pci(dev)) + trace_cxl_port_aer_uncorrectable_error(dev, status, fe, hl); + writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); =20 return true; diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h index 8672b42ee4d1..1c4368a7b50b 100644 --- a/drivers/cxl/core/trace.h +++ b/drivers/cxl/core/trace.h @@ -48,6 +48,34 @@ { CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" } \ ) =20 +TRACE_EVENT(cxl_port_aer_uncorrectable_error, + TP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl), + TP_ARGS(dev, status, fe, hl), + TP_STRUCT__entry( + __string(devname, dev_name(dev)) + __string(host, dev_name(dev->parent)) + __field(u32, status) + __field(u32, first_error) + __array(u32, header_log, CXL_HEADERLOG_SIZE_U32) + ), + TP_fast_assign( + __assign_str(devname); + __assign_str(host); + __entry->status =3D status; + __entry->first_error =3D fe; + /* + * Embed the 512B headerlog data for user app retrieval and + * parsing, but no need to print this in the trace buffer. + */ + memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE); + ), + TP_printk("device=3D%s host=3D%s status: '%s' first_error: '%s'", + __get_str(devname), __get_str(host), + show_uc_errs(__entry->status), + show_uc_errs(__entry->first_error) + ) +); + TRACE_EVENT(cxl_aer_uncorrectable_error, TP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl), TP_ARGS(cxlmd, status, fe, hl), @@ -96,6 +124,25 @@ TRACE_EVENT(cxl_aer_uncorrectable_error, { CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer" } \ ) =20 +TRACE_EVENT(cxl_port_aer_correctable_error, + TP_PROTO(struct device *dev, u32 status), + TP_ARGS(dev, status), + TP_STRUCT__entry( + __string(devname, dev_name(dev)) + __string(host, dev_name(dev->parent)) + __field(u32, status) + ), + TP_fast_assign( + __assign_str(devname); + __assign_str(host); + __entry->status =3D status; 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Fri, 25 Oct 2024 21:05:46 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000044F7.mail.protection.outlook.com (10.167.241.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8137.0 via Frontend Transport; Fri, 25 Oct 2024 21:05:45 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 25 Oct 2024 16:05:44 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 14/14] cxl/pci: Add support to assign and clear pci_driver::cxl_err_handlers Date: Fri, 25 Oct 2024 16:03:05 -0500 Message-ID: <20241025210305.27499-15-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025210305.27499-1-terry.bowman@amd.com> References: <20241025210305.27499-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F7:EE_|CH2PR12MB4327:EE_ X-MS-Office365-Filtering-Correlation-Id: 6a0fa4dc-03c6-4606-2fce-08dcf538cb79 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|36860700013|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 21:05:45.8583 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6a0fa4dc-03c6-4606-2fce-08dcf538cb79 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F7.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4327 Content-Type: text/plain; charset="utf-8" pci_driver::cxl_err_handlers are not currrently assigned handler callbacks. The handlers can't be set in the pci_driver static definition because the CXL PCIe port devices are bound to the portdrv driver which is not CXL driver aware. Add cxl_assign_port_error_handlers() in the cxl_core module. This function will assign the default handlers for a CXL PCIe port device. When the CXL port (cxl_port or cxl_dport) is destroyed the CXL PCIe port device's pci_driver::cxl_err_handlers must be set to NULL to prevent future use. Create cxl_clear_port_error_handlers() and register it to be called when the CXL port device (cxl_port or cxl_dport) is destroyed. Signed-off-by: Terry Bowman --- drivers/cxl/core/pci.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index eeb4a64ba5b5..5f7570c6173c 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -839,8 +839,36 @@ static bool cxl_port_error_detected(struct pci_dev *pd= ev) return ue; } =20 +static const struct cxl_error_handlers cxl_port_error_handlers =3D { + .error_detected =3D cxl_port_error_detected, + .cor_error_detected =3D cxl_port_cor_error_detected, +}; + +static void cxl_assign_port_error_handlers(struct pci_dev *pdev) +{ + struct pci_driver *pdrv =3D pdev->driver; + + if (!pdrv) + return; + + pdrv->cxl_err_handler =3D &cxl_port_error_handlers; +} + +static void cxl_clear_port_error_handlers(void *data) +{ + struct pci_dev *pdev =3D data; + struct pci_driver *pdrv =3D pdev->driver; + + if (!pdrv) + return; + + pdrv->cxl_err_handler =3D NULL; +} + void cxl_uport_init_ras_reporting(struct cxl_port *port) { + struct pci_dev *pdev =3D to_pci_dev(port->uport_dev); + /* uport may have more than 1 downstream EP. Check if already mapped. */ if (port->uport_regs.ras) { dev_warn(&port->dev, "RAS is already mapped\n"); @@ -853,6 +881,9 @@ void cxl_uport_init_ras_reporting(struct cxl_port *port) dev_err(&port->dev, "Failed to map RAS capability.\n"); return; } + + cxl_assign_port_error_handlers(pdev); + devm_add_action_or_reset(port->uport_dev, cxl_clear_port_error_handlers, = pdev); } EXPORT_SYMBOL_NS_GPL(cxl_uport_init_ras_reporting, CXL); =20 @@ -865,6 +896,7 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dpo= rt) { struct device *dport_dev =3D dport->dport_dev; struct pci_host_bridge *host_bridge =3D to_pci_host_bridge(dport_dev); + struct pci_dev *pdev =3D to_pci_dev(dport_dev); =20 if (dport->rch && host_bridge->native_aer) { cxl_dport_map_rch_aer(dport); @@ -883,6 +915,9 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dpo= rt) dev_err(dport_dev, "Failed to map RAS capability.\n"); return; } + + cxl_assign_port_error_handlers(pdev); + devm_add_action_or_reset(dport_dev, cxl_clear_port_error_handlers, pdev); } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, CXL); =20 --=20 2.34.1