From nobody Mon Nov 25 14:41:09 2024 Received: from out-178.mta1.migadu.com (out-178.mta1.migadu.com [95.215.58.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A5061FB8A9 for ; Fri, 25 Oct 2024 18:24:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880653; cv=none; b=adHTI/U00XpWTv9e7Wt5dPIFv529PVbFPbflg8E9vUYPM3DcfRA8wA0+Vjh8KZaILVQ9EnLyIevRLATFDX5wQs7OCS8y3on9CBD8mxh/AgHWPPNja/uPR70Svx+mZu1w1i2o7RcebnLKTvaFUumlVB0piUe3x5OW3GCeEdalR2o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880653; c=relaxed/simple; bh=PDCcPrQinjbIXiZ5EARzDQFjXrFM6VDckRuDEtXvSTc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KlfEUmapD98IvMPHfucBg1kkHj11BUpxbMpE/2Y/0dpoA35TtmoMgpnagOc3oqkWIEEWFlHBBcWIupZshDbWsdWZERU/DUT+ljq6FsZk7v7SdtPZs2QOY9jBFknqqzJZyuqZgcFkivejXvzC75aeW5h6YywkNPvOqJsDO0oor5Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=J9K565V5; arc=none smtp.client-ip=95.215.58.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="J9K565V5" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1729880648; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AENT3HV05ZYgfYGtK7xFvzc3fnZN0pfnRLgWILAuZnQ=; b=J9K565V5Mp1DK+wZq8UNE8ZhLwLNylJy4zux1sSKU6e9q/asZkxef2QDlnTmHlez3xIKcR 8Un/4YcuL2+92GFzohCcrXuwYh0sNgMbMX3O8GMiEkZl9zhxqWcZMBNJBwZFh3VzmXrht1 8sHA075HhzvHi20Sxz5ES3vHtFQ0MN4= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Oliver Upton Subject: [PATCH v4 01/18] KVM: arm64: Extend masking facility to arbitrary registers Date: Fri, 25 Oct 2024 18:23:36 +0000 Message-ID: <20241025182354.3364124-2-oliver.upton@linux.dev> In-Reply-To: <20241025182354.3364124-1-oliver.upton@linux.dev> References: <20241025182354.3364124-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" From: Marc Zyngier We currently only use the masking (RES0/RES1) facility for VNCR registers, as they are memory-based and thus easy to sanitise. But we could apply the same thing to other registers if we: - split the sanitisation from __VNCR_START__ - apply the sanitisation when reading from a HW register This involves a new "marker" in the vcpu_sysreg enum, which defines the point at which the sanitisation applies (the VNCR registers being of course after this marker). Whle we are at it, rename kvm_vcpu_sanitise_vncr_reg() to kvm_vcpu_apply_reg_masks(), which is vaguely more explicit, and harden set_sysreg_masks() against setting masks for random registers... Signed-off-by: Marc Zyngier Reviewed-by: Joey Gouly Signed-off-by: Oliver Upton Reviewed-by: Marc Zyngier --- arch/arm64/include/asm/kvm_host.h | 19 +++++++++++++------ arch/arm64/kvm/nested.c | 12 ++++++++---- arch/arm64/kvm/sys_regs.c | 3 +++ 3 files changed, 24 insertions(+), 10 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 94cff508874b..07c7d2b7b3a3 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -367,7 +367,7 @@ struct kvm_arch { =20 u64 ctr_el0; =20 - /* Masks for VNCR-baked sysregs */ + /* Masks for VNCR-backed and general EL2 sysregs */ struct kvm_sysreg_masks *sysreg_masks; =20 /* @@ -401,6 +401,9 @@ struct kvm_vcpu_fault_info { r =3D __VNCR_START__ + ((VNCR_ ## r) / 8), \ __after_##r =3D __MAX__(__before_##r - 1, r) =20 +#define MARKER(m) \ + m, __after_##m =3D m - 1 + enum vcpu_sysreg { __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ MPIDR_EL1, /* MultiProcessor Affinity Register */ @@ -487,7 +490,11 @@ enum vcpu_sysreg { CNTHV_CTL_EL2, CNTHV_CVAL_EL2, =20 - __VNCR_START__, /* Any VNCR-capable reg goes after this point */ + /* Anything from this can be RES0/RES1 sanitised */ + MARKER(__SANITISED_REG_START__), + + /* Any VNCR-capable reg goes after this point */ + MARKER(__VNCR_START__), =20 VNCR(SCTLR_EL1),/* System Control Register */ VNCR(ACTLR_EL1),/* Auxiliary Control Register */ @@ -547,7 +554,7 @@ struct kvm_sysreg_masks { struct { u64 res0; u64 res1; - } mask[NR_SYS_REGS - __VNCR_START__]; + } mask[NR_SYS_REGS - __SANITISED_REG_START__]; }; =20 struct kvm_cpu_context { @@ -995,13 +1002,13 @@ static inline u64 *___ctxt_sys_reg(const struct kvm_= cpu_context *ctxt, int r) =20 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r)) =20 -u64 kvm_vcpu_sanitise_vncr_reg(const struct kvm_vcpu *, enum vcpu_sysreg); +u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *, enum vcpu_sysreg, u6= 4); #define __vcpu_sys_reg(v,r) \ (*({ \ const struct kvm_cpu_context *ctxt =3D &(v)->arch.ctxt; \ u64 *__r =3D __ctxt_sys_reg(ctxt, (r)); \ - if (vcpu_has_nv((v)) && (r) >=3D __VNCR_START__) \ - *__r =3D kvm_vcpu_sanitise_vncr_reg((v), (r)); \ + if (vcpu_has_nv((v)) && (r) >=3D __SANITISED_REG_START__) \ + *__r =3D kvm_vcpu_apply_reg_masks((v), (r), *__r);\ __r; \ })) =20 diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c index f9e30dd34c7a..b20b3bfb9cae 100644 --- a/arch/arm64/kvm/nested.c +++ b/arch/arm64/kvm/nested.c @@ -908,15 +908,15 @@ static void limit_nv_id_regs(struct kvm *kvm) kvm_set_vm_id_reg(kvm, SYS_ID_AA64DFR0_EL1, val); } =20 -u64 kvm_vcpu_sanitise_vncr_reg(const struct kvm_vcpu *vcpu, enum vcpu_sysr= eg sr) +u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *vcpu, + enum vcpu_sysreg sr, u64 v) { - u64 v =3D ctxt_sys_reg(&vcpu->arch.ctxt, sr); struct kvm_sysreg_masks *masks; =20 masks =3D vcpu->kvm->arch.sysreg_masks; =20 if (masks) { - sr -=3D __VNCR_START__; + sr -=3D __SANITISED_REG_START__; =20 v &=3D ~masks->mask[sr].res0; v |=3D masks->mask[sr].res1; @@ -927,7 +927,11 @@ u64 kvm_vcpu_sanitise_vncr_reg(const struct kvm_vcpu *= vcpu, enum vcpu_sysreg sr) =20 static void set_sysreg_masks(struct kvm *kvm, int sr, u64 res0, u64 res1) { - int i =3D sr - __VNCR_START__; + int i =3D sr - __SANITISED_REG_START__; + + BUILD_BUG_ON(!__builtin_constant_p(sr)); + BUILD_BUG_ON(sr < __SANITISED_REG_START__); + BUILD_BUG_ON(sr >=3D NR_SYS_REGS); =20 kvm->arch.sysreg_masks->mask[i].res0 =3D res0; kvm->arch.sysreg_masks->mask[i].res1 =3D res1; diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index dad88e31f953..30fe940cd5bd 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -165,6 +165,9 @@ u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int = reg) =20 /* Get the current version of the EL1 counterpart. */ WARN_ON(!__vcpu_read_sys_reg_from_cpu(el1r, &val)); + if (reg >=3D __SANITISED_REG_START__) + val =3D kvm_vcpu_apply_reg_masks(vcpu, reg, val); + return val; } =20 --=20 2.47.0.163.g1226f6d8fa-goog From nobody Mon Nov 25 14:41:09 2024 Received: from out-187.mta1.migadu.com (out-187.mta1.migadu.com [95.215.58.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60F17209F57 for ; Fri, 25 Oct 2024 18:24:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880654; cv=none; b=d6GNCxIjKnndfn/B87W/sSvuniA2jJqjSfNt55fc3PSvPPFDpqcAXdhcNgnL/8lKd7LxpJcde1hu3abwjcoLJJlkDri8qUjjaoGyYVUFoS+TmLGd8DLSY+Dmvr3Hy7QQmzVwYv203uI4JxP8gwZ4GhexSKjiWhMo5osWf1eaREM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880654; c=relaxed/simple; bh=5hfrBegQJ+ZnoqKqylzYAuKuo/qmiAnNrTvu/0ZGM8Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1729880650; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=X+s7YOZIeIWAs/5W19BCTzijIhqnkURfVQCL2Dnr1iE=; b=I5ZziLi59uBxmOn9KsacgP2NIz3Ie6Lhy8SqDAM6jRPm/4eud6+Qlq9lUmhzo3O9N+ZgaV WTsy494La1HGQqrXB5hEpsrZyYNGl1xECZ9hCyu+E336CwQCBpjSDKC/H61OjALXM3OWJv 6dHXKahNrismibLkAD5VTxOFypxi2GQ= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Oliver Upton Subject: [PATCH v4 02/18] arm64: sysreg: Describe ID_AA64DFR2_EL1 fields Date: Fri, 25 Oct 2024 18:23:37 +0000 Message-ID: <20241025182354.3364124-3-oliver.upton@linux.dev> In-Reply-To: <20241025182354.3364124-1-oliver.upton@linux.dev> References: <20241025182354.3364124-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Describe the new ID register in line with DDI0601 2024-09. Signed-off-by: Oliver Upton Reviewed-by: Marc Zyngier --- arch/arm64/tools/sysreg | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 8d637ac4b7c6..5670e51a6f90 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1287,6 +1287,32 @@ Field 15:8 BRPs Field 7:0 SYSPMUID EndSysreg =20 +Sysreg ID_AA64DFR2_EL1 3 0 0 5 2 +Res0 63:28 +UnsignedEnum 27:24 TRBE_EXC + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 23:20 SPE_nVM + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 19:16 SPE_EXC + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 15:8 +UnsignedEnum 7:4 BWE + 0b0000 NI + 0b0001 FEAT_BWE + 0b0002 FEAT_BWE2 +EndEnum +UnsignedEnum 3:0 STEP + 0b0000 NI + 0b0001 IMP +EndEnum +EndSysreg + Sysreg ID_AA64AFR0_EL1 3 0 0 5 4 Res0 63:32 Field 31:28 IMPDEF7 --=20 2.47.0.163.g1226f6d8fa-goog From nobody Mon Nov 25 14:41:09 2024 Received: from out-177.mta1.migadu.com (out-177.mta1.migadu.com [95.215.58.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EDA120EA2F for ; Fri, 25 Oct 2024 18:24:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880657; cv=none; b=kUYy1fHCK7BNCBwXMqcP7GXFeSYp4aUcnRfY8RzJz04oCjZW+TzXkNCzzUPvg56h4EbofQBdgf8kD12AmA9yOgBlLFIJ3UnU80f1fr/eBeptRS3/Irb91QfaVg3gxHrhjKNzp2MpyZO1IeQC7/59mW1nEJsGe18iKRqQMmZTMH4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880657; c=relaxed/simple; bh=QK86OF+M6Cnw2Q+RRRDm2E/w+KGWMmdJhG0adCArxK0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kXXTF9PLVTAB32ONIKCin9Vx+sXa5xnEYf1BEEVMf6UcUF4LWROMh35ZqdzHN07iWEDGnUZgYk0YAxR5rn9A2dLjvjVmw8W4VXg9j4wpeu85k4Vr3XociQ7NaSPltjE6AcgFc1jX2pwd+zUn3Y4hHaG9Tfdp+A7EhVYJTP0fXWg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=E0L114QL; arc=none smtp.client-ip=95.215.58.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="E0L114QL" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1729880652; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4wt7hpGsUlZRR1MZ3fpe3CXoXzKibMI0SDo4lB5jVPg=; b=E0L114QLgltFCgRG6Xy5/Zqz8lHJUkqPukCPSaQz59FYFykUgrTSG+jR7y81Sq2JXIQ2hK 9f92rYIW3JKXdu53D86AsxWmCXRTNx3pdgWPKb7qPdoI0FDpWWIn9ncUtRs6n+7slEc0rD 6daq2Kplo1Zu1mSaJPSq2foCC2x4WDI= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Oliver Upton Subject: [PATCH v4 03/18] arm64: sysreg: Migrate MDCR_EL2 definition to table Date: Fri, 25 Oct 2024 18:23:38 +0000 Message-ID: <20241025182354.3364124-4-oliver.upton@linux.dev> In-Reply-To: <20241025182354.3364124-1-oliver.upton@linux.dev> References: <20241025182354.3364124-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Migrate MDCR_EL2 over to the sysreg table and align definitions with DDI0601 2024-09. Signed-off-by: Oliver Upton Reviewed-by: Marc Zyngier --- arch/arm64/include/asm/kvm_arm.h | 29 -------------------------- arch/arm64/tools/sysreg | 35 ++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+), 29 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_= arm.h index 109a85ee6910..fb8d15f299a4 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -311,35 +311,6 @@ GENMASK(19, 18) | \ GENMASK(15, 0)) =20 -/* Hyp Debug Configuration Register bits */ -#define MDCR_EL2_E2TB_MASK (UL(0x3)) -#define MDCR_EL2_E2TB_SHIFT (UL(24)) -#define MDCR_EL2_HPMFZS (UL(1) << 36) -#define MDCR_EL2_HPMFZO (UL(1) << 29) -#define MDCR_EL2_MTPME (UL(1) << 28) -#define MDCR_EL2_TDCC (UL(1) << 27) -#define MDCR_EL2_HLP (UL(1) << 26) -#define MDCR_EL2_HCCD (UL(1) << 23) -#define MDCR_EL2_TTRF (UL(1) << 19) -#define MDCR_EL2_HPMD (UL(1) << 17) -#define MDCR_EL2_TPMS (UL(1) << 14) -#define MDCR_EL2_E2PB_MASK (UL(0x3)) -#define MDCR_EL2_E2PB_SHIFT (UL(12)) -#define MDCR_EL2_TDRA (UL(1) << 11) -#define MDCR_EL2_TDOSA (UL(1) << 10) -#define MDCR_EL2_TDA (UL(1) << 9) -#define MDCR_EL2_TDE (UL(1) << 8) -#define MDCR_EL2_HPME (UL(1) << 7) -#define MDCR_EL2_TPM (UL(1) << 6) -#define MDCR_EL2_TPMCR (UL(1) << 5) -#define MDCR_EL2_HPMN_MASK (UL(0x1F)) -#define MDCR_EL2_RES0 (GENMASK(63, 37) | \ - GENMASK(35, 30) | \ - GENMASK(25, 24) | \ - GENMASK(22, 20) | \ - BIT(18) | \ - GENMASK(16, 15)) - /* * FGT register definitions * diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 5670e51a6f90..7061cf2d8444 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2414,6 +2414,41 @@ Field 1 AFSR1_EL1 Field 0 AFSR0_EL1 EndSysregFields =20 +Sysreg MDCR_EL2 3 4 1 1 1 +Res0 63:51 +Field 50 EnSTEPOP +Res0 49:44 +Field 43 EBWE +Res0 42 +Field 41:40 PMEE +Res0 39:37 +Field 36 HPMFZS +Res0 35:32 +Field 31:30 PMSSE +Field 29 HPMFZO +Field 28 MTPME +Field 27 TDCC +Field 26 HLP +Field 25:24 E2TB +Field 23 HCCD +Res0 22:20 +Field 19 TTRF +Res0 18 +Field 17 HPMD +Res0 16 +Field 15 EnSPM +Field 14 TPMS +Field 13:12 E2PB +Field 11 TDRA +Field 10 TDOSA +Field 9 TDA +Field 8 TDE +Field 7 HPME +Field 6 TPM +Field 5 TPMCR +Field 4:0 HPMN +EndSysreg + Sysreg HFGRTR_EL2 3 4 1 1 4 Fields HFGxTR_EL2 EndSysreg --=20 2.47.0.163.g1226f6d8fa-goog From nobody Mon Nov 25 14:41:09 2024 Received: from out-183.mta1.migadu.com (out-183.mta1.migadu.com [95.215.58.183]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8537020EA3F for ; Fri, 25 Oct 2024 18:24:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.183 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880658; cv=none; b=RubTmHX1Vv8dqUZblx5bdUUXW+aWjWY/+/EdHdNYJCCulw/FAQVJnd3/Fx/EvqeaYMy5dEWL+1MPOeQMGZ0hdi652CEzLm3w8RLAx0ZHrkAwKAyLab6TOGXoRym+UgYZ8Tg9eG1QG+xe8Pxb6eeIPPixwUgzOxKXkh3640GloSM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880658; c=relaxed/simple; bh=9MaTPQcI0kQdWN9IrNV5oXDv71+tP8RwqE7/m2nJRyQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YrXcN1A5oSr5M4vU8P7unUeyqYGi2yLjDK9VhV1xK2AJQBq9n2YFSd1x6O6t0/6oCj2vP9j8X+V3tW2NqqXP2mrMvcWPvZikeJF+fG+OC3bDD93irJW6VmMfP4o35vJUPERRilYKt/l6cc80xkCbF7+MXNGNu1SthC4pdHeiEMQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=n7nmhSXY; arc=none smtp.client-ip=95.215.58.183 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="n7nmhSXY" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1729880655; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WvBdGV/fEuM1t1ncHOm4+9FLFUwv2pJggZf0gOiw5tU=; b=n7nmhSXYNWWwPRgwzEdAF6dz9klA0M5XAE3gthqTLWz1eb3m758VfO+i4G0qjXjatishgW luSdCFMukzAqipU76CQu054hbuPD4HAzci8qf8xhT34g5HUXaxv9vU+/dzJTlYu9wvTpih 3bxhITS8dxoq/HJAGeW6WG8tbdaiV94= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Oliver Upton Subject: [PATCH v4 04/18] arm64: sysreg: Add new definitions for ID_AA64DFR0_EL1 Date: Fri, 25 Oct 2024 18:23:39 +0000 Message-ID: <20241025182354.3364124-5-oliver.upton@linux.dev> In-Reply-To: <20241025182354.3364124-1-oliver.upton@linux.dev> References: <20241025182354.3364124-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Align the field definitions w/ DDI0601 2024-09 and opportunistically declare MTPMU as a signed field. Signed-off-by: Oliver Upton Reviewed-by: Marc Zyngier --- arch/arm64/tools/sysreg | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 7061cf2d8444..e5d2c25fe463 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1200,7 +1200,7 @@ UnsignedEnum 55:52 BRBE 0b0001 IMP 0b0010 BRBE_V1P1 EndEnum -Enum 51:48 MTPMU +SignedEnum 51:48 MTPMU 0b0000 NI_IMPDEF 0b0001 IMP 0b1111 NI @@ -1208,6 +1208,7 @@ EndEnum UnsignedEnum 47:44 TraceBuffer 0b0000 NI 0b0001 IMP + 0b0010 TRBE_V1P1 EndEnum UnsignedEnum 43:40 TraceFilt 0b0000 NI @@ -1224,11 +1225,18 @@ UnsignedEnum 35:32 PMSVer 0b0011 V1P2 0b0100 V1P3 0b0101 V1P4 + 0b0110 V1P5 EndEnum Field 31:28 CTX_CMPs -Res0 27:24 +UnsignedEnum 27:24 SEBEP + 0b0000 NI + 0b0001 IMP +EndEnum Field 23:20 WRPs -Res0 19:16 +UnsignedEnum 19:16 PMSS + 0b0000 NI + 0b0001 IMP +EndEnum Field 15:12 BRPs UnsignedEnum 11:8 PMUVer 0b0000 NI @@ -1238,6 +1246,7 @@ UnsignedEnum 11:8 PMUVer 0b0110 V3P5 0b0111 V3P7 0b1000 V3P8 + 0b1001 V3P9 0b1111 IMP_DEF EndEnum UnsignedEnum 7:4 TraceVer --=20 2.47.0.163.g1226f6d8fa-goog From nobody Mon Nov 25 14:41:09 2024 Received: from out-176.mta1.migadu.com (out-176.mta1.migadu.com [95.215.58.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10CB220D51D for ; Fri, 25 Oct 2024 18:24:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880661; cv=none; b=uZWEfKjPDnZQV1BlVS42b8+QMaM7rb8qJ/ywGarq9Uk9EzuWI4OBdACV3dc2LpWeUD3VZXKSy8ocyF7dIn3MfeLVSthpLLjj91pBm8eZw+lc90Qj8oojaPhkOSA+6Rd+1eqSW5Li/HIEAs8sacK/GnHJFz+5L7surFZB9PtnR0U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880661; c=relaxed/simple; bh=VYwuvl/xw3pSsqF154eu/B3sMo2iWzU5sAmrgp0ruZ8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MFFYLVEAhGEUlPS7A1Z7wf5LIwQFZattqkilCzpHVEfUUQDciiDPyoMqcAzDqnTQlQz/NaSD28oIC7/sjGwqKrUfFoCTlASwkGNs1LG2TeAavLJCd5CRNrD1uHzRqTEskDit0RTrwzAwaHh/AoCNWymjiTPS1g2ghB50MA6eHSw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=GtvuLaGn; arc=none smtp.client-ip=95.215.58.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="GtvuLaGn" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1729880657; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fmDWvCoZ7RJkt3LBlK0ytyCUy3NDKnSPU2karwJr82A=; b=GtvuLaGniKuhPHatIPMHOKL3PAWVdOsfWYvQBeWxdgjB6QLj/cIPjRdEvDn0cIc9yDDf1A rKRZRSmxTxvnn79TqAM6oF26UVi5MI/TijmZ9zO0fgOh6elsMGWOYxrLXD85SQVtaxiKky oMbONfZ6u7KfXH+L7ZHZ0HiS0vdVlP4= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Oliver Upton Subject: [PATCH v4 05/18] KVM: arm64: Describe RES0/RES1 bits of MDCR_EL2 Date: Fri, 25 Oct 2024 18:23:40 +0000 Message-ID: <20241025182354.3364124-6-oliver.upton@linux.dev> In-Reply-To: <20241025182354.3364124-1-oliver.upton@linux.dev> References: <20241025182354.3364124-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Add support for sanitising MDCR_EL2 and describe the RES0/RES1 bits according to the feature set exposed to the VM. Signed-off-by: Oliver Upton Reviewed-by: Marc Zyngier --- arch/arm64/include/asm/kvm_host.h | 2 +- arch/arm64/kvm/nested.c | 37 +++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 07c7d2b7b3a3..ca8fe74920d4 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -464,7 +464,6 @@ enum vcpu_sysreg { /* EL2 registers */ SCTLR_EL2, /* System Control Register (EL2) */ ACTLR_EL2, /* Auxiliary Control Register (EL2) */ - MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */ CPTR_EL2, /* Architectural Feature Trap Register (EL2) */ HACR_EL2, /* Hypervisor Auxiliary Control Register */ ZCR_EL2, /* SVE Control Register (EL2) */ @@ -492,6 +491,7 @@ enum vcpu_sysreg { =20 /* Anything from this can be RES0/RES1 sanitised */ MARKER(__SANITISED_REG_START__), + MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */ =20 /* Any VNCR-capable reg goes after this point */ MARKER(__VNCR_START__), diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c index b20b3bfb9cae..d256a495a6ba 100644 --- a/arch/arm64/kvm/nested.c +++ b/arch/arm64/kvm/nested.c @@ -1186,5 +1186,42 @@ int kvm_init_nv_sysregs(struct kvm *kvm) res0 |=3D SCTLR_EL1_EPAN; set_sysreg_masks(kvm, SCTLR_EL1, res0, res1); =20 + /* MDCR_EL2 */ + res0 =3D MDCR_EL2_RES0; + res1 =3D MDCR_EL2_RES1; + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, IMP)) + res0 |=3D (MDCR_EL2_HPMN | MDCR_EL2_TPMCR | + MDCR_EL2_TPM | MDCR_EL2_HPME); + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSVer, IMP)) + res0 |=3D MDCR_EL2_E2PB | MDCR_EL2_TPMS; + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, SPMU, IMP)) + res0 |=3D MDCR_EL2_EnSPM; + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, V3P1)) + res0 |=3D MDCR_EL2_HPMD; + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, TraceFilt, IMP)) + res0 |=3D MDCR_EL2_TTRF; + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, V3P5)) + res0 |=3D MDCR_EL2_HCCD | MDCR_EL2_HLP; + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, TraceBuffer, IMP)) + res0 |=3D MDCR_EL2_E2TB; + if (!kvm_has_feat(kvm, ID_AA64MMFR0_EL1, FGT, IMP)) + res0 |=3D MDCR_EL2_TDCC; + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, MTPMU, IMP) || + kvm_has_feat(kvm, ID_AA64PFR0_EL1, EL3, IMP)) + res0 |=3D MDCR_EL2_MTPME; + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, V3P7)) + res0 |=3D MDCR_EL2_HPMFZO; + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSS, IMP)) + res0 |=3D MDCR_EL2_PMSSE; + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSVer, V1P2)) + res0 |=3D MDCR_EL2_HPMFZS; + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, EBEP, IMP)) + res0 |=3D MDCR_EL2_PMEE; + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, DebugVer, V8P9)) + res0 |=3D MDCR_EL2_EBWE; + if (!kvm_has_feat(kvm, ID_AA64DFR2_EL1, STEP, IMP)) + res0 |=3D MDCR_EL2_EnSTEPOP; + set_sysreg_masks(kvm, MDCR_EL2, res0, res1); + return 0; } --=20 2.47.0.163.g1226f6d8fa-goog From nobody Mon Nov 25 14:41:09 2024 Received: from out-180.mta1.migadu.com (out-180.mta1.migadu.com [95.215.58.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1A1820F3F2 for ; Fri, 25 Oct 2024 18:24:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880663; cv=none; b=fwliQk4Tkkq66m/xAF16RT3Ybi0au7Axs6SNAEx+z+ab/TmMCePrmPYweRtmuQm9ZiAxka6Iv8rh+V37MFMeo2PpYa58rzLca/lZuw42hBjVV6sY6Rf5msXQVOSQIjP0k+togq70/iLjq5vYHeGl+HZXppzUYjp0XrnetuaMAAc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880663; c=relaxed/simple; bh=d9/iMdqKv+XLG6+WmqeIMg4S4oZiommor9qaH5XHqAM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UW5X4hlbUayoK4wlnkbUXRG8VkNTzO94b1l90ewxZ+pC38B9wM4rR3WLWWjQ+NYVIDlgINxiqGFp7zwhvQVlJ1tCXMIN2RqOix1mxkHF+ak2TyWiS4PXCo1BvNR9SP7pwNVHyW9jUZObueKe1lxxCv4v62V2RUEUjedAL51JUMQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=xAAF1zES; arc=none smtp.client-ip=95.215.58.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="xAAF1zES" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1729880660; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Tm9klPokIaTyW3+rN5LwBgShYgrwmCrkRkYvLTHZaEA=; b=xAAF1zESpqxl1al57F1z2eSH8ygVVG+N3KSq01OZtIqfAMMSELrvox0sC+4RDq+b9SYJq3 MdECuMdcFKZZeXmfrvw2ReJZEt2Xhj5DRyrQ+E9c1sKn6HWz7kRsEq+SA4iui5q7WCxFQR 6/i4BWazmfpCJnUoc5vmnA7L1o61H2g= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Oliver Upton Subject: [PATCH v4 06/18] KVM: arm64: nv: Allow coarse-grained trap combos to use complex traps Date: Fri, 25 Oct 2024 18:23:41 +0000 Message-ID: <20241025182354.3364124-7-oliver.upton@linux.dev> In-Reply-To: <20241025182354.3364124-1-oliver.upton@linux.dev> References: <20241025182354.3364124-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" KVM uses a sanity-check to avoid infinite recursion in trap combinations that could potentially depend on itself. Narrow the scope of this sanity check to the exact CGT IDs that correspond w/ trap combos, opening the door to using 'complex' traps as part of a combination. Signed-off-by: Oliver Upton Reviewed-by: Marc Zyngier --- arch/arm64/kvm/emulate-nested.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-neste= d.c index 05b6435d02a9..da7ab14e036d 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -2021,7 +2021,8 @@ int __init populate_nv_trap_config(void) cgids =3D coarse_control_combo[id - __MULTIPLE_CONTROL_BITS__]; =20 for (int i =3D 0; cgids[i] !=3D __RESERVED__; i++) { - if (cgids[i] >=3D __MULTIPLE_CONTROL_BITS__) { + if (cgids[i] >=3D __MULTIPLE_CONTROL_BITS__ && + cgids[i] < __COMPLEX_CONDITIONS__) { kvm_err("Recursive MCB %d/%d\n", id, cgids[i]); ret =3D -EINVAL; } --=20 2.47.0.163.g1226f6d8fa-goog From nobody Mon Nov 25 14:41:09 2024 Received: from out-185.mta1.migadu.com (out-185.mta1.migadu.com [95.215.58.185]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4C74212192 for ; Fri, 25 Oct 2024 18:24:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.185 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880666; cv=none; b=hO3l43OzMpUMavXQXpGqY2qwRhhXCrVyUd/jpaA33VOHRpwWljaRS3MKqjI12nsGNuzOi/XR41F627E+OGrb3ht0eJXQ0ayI8meosACRUmrOY/8vTZjE522aHmW1/K0srXKJFQz9F3ipKDEWOOJbqwLxVRFndTz1nUtr9O6Eqso= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880666; c=relaxed/simple; bh=3EsE2vEicI2ETRqCYydgDpIAjz4gjCDUHguJ3uyP0r4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZFKMRKWvkpQ3T8cTuNDKY44w52WuoWMafep9bWB4JdtKragS7tn2ujSt0YKr0WDPf6qaeNvNpoIEux4rOW/RmY9fpucNm6/AtGAz+MG/DTjxQ+dGvaga16tsij3xRcnPbHqKIQVRVJBuoIitDWxtL4pjdKmNkGW4SMND2LOAlxo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=D1ftKHiL; arc=none smtp.client-ip=95.215.58.185 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="D1ftKHiL" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1729880662; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=n/vLH7IaL0kII0g5Ri1DQb8sfURLSg7RQrQ+zZ1bWxc=; b=D1ftKHiLBpxZpeDW3gJBo1dAzJERsV8gyxofBmZSunivwtLQlRAhy7K2YacZwCqOBZrGm7 XQOAkbDvOaaz9sEOBFnw9/dDMWqSxLBdVTKjRWA0w0k4e5YKosTP1IlAJv4YY/E9Z9DpnB Uqx7iHkDcrI8GLQhVJgDE0M39PUFC8Q= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Oliver Upton Subject: [PATCH v4 07/18] KVM: arm64: nv: Rename BEHAVE_FORWARD_ANY Date: Fri, 25 Oct 2024 18:23:42 +0000 Message-ID: <20241025182354.3364124-8-oliver.upton@linux.dev> In-Reply-To: <20241025182354.3364124-1-oliver.upton@linux.dev> References: <20241025182354.3364124-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" BEHAVE_FORWARD_ANY is slightly ambiguous, especially since we're about to cram some more information into the enum. Rephrase it. Signed-off-by: Oliver Upton Reviewed-by: Marc Zyngier --- arch/arm64/kvm/emulate-nested.c | 93 +++++++++++++++++---------------- 1 file changed, 47 insertions(+), 46 deletions(-) diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-neste= d.c index da7ab14e036d..e1a30d1bcd06 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -16,9 +16,10 @@ =20 enum trap_behaviour { BEHAVE_HANDLE_LOCALLY =3D 0, + BEHAVE_FORWARD_READ =3D BIT(0), BEHAVE_FORWARD_WRITE =3D BIT(1), - BEHAVE_FORWARD_ANY =3D BEHAVE_FORWARD_READ | BEHAVE_FORWARD_WRITE, + BEHAVE_FORWARD_RW =3D BEHAVE_FORWARD_READ | BEHAVE_FORWARD_WRITE, }; =20 struct trap_bits { @@ -138,7 +139,7 @@ static const struct trap_bits coarse_trap_bits[] =3D { .index =3D HCR_EL2, .value =3D HCR_TID2, .mask =3D HCR_TID2, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_HCR_TID3] =3D { .index =3D HCR_EL2, @@ -162,37 +163,37 @@ static const struct trap_bits coarse_trap_bits[] =3D { .index =3D HCR_EL2, .value =3D HCR_TIDCP, .mask =3D HCR_TIDCP, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_HCR_TACR] =3D { .index =3D HCR_EL2, .value =3D HCR_TACR, .mask =3D HCR_TACR, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_HCR_TSW] =3D { .index =3D HCR_EL2, .value =3D HCR_TSW, .mask =3D HCR_TSW, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_HCR_TPC] =3D { /* Also called TCPC when FEAT_DPB is implemented */ .index =3D HCR_EL2, .value =3D HCR_TPC, .mask =3D HCR_TPC, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_HCR_TPU] =3D { .index =3D HCR_EL2, .value =3D HCR_TPU, .mask =3D HCR_TPU, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_HCR_TTLB] =3D { .index =3D HCR_EL2, .value =3D HCR_TTLB, .mask =3D HCR_TTLB, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_HCR_TVM] =3D { .index =3D HCR_EL2, @@ -204,7 +205,7 @@ static const struct trap_bits coarse_trap_bits[] =3D { .index =3D HCR_EL2, .value =3D HCR_TDZ, .mask =3D HCR_TDZ, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_HCR_TRVM] =3D { .index =3D HCR_EL2, @@ -216,205 +217,205 @@ static const struct trap_bits coarse_trap_bits[] = =3D { .index =3D HCR_EL2, .value =3D HCR_TLOR, .mask =3D HCR_TLOR, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_HCR_TERR] =3D { .index =3D HCR_EL2, .value =3D HCR_TERR, .mask =3D HCR_TERR, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_HCR_APK] =3D { .index =3D HCR_EL2, .value =3D 0, .mask =3D HCR_APK, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_HCR_NV] =3D { .index =3D HCR_EL2, .value =3D HCR_NV, .mask =3D HCR_NV, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_HCR_NV_nNV2] =3D { .index =3D HCR_EL2, .value =3D HCR_NV, .mask =3D HCR_NV | HCR_NV2, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_HCR_NV1_nNV2] =3D { .index =3D HCR_EL2, .value =3D HCR_NV | HCR_NV1, .mask =3D HCR_NV | HCR_NV1 | HCR_NV2, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_HCR_AT] =3D { .index =3D HCR_EL2, .value =3D HCR_AT, .mask =3D HCR_AT, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_HCR_nFIEN] =3D { .index =3D HCR_EL2, .value =3D 0, .mask =3D HCR_FIEN, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_HCR_TID4] =3D { .index =3D HCR_EL2, .value =3D HCR_TID4, .mask =3D HCR_TID4, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_HCR_TICAB] =3D { .index =3D HCR_EL2, .value =3D HCR_TICAB, .mask =3D HCR_TICAB, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_HCR_TOCU] =3D { .index =3D HCR_EL2, .value =3D HCR_TOCU, .mask =3D HCR_TOCU, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_HCR_ENSCXT] =3D { .index =3D HCR_EL2, .value =3D 0, .mask =3D HCR_ENSCXT, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_HCR_TTLBIS] =3D { .index =3D HCR_EL2, .value =3D HCR_TTLBIS, .mask =3D HCR_TTLBIS, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_HCR_TTLBOS] =3D { .index =3D HCR_EL2, .value =3D HCR_TTLBOS, .mask =3D HCR_TTLBOS, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_MDCR_TPMCR] =3D { .index =3D MDCR_EL2, .value =3D MDCR_EL2_TPMCR, .mask =3D MDCR_EL2_TPMCR, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_MDCR_TPM] =3D { .index =3D MDCR_EL2, .value =3D MDCR_EL2_TPM, .mask =3D MDCR_EL2_TPM, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_MDCR_TDE] =3D { .index =3D MDCR_EL2, .value =3D MDCR_EL2_TDE, .mask =3D MDCR_EL2_TDE, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_MDCR_TDA] =3D { .index =3D MDCR_EL2, .value =3D MDCR_EL2_TDA, .mask =3D MDCR_EL2_TDA, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_MDCR_TDOSA] =3D { .index =3D MDCR_EL2, .value =3D MDCR_EL2_TDOSA, .mask =3D MDCR_EL2_TDOSA, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_MDCR_TDRA] =3D { .index =3D MDCR_EL2, .value =3D MDCR_EL2_TDRA, .mask =3D MDCR_EL2_TDRA, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_MDCR_E2PB] =3D { .index =3D MDCR_EL2, .value =3D 0, .mask =3D BIT(MDCR_EL2_E2PB_SHIFT), - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_MDCR_TPMS] =3D { .index =3D MDCR_EL2, .value =3D MDCR_EL2_TPMS, .mask =3D MDCR_EL2_TPMS, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_MDCR_TTRF] =3D { .index =3D MDCR_EL2, .value =3D MDCR_EL2_TTRF, .mask =3D MDCR_EL2_TTRF, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_MDCR_E2TB] =3D { .index =3D MDCR_EL2, .value =3D 0, .mask =3D BIT(MDCR_EL2_E2TB_SHIFT), - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_MDCR_TDCC] =3D { .index =3D MDCR_EL2, .value =3D MDCR_EL2_TDCC, .mask =3D MDCR_EL2_TDCC, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_CPACR_E0POE] =3D { .index =3D CPTR_EL2, .value =3D CPACR_ELx_E0POE, .mask =3D CPACR_ELx_E0POE, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_CPTR_TAM] =3D { .index =3D CPTR_EL2, .value =3D CPTR_EL2_TAM, .mask =3D CPTR_EL2_TAM, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_CPTR_TCPAC] =3D { .index =3D CPTR_EL2, .value =3D CPTR_EL2_TCPAC, .mask =3D CPTR_EL2_TCPAC, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_HCRX_EnFPM] =3D { .index =3D HCRX_EL2, .value =3D 0, .mask =3D HCRX_EL2_EnFPM, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_HCRX_TCR2En] =3D { .index =3D HCRX_EL2, .value =3D 0, .mask =3D HCRX_EL2_TCR2En, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_ICH_HCR_TC] =3D { .index =3D ICH_HCR_EL2, .value =3D ICH_HCR_TC, .mask =3D ICH_HCR_TC, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_ICH_HCR_TALL0] =3D { .index =3D ICH_HCR_EL2, .value =3D ICH_HCR_TALL0, .mask =3D ICH_HCR_TALL0, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_ICH_HCR_TALL1] =3D { .index =3D ICH_HCR_EL2, .value =3D ICH_HCR_TALL1, .mask =3D ICH_HCR_TALL1, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, [CGT_ICH_HCR_TDIR] =3D { .index =3D ICH_HCR_EL2, .value =3D ICH_HCR_TDIR, .mask =3D ICH_HCR_TDIR, - .behaviour =3D BEHAVE_FORWARD_ANY, + .behaviour =3D BEHAVE_FORWARD_RW, }, }; =20 @@ -474,7 +475,7 @@ static enum trap_behaviour check_cnthctl_el1pcten(struc= t kvm_vcpu *vcpu) if (get_sanitized_cnthctl(vcpu) & (CNTHCTL_EL1PCTEN << 10)) return BEHAVE_HANDLE_LOCALLY; =20 - return BEHAVE_FORWARD_ANY; + return BEHAVE_FORWARD_RW; } =20 static enum trap_behaviour check_cnthctl_el1pten(struct kvm_vcpu *vcpu) @@ -482,7 +483,7 @@ static enum trap_behaviour check_cnthctl_el1pten(struct= kvm_vcpu *vcpu) if (get_sanitized_cnthctl(vcpu) & (CNTHCTL_EL1PCEN << 10)) return BEHAVE_HANDLE_LOCALLY; =20 - return BEHAVE_FORWARD_ANY; + return BEHAVE_FORWARD_RW; } =20 static enum trap_behaviour check_cptr_tta(struct kvm_vcpu *vcpu) @@ -493,7 +494,7 @@ static enum trap_behaviour check_cptr_tta(struct kvm_vc= pu *vcpu) val =3D translate_cptr_el2_to_cpacr_el1(val); =20 if (val & CPACR_ELx_TTA) - return BEHAVE_FORWARD_ANY; + return BEHAVE_FORWARD_RW; =20 return BEHAVE_HANDLE_LOCALLY; } --=20 2.47.0.163.g1226f6d8fa-goog From nobody Mon Nov 25 14:41:09 2024 Received: from out-178.mta1.migadu.com (out-178.mta1.migadu.com [95.215.58.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44415214412 for ; Fri, 25 Oct 2024 18:24:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880669; cv=none; b=V2nhnrHubQJ0DgUrwZTB9cNb1j6HPmvI3RAGy3MF4UR55xXtvsoDjA6HTGYh9Rf6pwDK5ax4rPdvxezA2NDZ+pV7OFDyyYEbixQaIQiGiBk5ISm44N42ueVhhDUF8DrEIyzYcKltuXZkB7AcYUUQwmqbc7Yc8ccr787B13rG2Js= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880669; c=relaxed/simple; bh=+CCGNeATfq1uVnjy7GKENLX5OKoPHdpQn41Y6gDlXMc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JUyKN0b/A4mdrPBjbV4mQ5q6LRahYzAAMwsPz05my5obvveK0WH3uFOkVlHAHizk3X71Gkq23LKZ7wAqi43bP7/dX589QV1hblD2GlcY8QEKjskDa9jf8pM2NSfISvGfBnqFG1AFLgrKNhrdeW1JkkgVW8qzDj+HlqsMWgkZQ80= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=BHWNcQWP; arc=none smtp.client-ip=95.215.58.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="BHWNcQWP" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1729880664; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jKTm4m4xkSSDot5gqGTZZQZNLb6OMOWuE8JyjW0IZZY=; b=BHWNcQWPDW1S1mG8FF6FNSbbPA6gMsGUnfLq7qoAakfp3QrKtVLHp1hE4I1Q8Yxn9KyTcM 2JrFBBuq3MAwMvrO0NzOxMrDU8WxpP1NrplBleeyITXFegwZruuBZoBhqr003jNmwGgqvl 7oHkKhlvePI2uDD92XrZH6d+ZqmjmzI= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Oliver Upton Subject: [PATCH v4 08/18] KVM: arm64: nv: Reinject traps that take effect in Host EL0 Date: Fri, 25 Oct 2024 18:23:43 +0000 Message-ID: <20241025182354.3364124-9-oliver.upton@linux.dev> In-Reply-To: <20241025182354.3364124-1-oliver.upton@linux.dev> References: <20241025182354.3364124-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Wire up the other end of traps that affect host EL0 by actually injecting them into the guest hypervisor. Skip over FGT entirely, as a cursory glance suggests no FGT is effective in host EL0. Note that kvm_inject_nested() is already equipped for handling exceptions while the VM is already in a host context. Signed-off-by: Oliver Upton Reviewed-by: Marc Zyngier --- arch/arm64/include/asm/kvm_emulate.h | 5 +++++ arch/arm64/kvm/emulate-nested.c | 29 ++++++++++++++++++++++++---- 2 files changed, 30 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/= kvm_emulate.h index a601a9305b10..bf0c48403f59 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -225,6 +225,11 @@ static inline bool is_hyp_ctxt(const struct kvm_vcpu *= vcpu) return vcpu_has_nv(vcpu) && __is_hyp_ctxt(&vcpu->arch.ctxt); } =20 +static inline bool vcpu_is_host_el0(const struct kvm_vcpu *vcpu) +{ + return is_hyp_ctxt(vcpu) && !vcpu_is_el2(vcpu); +} + /* * The layout of SPSR for an AArch32 state is different when observed from= an * AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArc= h32 diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-neste= d.c index e1a30d1bcd06..db3149379a4d 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -20,6 +20,9 @@ enum trap_behaviour { BEHAVE_FORWARD_READ =3D BIT(0), BEHAVE_FORWARD_WRITE =3D BIT(1), BEHAVE_FORWARD_RW =3D BEHAVE_FORWARD_READ | BEHAVE_FORWARD_WRITE, + + /* Traps that take effect in Host EL0, this is rare! */ + BEHAVE_IN_HOST_EL0 =3D BIT(2), }; =20 struct trap_bits { @@ -2128,11 +2131,19 @@ static u64 kvm_get_sysreg_res0(struct kvm *kvm, enu= m vcpu_sysreg sr) return masks->mask[sr - __VNCR_START__].res0; } =20 -static bool check_fgt_bit(struct kvm *kvm, bool is_read, +static bool check_fgt_bit(struct kvm_vcpu *vcpu, bool is_read, u64 val, const union trap_config tc) { + struct kvm *kvm =3D vcpu->kvm; enum vcpu_sysreg sr; =20 + /* + * KVM doesn't know about any FGTs that apply to the host, and hopefully + * that'll remain the case. + */ + if (is_hyp_ctxt(vcpu)) + return false; + if (tc.pol) return (val & BIT(tc.bit)); =20 @@ -2209,7 +2220,15 @@ bool triage_sysreg_trap(struct kvm_vcpu *vcpu, int *= sr_index) * If we're not nesting, immediately return to the caller, with the * sysreg index, should we have it. */ - if (!vcpu_has_nv(vcpu) || is_hyp_ctxt(vcpu)) + if (!vcpu_has_nv(vcpu)) + goto local; + + /* + * There are a few traps that take effect InHost, but are constrained + * to EL0. Don't bother with computing the trap behaviour if the vCPU + * isn't in EL0. + */ + if (is_hyp_ctxt(vcpu) && !vcpu_is_host_el0(vcpu)) goto local; =20 switch ((enum fgt_group_id)tc.fgt) { @@ -2255,12 +2274,14 @@ bool triage_sysreg_trap(struct kvm_vcpu *vcpu, int = *sr_index) goto local; } =20 - if (tc.fgt !=3D __NO_FGT_GROUP__ && check_fgt_bit(vcpu->kvm, is_read, - val, tc)) + if (tc.fgt !=3D __NO_FGT_GROUP__ && check_fgt_bit(vcpu, is_read, val, tc)) goto inject; =20 b =3D compute_trap_behaviour(vcpu, tc); =20 + if (!(b & BEHAVE_IN_HOST_EL0) && vcpu_is_host_el0(vcpu)) + goto local; + if (((b & BEHAVE_FORWARD_READ) && is_read) || ((b & BEHAVE_FORWARD_WRITE) && !is_read)) goto inject; --=20 2.47.0.163.g1226f6d8fa-goog From nobody Mon Nov 25 14:41:09 2024 Received: from out-183.mta1.migadu.com (out-183.mta1.migadu.com [95.215.58.183]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78C9E20D510 for ; Fri, 25 Oct 2024 18:24:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.183 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880670; cv=none; b=V783PmsoN7nT8bDTyiC5WFEnMq+etbE/UYzZECmAUZn5kn9+FjXU/Sr8L7WJaPrJN0R27UUBHzirJN/oiklJDLa8kdvJ2yIX8cXdL17AHLylIcjJYfcKmK1phijlBFsk6kxIH/PtqLXfDTkD320aHgv/Q7OC5rrW9wQw1iU/4i0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880670; c=relaxed/simple; bh=WnSYByWaIFbInwg4nT4ofApbDtPsbrFsPtiK9NnqSqs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=M+ndcJX6Vx2z3SlLOYair0pOAInXyFqIGM4Mk98e67e/0AEjlgiaRUD3HTMEfJ7NwQ8WxX6ZAZ6Db3Buu2KC08hOmXC6xIWfm77GXG+anDDrAfpzedeH/SwpNVZfTX9JWvSMm1Ow2pf8rhI82hwOakIttgCQCrnUnUafK1lO46o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=jSZuZMk5; arc=none smtp.client-ip=95.215.58.183 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="jSZuZMk5" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1729880666; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WjjCMEH326B4LIDtFwwuu6AngDXjHoyjb9Jg0/u5tag=; b=jSZuZMk5cy4cNE8GXAQNT/7vHsZAh7Dm7WBue7XiC5Q1fMP5x9QZoGdUFmWvcnEJD1WfzC jPKx4TBmEhEr8J0ktcwf1DZM+rqXuj8j6sjWP9T29K8OJ7FqbZFWmR1RKfkiNOWgjhuYh7 l1PGly1+mmLdAZrKdvlfVV5H8gDfuyU= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Oliver Upton Subject: [PATCH v4 09/18] KVM: arm64: nv: Honor MDCR_EL2.{TPM, TPMCR} in Host EL0 Date: Fri, 25 Oct 2024 18:23:44 +0000 Message-ID: <20241025182354.3364124-10-oliver.upton@linux.dev> In-Reply-To: <20241025182354.3364124-1-oliver.upton@linux.dev> References: <20241025182354.3364124-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" TPM and TPMCR trap bits also affect Host EL0. How fun. Mark these two trap bits as such and take advantage of the new infrastructure for dealing w/ EL0 traps. Signed-off-by: Oliver Upton Reviewed-by: Marc Zyngier --- arch/arm64/kvm/emulate-nested.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-neste= d.c index db3149379a4d..f9594296d69c 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -304,13 +304,15 @@ static const struct trap_bits coarse_trap_bits[] =3D { .index =3D MDCR_EL2, .value =3D MDCR_EL2_TPMCR, .mask =3D MDCR_EL2_TPMCR, - .behaviour =3D BEHAVE_FORWARD_RW, + .behaviour =3D BEHAVE_FORWARD_RW | + BEHAVE_IN_HOST_EL0, }, [CGT_MDCR_TPM] =3D { .index =3D MDCR_EL2, .value =3D MDCR_EL2_TPM, .mask =3D MDCR_EL2_TPM, - .behaviour =3D BEHAVE_FORWARD_RW, + .behaviour =3D BEHAVE_FORWARD_RW | + BEHAVE_IN_HOST_EL0, }, [CGT_MDCR_TDE] =3D { .index =3D MDCR_EL2, --=20 2.47.0.163.g1226f6d8fa-goog From nobody Mon Nov 25 14:41:09 2024 Received: from out-186.mta1.migadu.com (out-186.mta1.migadu.com [95.215.58.186]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC3421FF7D1 for ; Fri, 25 Oct 2024 18:24:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.186 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880673; cv=none; b=AQ3cRHqx8PnWPDyVDlbsXhef8/HGWPXoMEM5ii4WYI33bUnOqjzDdxLEONmdq4ndsZCyVy+2P+UA8153NMOsIZeehBkdqkE0VOSiV4ctdBSIjcdXRwfMGJRM3GmfvjET8XF/K8VnfMEnjPC2K7hiIFrJtnvou7gatRQuBisqZ2Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880673; c=relaxed/simple; bh=ltX2mgpEB6IEDsXh/X1u+xWVkggWg+VB8D07XKoYAOA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OV7eTec38J67m+am811UxXnodsnu/deVVeUha3jyrlpJbwXjWd3HgYCgyyFgIN0uYJxzvYmSRmfBg/2aqTvznFvO01q1P1wB6zHk/C9YVj22O+IkZQQxR+4IpTvhd9q0jjHIgqKwVk/Nlqb1Na2rQy/RFg19B2APjuWVMUjHEGw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=xTAYKlCE; arc=none smtp.client-ip=95.215.58.186 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="xTAYKlCE" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1729880669; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=03U+X0r3TsTKJK2hDl3YaYsZRpw044pn5Clu5ZhImjs=; b=xTAYKlCEg66jYYufMomKCrzMyj9DQx9Do6a7sgFexgRLn5UmntQdu9B+2JAyu980NkxTTF JT/yeQlixu926B6luxvxCjKWN9BRkYg1BNVVMCX1M9rjyjBjnQpj5BuvHCqUpCqlaZ4n5k UspkUBXMQd3g1CUSXuymWm9DzO3CuJ0= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Oliver Upton Subject: [PATCH v4 10/18] KVM: arm64: nv: Describe trap behaviour of MDCR_EL2.HPMN Date: Fri, 25 Oct 2024 18:23:45 +0000 Message-ID: <20241025182354.3364124-11-oliver.upton@linux.dev> In-Reply-To: <20241025182354.3364124-1-oliver.upton@linux.dev> References: <20241025182354.3364124-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" MDCR_EL2.HPMN splits the PMU event counters into two ranges: the first range is accessible from all ELs, and the second range is accessible only to EL2/3. Supposing the guest hypervisor allows direct access to the PMU counters from the L2, KVM needs to locally handle those accesses. Add a new complex trap configuration for HPMN that checks if the counter index is accessible to the current context. As written, the architecture suggests HPMN only causes PMEVCNTR_EL0 to trap, though intuition (and the pseudocode) suggest that the trap applies to PMEVTYPER_EL0 as well. Signed-off-by: Oliver Upton Reviewed-by: Marc Zyngier --- arch/arm64/kvm/emulate-nested.c | 160 +++++++++++++++++++------------- arch/arm64/kvm/pmu-emul.c | 18 ++++ include/kvm/arm_pmu.h | 6 ++ 3 files changed, 120 insertions(+), 64 deletions(-) diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-neste= d.c index f9594296d69c..162bddbfbe79 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -110,6 +110,7 @@ enum cgt_group_id { CGT_HCR_TPU_TOCU, CGT_HCR_NV1_nNV2_ENSCXT, CGT_MDCR_TPM_TPMCR, + CGT_MDCR_TPM_HPMN, CGT_MDCR_TDE_TDA, CGT_MDCR_TDE_TDOSA, CGT_MDCR_TDE_TDRA, @@ -126,6 +127,7 @@ enum cgt_group_id { CGT_CNTHCTL_EL1PTEN, =20 CGT_CPTR_TTA, + CGT_MDCR_HPMN, =20 /* Must be last */ __NR_CGT_GROUP_IDS__ @@ -441,6 +443,7 @@ static const enum cgt_group_id *coarse_control_combo[] = =3D { MCB(CGT_HCR_TPU_TOCU, CGT_HCR_TPU, CGT_HCR_TOCU), MCB(CGT_HCR_NV1_nNV2_ENSCXT, CGT_HCR_NV1_nNV2, CGT_HCR_ENSCXT), MCB(CGT_MDCR_TPM_TPMCR, CGT_MDCR_TPM, CGT_MDCR_TPMCR), + MCB(CGT_MDCR_TPM_HPMN, CGT_MDCR_TPM, CGT_MDCR_HPMN), MCB(CGT_MDCR_TDE_TDA, CGT_MDCR_TDE, CGT_MDCR_TDA), MCB(CGT_MDCR_TDE_TDOSA, CGT_MDCR_TDE, CGT_MDCR_TDOSA), MCB(CGT_MDCR_TDE_TDRA, CGT_MDCR_TDE, CGT_MDCR_TDRA), @@ -504,6 +507,34 @@ static enum trap_behaviour check_cptr_tta(struct kvm_v= cpu *vcpu) return BEHAVE_HANDLE_LOCALLY; } =20 +static enum trap_behaviour check_mdcr_hpmn(struct kvm_vcpu *vcpu) +{ + u32 sysreg =3D esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu)); + unsigned int idx; + + + switch (sysreg) { + case SYS_PMEVTYPERn_EL0(0) ... SYS_PMEVTYPERn_EL0(30): + case SYS_PMEVCNTRn_EL0(0) ... SYS_PMEVCNTRn_EL0(30): + idx =3D (sys_reg_CRm(sysreg) & 0x3) << 3 | sys_reg_Op2(sysreg); + break; + case SYS_PMXEVTYPER_EL0: + case SYS_PMXEVCNTR_EL0: + idx =3D SYS_FIELD_GET(PMSELR_EL0, SEL, + __vcpu_sys_reg(vcpu, PMSELR_EL0)); + break; + default: + /* Someone used this trap helper for something else... */ + KVM_BUG_ON(1, vcpu->kvm); + return BEHAVE_HANDLE_LOCALLY; + } + + if (kvm_pmu_counter_is_hyp(vcpu, idx)) + return BEHAVE_FORWARD_RW | BEHAVE_IN_HOST_EL0; + + return BEHAVE_HANDLE_LOCALLY; +} + #define CCC(id, fn) \ [id - __COMPLEX_CONDITIONS__] =3D fn =20 @@ -511,6 +542,7 @@ static const complex_condition_check ccc[] =3D { CCC(CGT_CNTHCTL_EL1PCTEN, check_cnthctl_el1pcten), CCC(CGT_CNTHCTL_EL1PTEN, check_cnthctl_el1pten), CCC(CGT_CPTR_TTA, check_cptr_tta), + CCC(CGT_MDCR_HPMN, check_mdcr_hpmn), }; =20 /* @@ -925,77 +957,77 @@ static const struct encoding_to_trap_config encoding_= to_cgt[] __initconst =3D { SR_TRAP(SYS_PMOVSCLR_EL0, CGT_MDCR_TPM), SR_TRAP(SYS_PMCEID0_EL0, CGT_MDCR_TPM), SR_TRAP(SYS_PMCEID1_EL0, CGT_MDCR_TPM), - SR_TRAP(SYS_PMXEVTYPER_EL0, CGT_MDCR_TPM), + SR_TRAP(SYS_PMXEVTYPER_EL0, CGT_MDCR_TPM_HPMN), SR_TRAP(SYS_PMSWINC_EL0, CGT_MDCR_TPM), SR_TRAP(SYS_PMSELR_EL0, CGT_MDCR_TPM), - SR_TRAP(SYS_PMXEVCNTR_EL0, CGT_MDCR_TPM), + SR_TRAP(SYS_PMXEVCNTR_EL0, CGT_MDCR_TPM_HPMN), SR_TRAP(SYS_PMCCNTR_EL0, CGT_MDCR_TPM), SR_TRAP(SYS_PMUSERENR_EL0, CGT_MDCR_TPM), SR_TRAP(SYS_PMINTENSET_EL1, CGT_MDCR_TPM), SR_TRAP(SYS_PMINTENCLR_EL1, CGT_MDCR_TPM), SR_TRAP(SYS_PMMIR_EL1, CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(0), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(1), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(2), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(3), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(4), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(5), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(6), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(7), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(8), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(9), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(10), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(11), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(12), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(13), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(14), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(15), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(16), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(17), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(18), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(19), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(20), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(21), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(22), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(23), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(24), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(25), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(26), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(27), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(28), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(29), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVCNTRn_EL0(30), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(0), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(1), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(2), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(3), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(4), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(5), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(6), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(7), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(8), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(9), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(10), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(11), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(12), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(13), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(14), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(15), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(16), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(17), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(18), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(19), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(20), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(21), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(22), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(23), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(24), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(25), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(26), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(27), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(28), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(29), CGT_MDCR_TPM), - SR_TRAP(SYS_PMEVTYPERn_EL0(30), CGT_MDCR_TPM), + SR_TRAP(SYS_PMEVCNTRn_EL0(0), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(1), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(2), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(3), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(4), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(5), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(6), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(7), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(8), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(9), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(10), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(11), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(12), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(13), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(14), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(15), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(16), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(17), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(18), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(19), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(20), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(21), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(22), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(23), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(24), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(25), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(26), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(27), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(28), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(29), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVCNTRn_EL0(30), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(0), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(1), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(2), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(3), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(4), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(5), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(6), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(7), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(8), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(9), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(10), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(11), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(12), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(13), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(14), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(15), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(16), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(17), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(18), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(19), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(20), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(21), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(22), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(23), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(24), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(25), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(26), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(27), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(28), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(29), CGT_MDCR_TPM_HPMN), + SR_TRAP(SYS_PMEVTYPERn_EL0(30), CGT_MDCR_TPM_HPMN), SR_TRAP(SYS_PMCCFILTR_EL0, CGT_MDCR_TPM), SR_TRAP(SYS_MDCCSR_EL0, CGT_MDCR_TDCC_TDE_TDA), SR_TRAP(SYS_MDCCINT_EL1, CGT_MDCR_TDCC_TDE_TDA), diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index ac36c438b8c1..28f938f145ac 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -265,6 +265,24 @@ void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) irq_work_sync(&vcpu->arch.pmu.overflow_work); } =20 +bool kvm_pmu_counter_is_hyp(struct kvm_vcpu *vcpu, unsigned int idx) +{ + unsigned int hpmn; + + if (!vcpu_has_nv(vcpu) || idx =3D=3D ARMV8_PMU_CYCLE_IDX) + return false; + + /* + * Programming HPMN=3D0 is CONSTRAINED UNPREDICTABLE if FEAT_HPMN0 isn't + * implemented. Since KVM's ability to emulate HPMN=3D0 does not directly + * depend on hardware (all PMU registers are trapped), make the + * implementation choice that all counters are included in the second + * range reserved for EL2/EL3. + */ + hpmn =3D SYS_FIELD_GET(MDCR_EL2, HPMN, __vcpu_sys_reg(vcpu, MDCR_EL2)); + return idx >=3D hpmn; +} + u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu) { u64 val =3D FIELD_GET(ARMV8_PMU_PMCR_N, kvm_vcpu_read_pmcr(vcpu)); diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index e08aeec5d936..e6103df9ef5d 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -96,6 +96,7 @@ int kvm_arm_set_default_pmu(struct kvm *kvm); u8 kvm_arm_pmu_get_max_counters(struct kvm *kvm); =20 u64 kvm_vcpu_read_pmcr(struct kvm_vcpu *vcpu); +bool kvm_pmu_counter_is_hyp(struct kvm_vcpu *vcpu, unsigned int idx); #else struct kvm_pmu { }; @@ -187,6 +188,11 @@ static inline u64 kvm_vcpu_read_pmcr(struct kvm_vcpu *= vcpu) return 0; } =20 +static inline bool kvm_pmu_counter_is_hyp(struct kvm_vcpu *vcpu) +{ + return false; +} + #endif =20 #endif --=20 2.47.0.163.g1226f6d8fa-goog From nobody Mon Nov 25 14:41:09 2024 Received: from out-178.mta1.migadu.com (out-178.mta1.migadu.com [95.215.58.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F387F215C5E for ; Fri, 25 Oct 2024 18:24:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880674; cv=none; b=rPuDWfk2t6TzFVu3FXJI1WcAmsrwEzx3TrlHj0482k2KauWSBsjRmdVpg3vEPkNw9LJHIeUJCEx+cjkRfZxUX7dgIcbj/Ov9R7euFN1rWdjTbDPVEPILU9bYrn5k7xq7DANJfYQQ+TAfixST6DRVJq4Tdl3QFadT8BJ0pP1RRYA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880674; c=relaxed/simple; bh=Q7vBKgIbIND4zk/PaL6BpQwZYWCwg8LD8P5zBonajQU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oqQdl9pNP7PAuwxzi6/XkyHzXL31FvV3NAYAoiIMAOSgcFQC/6wYoxThMLdCmdlwKc/4urnNEPY7lL4UxuhwDlHVQkvxTLd9oS80VcHMFv/aLQdpt0aCrKkN16auoxiB9TtjjtGfYtfkGQVCmG42AU1K/88HQiAI8+9EAWg/PqM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=A4y2jPMP; arc=none smtp.client-ip=95.215.58.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="A4y2jPMP" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1729880671; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1Zy6kGgU90OTXWFjrU27ot0S1ZKtGk6pNy9r56UsKD0=; b=A4y2jPMPE4BmR7TzBqQJGkn0DYhVlj3aXzkH85lk5syb6tnnb3I9YfE0upgTkJycKdcsUt HiS5Mu4JobQdcE6BNtc4hFKCajIzc5Hfb33q4Loxpv9Wzpc4y5p7Ff1PHzFvx76rPVVTdW GTCsQzpR30nsm4olM5vTfbpCJhh60Qw= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Oliver Upton Subject: [PATCH v4 11/18] KVM: arm64: nv: Advertise support for FEAT_HPMN0 Date: Fri, 25 Oct 2024 18:23:46 +0000 Message-ID: <20241025182354.3364124-12-oliver.upton@linux.dev> In-Reply-To: <20241025182354.3364124-1-oliver.upton@linux.dev> References: <20241025182354.3364124-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Everything is in place now for KVM to actually handle MDCR_EL2.HPMN. Not only that, the emulation is capable of doing FEAT_HPMN0. Advertise support for the feature in the VM's ID registers. It is possible to emulate FEAT_HPMN0 on hardware that doesn't support it since KVM currently traps all PMU registers. Having said that, let's only advertise the feature on supporting hardware in case KVM ever provides 'direct' PMU support to VMs w/o involving host perf. Signed-off-by: Oliver Upton Reviewed-by: Marc Zyngier --- arch/arm64/kvm/nested.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c index d256a495a6ba..762f3ea8126d 100644 --- a/arch/arm64/kvm/nested.c +++ b/arch/arm64/kvm/nested.c @@ -892,12 +892,13 @@ static void limit_nv_id_regs(struct kvm *kvm) ID_AA64MMFR4_EL1_E2H0_NI_NV1); kvm_set_vm_id_reg(kvm, SYS_ID_AA64MMFR4_EL1, val); =20 - /* Only limited support for PMU, Debug, BPs and WPs */ + /* Only limited support for PMU, Debug, BPs, WPs, and HPMN0 */ val =3D kvm_read_vm_id_reg(kvm, SYS_ID_AA64DFR0_EL1); val &=3D (NV_FTR(DFR0, PMUVer) | NV_FTR(DFR0, WRPs) | NV_FTR(DFR0, BRPs) | - NV_FTR(DFR0, DebugVer)); + NV_FTR(DFR0, DebugVer) | + NV_FTR(DFR0, HPMN0)); =20 /* Cap Debug to ARMv8.1 */ tmp =3D FIELD_GET(NV_FTR(DFR0, DebugVer), val); --=20 2.47.0.163.g1226f6d8fa-goog From nobody Mon Nov 25 14:41:09 2024 Received: from out-188.mta1.migadu.com (out-188.mta1.migadu.com [95.215.58.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 238D3215C4F for ; Fri, 25 Oct 2024 18:24:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.188 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880677; cv=none; b=IzQoYUtYljbUdmvpYazVtCUvqE6hO3rjSH4hent2QrDiPtoFK4ToKBJXu+HPSgtvX7zdOG/MLVUdelE8TuUIXQvnkyZXlyds/ktCB6O989np41UCQESZZnwp+Rb0ZSp0OtvsuuaK3cW/0PfUU8Hl8mk1VAZcixYXR3vQ+r1K7mg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880677; c=relaxed/simple; bh=HwkrC5aYPyJueVAlEgE14kMiYROceJnsX/Qw7zWubvY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=C7BlrMg4J8UXuqaqNfKQbKSSg5gNqHdWb175Tw+TOrBo7jxJHIZ/1d4vb6oK3nGEasw9hnLvXCH8YwbmWlj9kc+qwo37c71QxfIwn5dr1JVbGis2vl9ViOukUduyBCSmuMula8o/ctK6RzSCrCZ2ql1q8MvSt0Avx5GshBJ972k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=VtQ3YKFg; arc=none smtp.client-ip=95.215.58.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="VtQ3YKFg" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1729880673; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xS0LNtsr13NpmIWzYUeUSq9N7nBweh4XNUS3GYHX4cw=; b=VtQ3YKFgXHUajBZz+dZotBgh3+GWO+WNGMC630H6ZIeq4kUc7UrLdRJ4T3JbWDrpiZ9o8J JJK8kKyIr8bj0P6U9nLHUBAiByt0JFXUzxRGSyvT3T4o/Wiy22J+63AJ5qItg4lA/HxNct EXb9KW4wxBpApx32kZKY5tYLG7ePMP0= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Oliver Upton Subject: [PATCH v4 12/18] KVM: arm64: Rename kvm_pmu_valid_counter_mask() Date: Fri, 25 Oct 2024 18:23:47 +0000 Message-ID: <20241025182354.3364124-13-oliver.upton@linux.dev> In-Reply-To: <20241025182354.3364124-1-oliver.upton@linux.dev> References: <20241025182354.3364124-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Nested PMU support requires dynamically changing the visible range of PMU counters based on the exception level and value of MDCR_EL2.HPMN. At the same time, the PMU emulation code needs to know the absolute number of implemented counters, regardless of context. Rename the existing helper to make it obvious that it returns the number of implemented counters and not anything else. Signed-off-by: Oliver Upton Reviewed-by: Marc Zyngier --- arch/arm64/kvm/pmu-emul.c | 8 ++++---- arch/arm64/kvm/sys_regs.c | 12 ++++++------ include/kvm/arm_pmu.h | 4 ++-- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 28f938f145ac..fd08c4b53be3 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -244,7 +244,7 @@ void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu) */ void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) { - unsigned long mask =3D kvm_pmu_valid_counter_mask(vcpu); + unsigned long mask =3D kvm_pmu_implemented_counter_mask(vcpu); int i; =20 for_each_set_bit(i, &mask, 32) @@ -283,7 +283,7 @@ bool kvm_pmu_counter_is_hyp(struct kvm_vcpu *vcpu, unsi= gned int idx) return idx >=3D hpmn; } =20 -u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu) +u64 kvm_pmu_implemented_counter_mask(struct kvm_vcpu *vcpu) { u64 val =3D FIELD_GET(ARMV8_PMU_PMCR_N, kvm_vcpu_read_pmcr(vcpu)); =20 @@ -592,7 +592,7 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0); =20 if (val & ARMV8_PMU_PMCR_P) { - unsigned long mask =3D kvm_pmu_valid_counter_mask(vcpu); + unsigned long mask =3D kvm_pmu_implemented_counter_mask(vcpu); mask &=3D ~BIT(ARMV8_PMU_CYCLE_IDX); for_each_set_bit(i, &mask, 32) kvm_pmu_set_pmc_value(kvm_vcpu_idx_to_pmc(vcpu, i), 0, true); @@ -822,7 +822,7 @@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmce= id1) =20 void kvm_vcpu_reload_pmu(struct kvm_vcpu *vcpu) { - u64 mask =3D kvm_pmu_valid_counter_mask(vcpu); + u64 mask =3D kvm_pmu_implemented_counter_mask(vcpu); =20 kvm_pmu_handle_pmcr(vcpu, kvm_vcpu_read_pmcr(vcpu)); =20 diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 30fe940cd5bd..bd0c116f041b 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1131,7 +1131,7 @@ static int set_pmreg(struct kvm_vcpu *vcpu, const str= uct sys_reg_desc *r, u64 va { bool set; =20 - val &=3D kvm_pmu_valid_counter_mask(vcpu); + val &=3D kvm_pmu_implemented_counter_mask(vcpu); =20 switch (r->reg) { case PMOVSSET_EL0: @@ -1154,7 +1154,7 @@ static int set_pmreg(struct kvm_vcpu *vcpu, const str= uct sys_reg_desc *r, u64 va =20 static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, = u64 *val) { - u64 mask =3D kvm_pmu_valid_counter_mask(vcpu); + u64 mask =3D kvm_pmu_implemented_counter_mask(vcpu); =20 *val =3D __vcpu_sys_reg(vcpu, r->reg) & mask; return 0; @@ -1168,7 +1168,7 @@ static bool access_pmcnten(struct kvm_vcpu *vcpu, str= uct sys_reg_params *p, if (pmu_access_el0_disabled(vcpu)) return false; =20 - mask =3D kvm_pmu_valid_counter_mask(vcpu); + mask =3D kvm_pmu_implemented_counter_mask(vcpu); if (p->is_write) { val =3D p->regval & mask; if (r->Op2 & 0x1) { @@ -1191,7 +1191,7 @@ static bool access_pmcnten(struct kvm_vcpu *vcpu, str= uct sys_reg_params *p, static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { - u64 mask =3D kvm_pmu_valid_counter_mask(vcpu); + u64 mask =3D kvm_pmu_implemented_counter_mask(vcpu); =20 if (check_pmu_access_disabled(vcpu, 0)) return false; @@ -1215,7 +1215,7 @@ static bool access_pminten(struct kvm_vcpu *vcpu, str= uct sys_reg_params *p, static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { - u64 mask =3D kvm_pmu_valid_counter_mask(vcpu); + u64 mask =3D kvm_pmu_implemented_counter_mask(vcpu); =20 if (pmu_access_el0_disabled(vcpu)) return false; @@ -1245,7 +1245,7 @@ static bool access_pmswinc(struct kvm_vcpu *vcpu, str= uct sys_reg_params *p, if (pmu_write_swinc_el0_disabled(vcpu)) return false; =20 - mask =3D kvm_pmu_valid_counter_mask(vcpu); + mask =3D kvm_pmu_implemented_counter_mask(vcpu); kvm_pmu_software_increment(vcpu, p->regval & mask); return true; } diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index e6103df9ef5d..b175b10491f0 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -47,7 +47,7 @@ static __always_inline bool kvm_arm_support_pmu_v3(void) #define kvm_arm_pmu_irq_initialized(v) ((v)->arch.pmu.irq_num >=3D VGIC_NR= _SGIS) u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx); void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 = val); -u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu); +u64 kvm_pmu_implemented_counter_mask(struct kvm_vcpu *vcpu); u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1); void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu); void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu); @@ -114,7 +114,7 @@ static inline u64 kvm_pmu_get_counter_value(struct kvm_= vcpu *vcpu, } static inline void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val) {} -static inline u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu) +static inline u64 kvm_pmu_implemented_counter_mask(struct kvm_vcpu *vcpu) { return 0; } --=20 2.47.0.163.g1226f6d8fa-goog From nobody Mon Nov 25 14:41:09 2024 Received: from out-177.mta1.migadu.com (out-177.mta1.migadu.com [95.215.58.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A6512161EB for ; Fri, 25 Oct 2024 18:24:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1729880675; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HQbPfXcKqguf2CSntuN0/NMKRu/M0rQKlM/2rK1MGZk=; b=AHPoUC9fdpWn9L1Z6PNl/PyiY2zsU/YeEPLLX12r1jXZ1Pon2gkoHeUmaHyYYpLeys3q1/ uVFUNZWFZo0ZyV/3krAe8WdZqr23+kLc8HHxsPY6WNJDKGSbW7d2RsK/oJ6Mj+XSqAqoiE XaxW+2OMkQOMkhtqf7gxZIIVXqWMmLU= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Oliver Upton Subject: [PATCH v4 13/18] KVM: arm64: nv: Adjust range of accessible PMCs according to HPMN Date: Fri, 25 Oct 2024 18:23:48 +0000 Message-ID: <20241025182354.3364124-14-oliver.upton@linux.dev> In-Reply-To: <20241025182354.3364124-1-oliver.upton@linux.dev> References: <20241025182354.3364124-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" The value of MDCR_EL2.HPMN controls the number of event counters made visible to EL0 and EL1. This means it is possible for the guest hypervisor to allow direct access to event counters to the L2. Rework KVM's PMU register emulation to take the effects of HPMN into account when handling a trap. For bitmask-style registers, writes only affect accessible registers. Signed-off-by: Oliver Upton Reviewed-by: Marc Zyngier --- arch/arm64/kvm/pmu-emul.c | 14 +++++++++++++- arch/arm64/kvm/sys_regs.c | 12 ++++++------ include/kvm/arm_pmu.h | 5 +++++ 3 files changed, 24 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index fd08c4b53be3..0d669fb84485 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -283,6 +283,18 @@ bool kvm_pmu_counter_is_hyp(struct kvm_vcpu *vcpu, uns= igned int idx) return idx >=3D hpmn; } =20 +u64 kvm_pmu_accessible_counter_mask(struct kvm_vcpu *vcpu) +{ + u64 mask =3D kvm_pmu_implemented_counter_mask(vcpu); + u64 hpmn; + + if (!vcpu_has_nv(vcpu) || vcpu_is_el2(vcpu)) + return mask; + + hpmn =3D SYS_FIELD_GET(MDCR_EL2, HPMN, __vcpu_sys_reg(vcpu, MDCR_EL2)); + return mask & ~GENMASK(vcpu->kvm->arch.pmcr_n - 1, hpmn); +} + u64 kvm_pmu_implemented_counter_mask(struct kvm_vcpu *vcpu) { u64 val =3D FIELD_GET(ARMV8_PMU_PMCR_N, kvm_vcpu_read_pmcr(vcpu)); @@ -592,7 +604,7 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0); =20 if (val & ARMV8_PMU_PMCR_P) { - unsigned long mask =3D kvm_pmu_implemented_counter_mask(vcpu); + unsigned long mask =3D kvm_pmu_accessible_counter_mask(vcpu); mask &=3D ~BIT(ARMV8_PMU_CYCLE_IDX); for_each_set_bit(i, &mask, 32) kvm_pmu_set_pmc_value(kvm_vcpu_idx_to_pmc(vcpu, i), 0, true); diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index bd0c116f041b..8c226ec8bc25 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1131,7 +1131,7 @@ static int set_pmreg(struct kvm_vcpu *vcpu, const str= uct sys_reg_desc *r, u64 va { bool set; =20 - val &=3D kvm_pmu_implemented_counter_mask(vcpu); + val &=3D kvm_pmu_accessible_counter_mask(vcpu); =20 switch (r->reg) { case PMOVSSET_EL0: @@ -1154,7 +1154,7 @@ static int set_pmreg(struct kvm_vcpu *vcpu, const str= uct sys_reg_desc *r, u64 va =20 static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, = u64 *val) { - u64 mask =3D kvm_pmu_implemented_counter_mask(vcpu); + u64 mask =3D kvm_pmu_accessible_counter_mask(vcpu); =20 *val =3D __vcpu_sys_reg(vcpu, r->reg) & mask; return 0; @@ -1168,7 +1168,7 @@ static bool access_pmcnten(struct kvm_vcpu *vcpu, str= uct sys_reg_params *p, if (pmu_access_el0_disabled(vcpu)) return false; =20 - mask =3D kvm_pmu_implemented_counter_mask(vcpu); + mask =3D kvm_pmu_accessible_counter_mask(vcpu); if (p->is_write) { val =3D p->regval & mask; if (r->Op2 & 0x1) { @@ -1191,7 +1191,7 @@ static bool access_pmcnten(struct kvm_vcpu *vcpu, str= uct sys_reg_params *p, static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { - u64 mask =3D kvm_pmu_implemented_counter_mask(vcpu); + u64 mask =3D kvm_pmu_accessible_counter_mask(vcpu); =20 if (check_pmu_access_disabled(vcpu, 0)) return false; @@ -1215,7 +1215,7 @@ static bool access_pminten(struct kvm_vcpu *vcpu, str= uct sys_reg_params *p, static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { - u64 mask =3D kvm_pmu_implemented_counter_mask(vcpu); + u64 mask =3D kvm_pmu_accessible_counter_mask(vcpu); =20 if (pmu_access_el0_disabled(vcpu)) return false; @@ -1245,7 +1245,7 @@ static bool access_pmswinc(struct kvm_vcpu *vcpu, str= uct sys_reg_params *p, if (pmu_write_swinc_el0_disabled(vcpu)) return false; =20 - mask =3D kvm_pmu_implemented_counter_mask(vcpu); + mask =3D kvm_pmu_accessible_counter_mask(vcpu); kvm_pmu_software_increment(vcpu, p->regval & mask); return true; } diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index b175b10491f0..b738ffb39bb0 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -48,6 +48,7 @@ static __always_inline bool kvm_arm_support_pmu_v3(void) u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx); void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 = val); u64 kvm_pmu_implemented_counter_mask(struct kvm_vcpu *vcpu); +u64 kvm_pmu_accessible_counter_mask(struct kvm_vcpu *vcpu); u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1); void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu); void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu); @@ -118,6 +119,10 @@ static inline u64 kvm_pmu_implemented_counter_mask(str= uct kvm_vcpu *vcpu) { return 0; } +static inline u64 kvm_pmu_accessible_counter_mask(struct kvm_vcpu *vcpu) +{ + return 0; +} static inline void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu) {} static inline void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {} static inline void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {} --=20 2.47.0.163.g1226f6d8fa-goog From nobody Mon Nov 25 14:41:09 2024 Received: from out-188.mta1.migadu.com (out-188.mta1.migadu.com [95.215.58.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A22F2216200 for ; Fri, 25 Oct 2024 18:24:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.188 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880681; cv=none; b=GO1bSYwJiWNq8mzP8VOfYiZsOOkXV3M9yEgnPw9Z9uFb1QzsutYeokFF2yR74qTfM1hWo6KFaRPMLEBdL0xHdkPgTxpGmv5mu3qFaw+hP+QVqOPqj07fqI4RziBNYxDV0lgW6J/fnbDR7LmbNQLT/uOZ+3hBJbOZ/kXR1vamlhQ= ARC-Message-Signature: i=1; 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DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1729880678; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lWJEQN56N/CeKfveDMMoJU65zML9g/eXZiwy9Gw5WvI=; b=ejB6tZgterLk/gbHmBLxWNnprsUUwqRnXUpyPbf/SYm1C0qPn8Ks1SwIKU9WW/VEyoim94 aWHL5eKiXMOYI7r2KQkQMiicqSsdEFqd6VX9jp6RVhi5O44qT3bKU3KS7jbpcEAB4TrLkw SLgGU+sYMsYhnSYtXBegEs5nN8IENs0= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Oliver Upton Subject: [PATCH v4 14/18] KVM: arm64: Add helpers to determine if PMC counts at a given EL Date: Fri, 25 Oct 2024 18:23:49 +0000 Message-ID: <20241025182354.3364124-15-oliver.upton@linux.dev> In-Reply-To: <20241025182354.3364124-1-oliver.upton@linux.dev> References: <20241025182354.3364124-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Checking the exception level filters for a PMC is a minor annoyance to open code. Add helpers to check if an event counts at EL0 and EL1, which will prove useful in a subsequent change. Signed-off-by: Oliver Upton Reviewed-by: Marc Zyngier --- arch/arm64/kvm/pmu-emul.c | 40 +++++++++++++++++++++++++++------------ 1 file changed, 28 insertions(+), 12 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 0d669fb84485..03cd1ad7a55a 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -111,6 +111,11 @@ static u32 counter_index_to_evtreg(u64 idx) return (idx =3D=3D ARMV8_PMU_CYCLE_IDX) ? PMCCFILTR_EL0 : PMEVTYPER0_EL0 = + idx; } =20 +static u64 kvm_pmc_read_evtreg(const struct kvm_pmc *pmc) +{ + return __vcpu_sys_reg(kvm_pmc_to_vcpu(pmc), counter_index_to_evtreg(pmc->= idx)); +} + static u64 kvm_pmu_get_pmc_value(struct kvm_pmc *pmc) { struct kvm_vcpu *vcpu =3D kvm_pmc_to_vcpu(pmc); @@ -619,6 +624,24 @@ static bool kvm_pmu_counter_is_enabled(struct kvm_pmc = *pmc) (__vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & BIT(pmc->idx)); } =20 +static bool kvm_pmc_counts_at_el0(struct kvm_pmc *pmc) +{ + u64 evtreg =3D kvm_pmc_read_evtreg(pmc); + bool nsu =3D evtreg & ARMV8_PMU_EXCLUDE_NS_EL0; + bool u =3D evtreg & ARMV8_PMU_EXCLUDE_EL0; + + return u =3D=3D nsu; +} + +static bool kvm_pmc_counts_at_el1(struct kvm_pmc *pmc) +{ + u64 evtreg =3D kvm_pmc_read_evtreg(pmc); + bool nsk =3D evtreg & ARMV8_PMU_EXCLUDE_NS_EL1; + bool p =3D evtreg & ARMV8_PMU_EXCLUDE_EL1; + + return p =3D=3D nsk; +} + /** * kvm_pmu_create_perf_event - create a perf event for a counter * @pmc: Counter context @@ -629,17 +652,15 @@ static void kvm_pmu_create_perf_event(struct kvm_pmc = *pmc) struct arm_pmu *arm_pmu =3D vcpu->kvm->arch.arm_pmu; struct perf_event *event; struct perf_event_attr attr; - u64 eventsel, reg, data; - bool p, u, nsk, nsu; + u64 eventsel, evtreg; =20 - reg =3D counter_index_to_evtreg(pmc->idx); - data =3D __vcpu_sys_reg(vcpu, reg); + evtreg =3D kvm_pmc_read_evtreg(pmc); =20 kvm_pmu_stop_counter(pmc); if (pmc->idx =3D=3D ARMV8_PMU_CYCLE_IDX) eventsel =3D ARMV8_PMUV3_PERFCTR_CPU_CYCLES; else - eventsel =3D data & kvm_pmu_event_mask(vcpu->kvm); + eventsel =3D evtreg & kvm_pmu_event_mask(vcpu->kvm); =20 /* * Neither SW increment nor chained events need to be backed @@ -657,18 +678,13 @@ static void kvm_pmu_create_perf_event(struct kvm_pmc = *pmc) !test_bit(eventsel, vcpu->kvm->arch.pmu_filter)) return; =20 - p =3D data & ARMV8_PMU_EXCLUDE_EL1; - u =3D data & ARMV8_PMU_EXCLUDE_EL0; - nsk =3D data & ARMV8_PMU_EXCLUDE_NS_EL1; - nsu =3D data & ARMV8_PMU_EXCLUDE_NS_EL0; - memset(&attr, 0, sizeof(struct perf_event_attr)); attr.type =3D arm_pmu->pmu.type; attr.size =3D sizeof(attr); attr.pinned =3D 1; attr.disabled =3D !kvm_pmu_counter_is_enabled(pmc); - attr.exclude_user =3D (u !=3D nsu); - attr.exclude_kernel =3D (p !=3D nsk); + attr.exclude_user =3D !kvm_pmc_counts_at_el0(pmc); + attr.exclude_kernel =3D !kvm_pmc_counts_at_el1(pmc); attr.exclude_hv =3D 1; /* Don't count EL2 events */ attr.exclude_host =3D 1; /* Don't count host events */ attr.config =3D eventsel; --=20 2.47.0.163.g1226f6d8fa-goog From nobody Mon Nov 25 14:41:09 2024 Received: from out-179.mta1.migadu.com (out-179.mta1.migadu.com [95.215.58.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1113E216DE1 for ; Fri, 25 Oct 2024 18:24:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880684; cv=none; b=sxynEGTTT5wVVrBSQxp/1pml0EN8FlkwoaSiIxkFIB3MjN8B2BvvliqZMDUZxyKvEoCrQ4NaIk096YKuAASHV4XzW15BZiV0Iw1F5z+r/claFa5j8rg0074OAa0i46TzaKDDX1IKSL4yermhFMjVLkK5Mf7MXTHGJ/qJDaCphQY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880684; c=relaxed/simple; bh=HOnseCa4w27iSy+w9y5fRHyXmlUTzPh/7iSZeSnZbhs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IPfd0PWnEv3P+Y5/5kGafAHgoyocs/nycyxSq9aHhgSt8vNBgqnVks9gt7Bg88aKdGhAC89iUJgy+yhkmWE2whg2IeDfcPDPJzJNwjfOqydQmcOw5qQNKTqNkC1oZpQxhBCu0yP7IZ8xmt5AMdqKRb+WAhBHkzn/xAPLtrHFz2A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=mpQyf5fd; arc=none smtp.client-ip=95.215.58.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="mpQyf5fd" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1729880680; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZrYN5raZtmWI3hPp7h1MaTZOJ1/CQmOwVJXTIAsdSvU=; b=mpQyf5fdkDWX8vMbgGH7PlXuYSF8BTzvlYcX6H0p4IGeZ/kEntusuo+rmuplKHsnkDsTKY uD0mK395NR1Pxp3tAQUPu8QC+gmRXi9jHuqH4f6XLrY0hWpEN4a6GHX6XS80Hyg4l5hedH 8oOuJ78UyWpHzLqYlenhequjjM5IUZM= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Oliver Upton Subject: [PATCH v4 15/18] KVM: arm64: nv: Honor MDCR_EL2.HPME Date: Fri, 25 Oct 2024 18:23:50 +0000 Message-ID: <20241025182354.3364124-16-oliver.upton@linux.dev> In-Reply-To: <20241025182354.3364124-1-oliver.upton@linux.dev> References: <20241025182354.3364124-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" When the PMU is configured with split counter ranges, HPME becomes the enable bit for the counters reserved for EL2. Signed-off-by: Oliver Upton Reviewed-by: Marc Zyngier --- arch/arm64/kvm/pmu-emul.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 03cd1ad7a55a..349886f03fd5 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -620,8 +620,15 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 va= l) static bool kvm_pmu_counter_is_enabled(struct kvm_pmc *pmc) { struct kvm_vcpu *vcpu =3D kvm_pmc_to_vcpu(pmc); - return (kvm_vcpu_read_pmcr(vcpu) & ARMV8_PMU_PMCR_E) && - (__vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & BIT(pmc->idx)); + unsigned int mdcr =3D __vcpu_sys_reg(vcpu, MDCR_EL2); + + if (!(__vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & BIT(pmc->idx))) + return false; + + if (kvm_pmu_counter_is_hyp(vcpu, pmc->idx)) + return mdcr & MDCR_EL2_HPME; + + return kvm_vcpu_read_pmcr(vcpu) & ARMV8_PMU_PMCR_E; } =20 static bool kvm_pmc_counts_at_el0(struct kvm_pmc *pmc) --=20 2.47.0.163.g1226f6d8fa-goog From nobody Mon Nov 25 14:41:09 2024 Received: from out-179.mta1.migadu.com (out-179.mta1.migadu.com [95.215.58.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FAEF216E04 for ; Fri, 25 Oct 2024 18:24:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880686; cv=none; b=mFez0KRZDl+u7cZKZnK5oaMM8SXD7z5Kba5pnaiUO0ovN1VsWaxfY/j+1bOqZFrrwKnn6pozTkS+cSSSXwziTzwp6L8wRtqAuo1wl/sRGDdeVM2RL86VkOWyeR4tLTUOcx6o4LU9idvfEWt/wU5Yl73W/4Ld+iol+tjwNSHimu4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880686; c=relaxed/simple; bh=WYsNVCFGAHBmLIR5ZwVMA7UgwETHZyDsk9g7TP4BdGQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kVetqVw1h9T+FE66k2U/eY8czok4Yrkdgz3iyIBc3vEcz/AtNLOceDCXW8r9g2pG99fGcOnCvdC+H9kVh+QU1f1vG/abGAPbSqRAX9EaFZ2TNIf+PPdoDaOddVaeTl2e2y35k8w77/1icrK6eYbiEsEZ/1G+lx9U3jLh6cHryZc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=TcH6DeFL; arc=none smtp.client-ip=95.215.58.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="TcH6DeFL" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1729880682; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Owyw17gWiY/wAB+tVVFDbqz1mQh4LseuhIiRcAFPnCo=; b=TcH6DeFLIlJxfOvvh2g2c8lQNf63nJ1xNdujBUnCnhFJANWPjwhf3LJFZXDluQntM4Rk/H PcB85ZdAIMr3VD+fyZQM715VWN6peLMTHM4T1xAhsUp1C4wNOEBsq1aqR4LN5QWB26C5bR vHfvYTYR28NWFj03/2ihe3LkPxPapCY= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Oliver Upton Subject: [PATCH v4 16/18] KVM: arm64: nv: Honor MDCR_EL2.HLP Date: Fri, 25 Oct 2024 18:23:51 +0000 Message-ID: <20241025182354.3364124-17-oliver.upton@linux.dev> In-Reply-To: <20241025182354.3364124-1-oliver.upton@linux.dev> References: <20241025182354.3364124-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Counters that fall in the hypervisor range (i.e. N >=3D HPMN) have a separate control for enabling 64 bit overflow. Take it into account. Signed-off-by: Oliver Upton Reviewed-by: Marc Zyngier --- arch/arm64/kvm/pmu-emul.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 349886f03fd5..1e9cdbc235a8 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -89,7 +89,11 @@ static bool kvm_pmc_is_64bit(struct kvm_pmc *pmc) =20 static bool kvm_pmc_has_64bit_overflow(struct kvm_pmc *pmc) { - u64 val =3D kvm_vcpu_read_pmcr(kvm_pmc_to_vcpu(pmc)); + struct kvm_vcpu *vcpu =3D kvm_pmc_to_vcpu(pmc); + u64 val =3D kvm_vcpu_read_pmcr(vcpu); + + if (kvm_pmu_counter_is_hyp(vcpu, pmc->idx)) + return __vcpu_sys_reg(vcpu, MDCR_EL2) & MDCR_EL2_HLP; =20 return (pmc->idx < ARMV8_PMU_CYCLE_IDX && (val & ARMV8_PMU_PMCR_LP)) || (pmc->idx =3D=3D ARMV8_PMU_CYCLE_IDX && (val & ARMV8_PMU_PMCR_LC)); --=20 2.47.0.163.g1226f6d8fa-goog From nobody Mon Nov 25 14:41:09 2024 Received: from out-186.mta1.migadu.com (out-186.mta1.migadu.com [95.215.58.186]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92713216E1E for ; Fri, 25 Oct 2024 18:24:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.186 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880688; cv=none; b=EJvjuc6ThC+3e0eR1cmabX4tcWxfbyv0sBjQwr+BYB6PvA1CL462twe+lbnFU0yAsWIxaDVKlHpEwJwzB5u+gI6sLvi9BQLQBXzmoLVbT2vDfyqivSMQVLmPbf0aFYJrvkpqt/Fx4MAMI+zcFxNOY3O3Iip57DImhuVhN19FSBo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880688; c=relaxed/simple; bh=hfE2jrLI8Wub6PeIsfHPmMzyzyRjeYZOW47T7BeWD+Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PivowFKqaYk2H9xOsLjvwFbt/uq4cX98s663Hy7N6u1svInN76gCqdNmuhE8eH+y+zlerdiUA2lzzpGZBk48eQ6ZHs6NdFxX3YmvO9IAV64pYA0MfZXyEOTY8fqseAnfhL51rLWCktgFqJ+GUXUdiAveS21E4MmF1updu/M9ffM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=tzsa6SIp; arc=none smtp.client-ip=95.215.58.186 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="tzsa6SIp" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1729880684; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=O7f8WlbTuKg/9ktNP6L6Uj0B1bwQ9caDZTgl7idjk1c=; b=tzsa6SIpMG2GGdxlZz43xIRwLBzOu3M1d3lUZt7g+JKNgpiibDr3Zh11gbQ2IVr/R+jZcw BmNMehCrxb69CuK+1R3Mko9Lg0pBjDBUk/9/BfquiDSI1oA/Tt8wlh2fuQVa5Wcu+WEWUS LwSl11kGz29JVI1HwUt5VXIwfSUcJgc= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Oliver Upton Subject: [PATCH v4 17/18] KVM: arm64: nv: Apply EL2 event filtering when in hyp context Date: Fri, 25 Oct 2024 18:23:52 +0000 Message-ID: <20241025182354.3364124-18-oliver.upton@linux.dev> In-Reply-To: <20241025182354.3364124-1-oliver.upton@linux.dev> References: <20241025182354.3364124-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" It hopefully comes as no surprise when I say that vEL2 actually runs at EL1. So, the guest hypervisor's EL2 event filter (NSH) needs to actually be applied to EL1 in the perf event. In addition to this, the disable bit for the guest counter range (HPMD) needs to have the effect of stopping the affected counters. Do exactly that by stuffing ::exclude_kernel with the combined effect of these controls. This isn't quite enough yet, as the backing perf events need to be reprogrammed upon nested ERET/exception entry to remap the effective filter onto ::exclude_kernel. Signed-off-by: Oliver Upton Reviewed-by: Marc Zyngier --- arch/arm64/kvm/pmu-emul.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 1e9cdbc235a8..e2eb2ba903b6 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -653,6 +653,17 @@ static bool kvm_pmc_counts_at_el1(struct kvm_pmc *pmc) return p =3D=3D nsk; } =20 +static bool kvm_pmc_counts_at_el2(struct kvm_pmc *pmc) +{ + struct kvm_vcpu *vcpu =3D kvm_pmc_to_vcpu(pmc); + u64 mdcr =3D __vcpu_sys_reg(vcpu, MDCR_EL2); + + if (!kvm_pmu_counter_is_hyp(vcpu, pmc->idx) && (mdcr & MDCR_EL2_HPMD)) + return false; + + return kvm_pmc_read_evtreg(pmc) & ARMV8_PMU_INCLUDE_EL2; +} + /** * kvm_pmu_create_perf_event - create a perf event for a counter * @pmc: Counter context @@ -695,11 +706,19 @@ static void kvm_pmu_create_perf_event(struct kvm_pmc = *pmc) attr.pinned =3D 1; attr.disabled =3D !kvm_pmu_counter_is_enabled(pmc); attr.exclude_user =3D !kvm_pmc_counts_at_el0(pmc); - attr.exclude_kernel =3D !kvm_pmc_counts_at_el1(pmc); attr.exclude_hv =3D 1; /* Don't count EL2 events */ attr.exclude_host =3D 1; /* Don't count host events */ attr.config =3D eventsel; =20 + /* + * Filter events at EL1 (i.e. vEL2) when in a hyp context based on the + * guest's EL2 filter. + */ + if (unlikely(is_hyp_ctxt(vcpu))) + attr.exclude_kernel =3D !kvm_pmc_counts_at_el2(pmc); + else + attr.exclude_kernel =3D !kvm_pmc_counts_at_el1(pmc); + /* * If counting with a 64bit counter, advertise it to the perf * code, carefully dealing with the initial sample period --=20 2.47.0.163.g1226f6d8fa-goog From nobody Mon Nov 25 14:41:09 2024 Received: from out-176.mta0.migadu.com (out-176.mta0.migadu.com [91.218.175.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16F597E792 for ; Fri, 25 Oct 2024 18:26:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880780; cv=none; b=OqGRzbbD5Scum0DLmQbWTLp4mRFNSBtmiqna2BSmjQCB58GbzMlu+nFbcX5oqNy7JZeGQtKdN+1osRHJaE9vlaeyyQra/uqZEBin/JYu01QnXU9Zro0BDXahEogevo2SkM/Ngp/BPqtdGhVkmut0GSJxkJBy0rMvZs8zhiulvRk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729880780; c=relaxed/simple; bh=L3oGte36E8/WUy+2jcHza7W302Rv5g0bNl3hB7ChqGs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IkE1NzMycDRvYwAvRWl3NGOkPg3sRjjhFDxEgckBbo37ZT1YpobL621E2rsrJyL839cOffOZ/jIC8FVEXJf9ZnA9FrmHaPI2lYRiXYsU4nOy5BaTRWaFJZkcEDUo+W3bIrGCJlkzy5SlPVG0/VbvrSzSQTqUAwdPWGtx1JO0o/M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=sKKAL2ku; arc=none smtp.client-ip=91.218.175.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="sKKAL2ku" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1729880775; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LYhcSWnuETsKJCEEluaZaBpAtwyQ/oGuJY+fGvbLS3M=; b=sKKAL2kuSWB2ST+WvVrSAu8UQYyNF6eTlL7xxdGWEFYBcw3OV/VgQBOvr8uupq5kztJWX4 DY4cNvMnRVw2JGcNDqmW+4aSYGXCGvw/FzxnBF/P/TyfjCgazgfT2llXkDp3QG1Ws4T6Bc fQVLKswN7mMxlyPPKA4vnfbXTZiJGmw= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Oliver Upton Subject: [PATCH v4 18/18] KVM: arm64: nv: Reprogram PMU events affected by nested transition Date: Fri, 25 Oct 2024 18:25:59 +0000 Message-ID: <20241025182559.3364829-1-oliver.upton@linux.dev> In-Reply-To: <20241025182354.3364124-1-oliver.upton@linux.dev> References: <20241025182354.3364124-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Start reprogramming PMU events at nested boundaries now that everything is in place to handle the EL2 event filter. Only repaint events where the filter differs between EL1 and EL2 as a slight optimization. PMU now 'works' for nested VMs, albeit slow. Signed-off-by: Oliver Upton Reviewed-by: Marc Zyngier --- arch/arm64/kvm/emulate-nested.c | 4 ++++ arch/arm64/kvm/pmu-emul.c | 29 +++++++++++++++++++++++++++++ include/kvm/arm_pmu.h | 3 +++ 3 files changed, 36 insertions(+) diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-neste= d.c index 162bddbfbe79..13f0be0911e8 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -2450,6 +2450,8 @@ void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu) =20 kvm_arch_vcpu_load(vcpu, smp_processor_id()); preempt_enable(); + + kvm_pmu_nested_transition(vcpu); } =20 static void kvm_inject_el2_exception(struct kvm_vcpu *vcpu, u64 esr_el2, @@ -2532,6 +2534,8 @@ static int kvm_inject_nested(struct kvm_vcpu *vcpu, u= 64 esr_el2, kvm_arch_vcpu_load(vcpu, smp_processor_id()); preempt_enable(); =20 + kvm_pmu_nested_transition(vcpu); + return 1; } =20 diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index e2eb2ba903b6..8ad62284fa23 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -1215,3 +1215,32 @@ u64 kvm_vcpu_read_pmcr(struct kvm_vcpu *vcpu) =20 return u64_replace_bits(pmcr, vcpu->kvm->arch.pmcr_n, ARMV8_PMU_PMCR_N); } + +void kvm_pmu_nested_transition(struct kvm_vcpu *vcpu) +{ + bool reprogrammed =3D false; + unsigned long mask; + int i; + + if (!kvm_vcpu_has_pmu(vcpu)) + return; + + mask =3D __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); + for_each_set_bit(i, &mask, 32) { + struct kvm_pmc *pmc =3D kvm_vcpu_idx_to_pmc(vcpu, i); + + /* + * We only need to reconfigure events where the filter is + * different at EL1 vs. EL2, as we're multiplexing the true EL1 + * event filter bit for nested. + */ + if (kvm_pmc_counts_at_el1(pmc) =3D=3D kvm_pmc_counts_at_el2(pmc)) + continue; + + kvm_pmu_create_perf_event(pmc); + reprogrammed =3D true; + } + + if (reprogrammed) + kvm_vcpu_pmu_restore_guest(vcpu); +} diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index b738ffb39bb0..3493e9d9f58e 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -98,6 +98,7 @@ u8 kvm_arm_pmu_get_max_counters(struct kvm *kvm); =20 u64 kvm_vcpu_read_pmcr(struct kvm_vcpu *vcpu); bool kvm_pmu_counter_is_hyp(struct kvm_vcpu *vcpu, unsigned int idx); +void kvm_pmu_nested_transition(struct kvm_vcpu *vcpu); #else struct kvm_pmu { }; @@ -198,6 +199,8 @@ static inline bool kvm_pmu_counter_is_hyp(struct kvm_vc= pu *vcpu) return false; } =20 +static inline void kvm_pmu_nested_transition(struct kvm_vcpu *vcpu) {} + #endif =20 #endif --=20 2.47.0.163.g1226f6d8fa-goog