From nobody Mon Nov 25 17:25:10 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 522AB208234; Fri, 25 Oct 2024 14:30:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729866656; cv=none; b=Xdpm+nILQIqyIMy+niTB5mWfr5lN9lBwVWR+MoAqYFKDF2TQO0xgCc+IAk2P0FQu9OWydFjRiTuKShk9MLFEJ5u5B//NDF8OKlakZauUkFXfYWMcfbiwAF26YpqZ7O7ypnvDRfBvyRLYzRl6Z3bJhDczNrFyPElSEBtH83wH3Ys= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729866656; c=relaxed/simple; bh=uRdY02G16xee66yZv3V9LaXcJX6pSUexpS2ItdhLEno=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=r64GsoymYNn/9PfDk2bEEqQ7WAWpCu9ugSS4tonRuZpde7idrKKLncc1dIeuZ0fC8+6ifbLyqdvEElGq4pZTYHJz/Jh6SdBJatoQZBdDfm73s6oQn9T/kUIDr8W8sml1BrJ8Ji1jVOhme5mSnqhmfz+qQfV5waOwnfPO+8j9Y2Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 68830497; Fri, 25 Oct 2024 07:31:23 -0700 (PDT) Received: from VDW30FN91H.arm.com (unknown [10.57.79.117]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 632793F73B; Fri, 25 Oct 2024 07:30:51 -0700 (PDT) From: Graham Woodward To: acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com, jolsa@kernel.org, irogers@google.com, james.clark@linaro.org, mike.leach@linaro.org, leo.yan@linux.dev, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: nd@arm.com, Graham Woodward Subject: [PATCH v1 1/4] perf arm-spe: Set sample.addr to target address for instruction sample Date: Fri, 25 Oct 2024 15:30:06 +0100 Message-Id: <20241025143009.25419-2-graham.woodward@arm.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241025143009.25419-1-graham.woodward@arm.com> References: <20241025143009.25419-1-graham.woodward@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For an instruction sample, assign the target address to the field 'to_ip'. If it is a non-branch record, to_ip will be 0, presenting a non-valid target address. Signed-off-by: Graham Woodward Reviewed-by: James Clark Tested-by: Leo Yan --- tools/perf/util/arm-spe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 856cc36f33d7..49b763807360 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -418,7 +418,7 @@ static int arm_spe__synth_instruction_sample(struct arm= _spe_queue *speq, =20 sample.id =3D spe_events_id; sample.stream_id =3D spe_events_id; - sample.addr =3D record->virt_addr; + sample.addr =3D record->to_ip; sample.phys_addr =3D record->phys_addr; sample.data_src =3D data_src; sample.period =3D spe->instructions_sample_period; --=20 2.40.1 From nobody Mon Nov 25 17:25:10 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BD3BC20BB4D; Fri, 25 Oct 2024 14:30:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729866658; cv=none; b=RfvGjwHTqlBRz2ZoXLiC9cP5Cr8TFRSlRqh6HVCsN43cDWin/LIMt0ektDQiCzPy+1ReJaNlSDH+6C3fiUVu6N/xv+pBBA8JETwNvWe5Mp/OpBGNRGBQ4s3kR9EMd7yHIJSVx4m3den26I3gk9m2a7f5R2rR8uQFhRow/lCjUhY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729866658; c=relaxed/simple; bh=+m1Fd6DkkUo2YpyeBWMJx86vmQUvxg9ZMGY1A/hh8zo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fhdVkvMMT2XeOf5MpeyL3bB+8M1bMMikPDhZSluLEfA5uD7b2eALAZX95br09bjirRh9tUpg4fKvZxRZTTdaXBSkwowrHa0Rb1aZYC9hP839SpeDFtfR2kbx1RvfIKCR5aIrjpE5xcms6WkaECOj+RS3qrJVBFs9Dnysz6Udjgo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E74A7339; Fri, 25 Oct 2024 07:31:25 -0700 (PDT) Received: from VDW30FN91H.arm.com (unknown [10.57.79.117]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id F3AB53F73B; Fri, 25 Oct 2024 07:30:53 -0700 (PDT) From: Graham Woodward To: acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com, jolsa@kernel.org, irogers@google.com, james.clark@linaro.org, mike.leach@linaro.org, leo.yan@linux.dev, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: nd@arm.com, Graham Woodward Subject: [PATCH v1 2/4] perf arm-spe: Use ARM_SPE_OP_BRANCH_ERET when synthesizing branches Date: Fri, 25 Oct 2024 15:30:07 +0100 Message-Id: <20241025143009.25419-3-graham.woodward@arm.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241025143009.25419-1-graham.woodward@arm.com> References: <20241025143009.25419-1-graham.woodward@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Instead of checking the type for just branch misses, we can instead check for the OP_BRANCH_ERET and synthesise branches as well as branch misses. Signed-off-by: Graham Woodward Reviewed-by: James Clark Tested-by: Leo Yan --- tools/perf/util/arm-spe.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 49b763807360..e60e21d24735 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -68,7 +68,7 @@ struct arm_spe { u64 llc_access_id; u64 tlb_miss_id; u64 tlb_access_id; - u64 branch_miss_id; + u64 branch_id; u64 remote_access_id; u64 memory_id; u64 instructions_id; @@ -672,8 +672,8 @@ static int arm_spe_sample(struct arm_spe_queue *speq) } } =20 - if (spe->sample_branch && (record->type & ARM_SPE_BRANCH_MISS)) { - err =3D arm_spe__synth_branch_sample(speq, spe->branch_miss_id); + if (spe->sample_branch && (record->op & ARM_SPE_OP_BRANCH_ERET)) { + err =3D arm_spe__synth_branch_sample(speq, spe->branch_id); if (err) return err; } @@ -1385,12 +1385,12 @@ arm_spe_synth_events(struct arm_spe *spe, struct pe= rf_session *session) if (spe->synth_opts.branches) { spe->sample_branch =3D true; =20 - /* Branch miss */ + /* Branch */ err =3D perf_session__deliver_synth_attr_event(session, &attr, id); if (err) return err; - spe->branch_miss_id =3D id; - arm_spe_set_event_name(evlist, id, "branch-miss"); + spe->branch_id =3D id; + arm_spe_set_event_name(evlist, id, "branch"); id +=3D 1; } =20 --=20 2.40.1 From nobody Mon Nov 25 17:25:10 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6750820D4F7; Fri, 25 Oct 2024 14:30:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729866661; cv=none; b=Id5A4EeO72T+orh2pz/izebDLIHuxUtxxDlpPLdkZCnN6hbvaaSON8couFBbeat9PpFNCrHR7ihx3WDBZelOOR39yOH2hPk6NocBdWW9uingtoA7ZkecZXnLAndQFEl3vt5Y1KrtmmzhC1CyOeBDqlSq/B1B2xWR2qnXVf6HRN0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729866661; c=relaxed/simple; bh=bxlavruyCeOG0aiYoX6EJZfe8AAgSdNwL5KyPxMXcQw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bwYtv4U95wGSiJlEErz7g3erD+bQFqwQk6f/L6IiHWzeKfFG6SMjySdi93s+CxtDxVEOrjn87YjPJdjZCgt5wewPbXkm0NOOaIBEuvr18saBoXzVk37kHAujVPxu3gBcMTn7vCEYq2jdP4V1tIyMgar49RPzMwLIrH/jx7dmcSM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 835B9497; Fri, 25 Oct 2024 07:31:28 -0700 (PDT) Received: from VDW30FN91H.arm.com (unknown [10.57.79.117]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 873E53F73B; Fri, 25 Oct 2024 07:30:56 -0700 (PDT) From: Graham Woodward To: acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com, jolsa@kernel.org, irogers@google.com, james.clark@linaro.org, mike.leach@linaro.org, leo.yan@linux.dev, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: nd@arm.com, Graham Woodward Subject: [PATCH v1 3/4] perf arm-spe: Correctly set sample flags Date: Fri, 25 Oct 2024 15:30:08 +0100 Message-Id: <20241025143009.25419-4-graham.woodward@arm.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241025143009.25419-1-graham.woodward@arm.com> References: <20241025143009.25419-1-graham.woodward@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Set flags on all synthesized instruction and branch samples. Signed-off-by: Graham Woodward Reviewed-by: James Clark Tested-by: Leo Yan --- tools/perf/builtin-script.c | 1 + tools/perf/util/arm-spe.c | 17 +++++++++++++++++ tools/perf/util/event.h | 1 + 3 files changed, 19 insertions(+) diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index 8c5d5cecfba4..6b6d4472db6e 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -1728,6 +1728,7 @@ static struct { {PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_TRACE_END, "tr end"}, {PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL | PERF_IP_FLAG_VMENTRY, "vmentry= "}, {PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL | PERF_IP_FLAG_VMEXIT, "vmexit"}, + {PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_BRANCH_MISS, "br miss"}, {0, NULL} }; =20 diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index e60e21d24735..a291a412f6a1 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -100,6 +100,7 @@ struct arm_spe_queue { u64 timestamp; struct thread *thread; u64 period_instructions; + u32 flags; }; =20 static void arm_spe_dump(struct arm_spe *spe __maybe_unused, @@ -394,6 +395,7 @@ static int arm_spe__synth_branch_sample(struct arm_spe_= queue *speq, sample.stream_id =3D spe_events_id; sample.addr =3D record->to_ip; sample.weight =3D record->latency; + sample.flags =3D speq->flags; =20 return arm_spe_deliver_synth_event(spe, speq, event, &sample); } @@ -423,6 +425,7 @@ static int arm_spe__synth_instruction_sample(struct arm= _spe_queue *speq, sample.data_src =3D data_src; sample.period =3D spe->instructions_sample_period; sample.weight =3D record->latency; + sample.flags =3D speq->flags; =20 return arm_spe_deliver_synth_event(spe, speq, event, &sample); } @@ -440,6 +443,19 @@ static const struct midr_range common_ds_encoding_cpus= [] =3D { {}, }; =20 +static void arm_spe__sample_flags(struct arm_spe_queue *speq) +{ + const struct arm_spe_record *record =3D &speq->decoder->record; + + speq->flags =3D 0; + if (record->op & ARM_SPE_OP_BRANCH_ERET) { + speq->flags =3D PERF_IP_FLAG_BRANCH; + + if (record->type & ARM_SPE_BRANCH_MISS) + speq->flags |=3D PERF_IP_FLAG_BRANCH_MISS; + } +} + static void arm_spe__synth_data_source_common(const struct arm_spe_record = *record, union perf_mem_data_src *data_src) { @@ -622,6 +638,7 @@ static int arm_spe_sample(struct arm_spe_queue *speq) u64 data_src; int err; =20 + arm_spe__sample_flags(speq); data_src =3D arm_spe__synth_data_source(speq, record); =20 if (spe->sample_flc) { diff --git a/tools/perf/util/event.h b/tools/perf/util/event.h index f8742e6230a5..2744c54f404e 100644 --- a/tools/perf/util/event.h +++ b/tools/perf/util/event.h @@ -66,6 +66,7 @@ enum { PERF_IP_FLAG_VMEXIT =3D 1ULL << 12, PERF_IP_FLAG_INTR_DISABLE =3D 1ULL << 13, PERF_IP_FLAG_INTR_TOGGLE =3D 1ULL << 14, + PERF_IP_FLAG_BRANCH_MISS =3D 1ULL << 15, }; =20 #define PERF_IP_FLAG_CHARS "bcrosyiABExghDt" --=20 2.40.1 From nobody Mon Nov 25 17:25:10 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 24A3620D511; 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dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 21C22339; Fri, 25 Oct 2024 07:31:31 -0700 (PDT) Received: from VDW30FN91H.arm.com (unknown [10.57.79.117]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 249AB3F73B; Fri, 25 Oct 2024 07:30:58 -0700 (PDT) From: Graham Woodward To: acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com, jolsa@kernel.org, irogers@google.com, james.clark@linaro.org, mike.leach@linaro.org, leo.yan@linux.dev, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: nd@arm.com, Graham Woodward Subject: [PATCH v1 4/4] perf arm-spe: Update --itrace help text Date: Fri, 25 Oct 2024 15:30:09 +0100 Message-Id: <20241025143009.25419-5-graham.woodward@arm.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241025143009.25419-1-graham.woodward@arm.com> References: <20241025143009.25419-1-graham.woodward@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The --itrace help now needs updating to reflect that the --itrace=3Db argument sythesises branches as well as branch misses. Signed-off-by: Graham Woodward Reviewed-by: James Clark Tested-by: Leo Yan --- tools/perf/Documentation/itrace.txt | 2 +- tools/perf/Documentation/perf-arm-spe.txt | 2 +- tools/perf/util/auxtrace.h | 3 +-- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/tools/perf/Documentation/itrace.txt b/tools/perf/Documentation= /itrace.txt index 19cc179be9a7..40476b227f8d 100644 --- a/tools/perf/Documentation/itrace.txt +++ b/tools/perf/Documentation/itrace.txt @@ -1,6 +1,6 @@ i synthesize instructions events y synthesize cycles events - b synthesize branches events (branch misses for Arm SPE) + b synthesize branches events c synthesize branches events (calls only) r synthesize branches events (returns only) x synthesize transactions events diff --git a/tools/perf/Documentation/perf-arm-spe.txt b/tools/perf/Documen= tation/perf-arm-spe.txt index 0a3eda482307..de2b0b479249 100644 --- a/tools/perf/Documentation/perf-arm-spe.txt +++ b/tools/perf/Documentation/perf-arm-spe.txt @@ -187,7 +187,7 @@ groups: 7 llc-access 2 tlb-miss 1K tlb-access - 36 branch-miss + 36 branch 0 remote-access 900 memory =20 diff --git a/tools/perf/util/auxtrace.h b/tools/perf/util/auxtrace.h index a1895a4f530b..dddaf4f3ffed 100644 --- a/tools/perf/util/auxtrace.h +++ b/tools/perf/util/auxtrace.h @@ -75,7 +75,6 @@ enum itrace_period_type { * (not fully accurate, since CYC packets are only emitted * together with other events, such as branches) * @branches: whether to synthesize 'branches' events - * (branch misses only for Arm SPE) * @transactions: whether to synthesize events for transactions * @ptwrites: whether to synthesize events for ptwrites * @pwr_events: whether to synthesize power events @@ -650,7 +649,7 @@ bool auxtrace__evsel_is_auxtrace(struct perf_session *s= ession, #define ITRACE_HELP \ " i[period]: synthesize instructions events\n" \ " y[period]: synthesize cycles events (same period as i)\n" \ -" b: synthesize branches events (branch misses for Arm SPE)\n" \ +" b: synthesize branches events\n" \ " c: synthesize branches events (calls only)\n" \ " r: synthesize branches events (returns only)\n" \ " x: synthesize transactions events\n" \ --=20 2.40.1