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AJvYcCXvLv3bh1znjbbXSAJSqXqiox8vVCTBPJyh11lyJKwz0SpolYL5N52dYVM0kIPJmkknPxU80oOFcEBDw5w=@vger.kernel.org X-Gm-Message-State: AOJu0Yyhqrn3nrKaRaz5lNutHLT/z51upbzk01OiSZ0bSYBY/6JswqUa 9WiRvzYRUZ1/JdxV9YB3c//fH661fT29zx7hMt0tfmwFNVIYfP9zYRqZl8xo0WE= X-Google-Smtp-Source: AGHT+IGy7gCwHmZzWRjYuJdLjKUklIvRll7qzxjTVKsdjpMsJu9lcX39EllePZe+fyuRleAhBbilyQ== X-Received: by 2002:a5d:4441:0:b0:37c:d1ea:f1ce with SMTP id ffacd0b85a97d-37efcf15f1fmr7504792f8f.25.1729862099741; Fri, 25 Oct 2024 06:14:59 -0700 (PDT) Received: from gpeter-l.lan ([145.224.67.228]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b58b6bdsm47616685e9.45.2024.10.25.06.14.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 06:14:59 -0700 (PDT) From: Peter Griffin To: alim.akhtar@samsung.com, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, avri.altman@wdc.com, bvanassche@acm.org, krzk@kernel.org Cc: tudor.ambarus@linaro.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, ebiggers@kernel.org, Peter Griffin Subject: [PATCH v2 08/11] scsi: ufs: exynos: enable write line unique transactions on gs101 Date: Fri, 25 Oct 2024 14:14:39 +0100 Message-ID: <20241025131442.112862-9-peter.griffin@linaro.org> X-Mailer: git-send-email 2.47.0.163.g1226f6d8fa-goog In-Reply-To: <20241025131442.112862-1-peter.griffin@linaro.org> References: <20241025131442.112862-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Previously just AXIDMA_RWDATA_BURST_LEN[3:0] field was set to 8. To enable WLU transaction additionally we need to set Write Line Unique enable [31], Write Line Unique Burst Length [30:27] and AXIDMA_RWDATA_BURST_LEN[3:0]. To support WLU transaction, both burth length fields need to be 0x3. Signed-off-by: Peter Griffin Reviewed-by: Tudor Ambarus --- drivers/ufs/host/ufs-exynos.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 40b2563fe011..b0cbb147c7a1 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -48,6 +48,8 @@ #define HCI_UNIPRO_APB_CLK_CTRL 0x68 #define UNIPRO_APB_CLK(v, x) (((v) & ~0xF) | ((x) & 0xF)) #define HCI_AXIDMA_RWDATA_BURST_LEN 0x6C +#define WLU_EN BIT(31) +#define WLU_BURST_LEN(x) ((x) << 27 | ((x) & 0xF)) #define HCI_GPIO_OUT 0x70 #define HCI_ERR_EN_PA_LAYER 0x78 #define HCI_ERR_EN_DL_LAYER 0x7C @@ -1925,6 +1927,12 @@ static int gs101_ufs_post_link(struct exynos_ufs *uf= s) { struct ufs_hba *hba =3D ufs->hba; =20 + /* + * Enable Write Line Unique. This field has to be 0x3 + * to support Write Line Unique transaction on gs101. + */ + hci_writel(ufs, WLU_EN | WLU_BURST_LEN(3), HCI_AXIDMA_RWDATA_BURST_LEN); + exynos_ufs_enable_dbg_mode(hba); ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0x3e8); exynos_ufs_disable_dbg_mode(hba); --=20 2.47.0.163.g1226f6d8fa-goog