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Fri, 25 Oct 2024 12:45:34 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id cPeAHO6SG2fzOAAAD6G6ig (envelope-from ); Fri, 25 Oct 2024 12:45:34 +0000 From: Stanimir Varbanov To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Broadcom internal kernel review list Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Jim Quinlan , Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , kw@linux.com, Philipp Zabel , Andrea della Porta , Phil Elwell , Jonathan Bell , Stanimir Varbanov Subject: [PATCH v4 07/10] PCI: brcmstb: Add bcm2712 support Date: Fri, 25 Oct 2024 15:45:12 +0300 Message-ID: <20241025124515.14066-8-svarbanov@suse.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241025124515.14066-1-svarbanov@suse.de> References: <20241025124515.14066-1-svarbanov@suse.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Level: X-Spamd-Result: default: False [-5.30 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; SUSPICIOUS_RECIPS(1.50)[]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; TAGGED_RCPT(0.00)[dt]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCPT_COUNT_TWELVE(0.00)[21]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; FREEMAIL_CC(0.00)[linutronix.de,kernel.org,broadcom.com,gmail.com,google.com,linux.com,pengutronix.de,suse.com,raspberrypi.com,suse.de]; FROM_HAS_DN(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.de:email,suse.de:mid,imap1.dmz-prg2.suse.org:helo]; RCVD_COUNT_TWO(0.00)[2]; RCVD_TLS_ALL(0.00)[]; DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; R_RATELIMIT(0.00)[to_ip_from(RL7mwea5a3cdyragbzqhrtit3y)]; FUZZY_BLOCKED(0.00)[rspamd.com]; FREEMAIL_ENVRCPT(0.00)[gmail.com] X-Spam-Score: -5.30 X-Spam-Flag: NO Content-Type: text/plain; charset="utf-8" Add bare minimum amount of changes in order to support PCIe RC hardware IP found on RPi5. The PCIe controller on bcm2712 is based on bcm7712 and as such it inherits register offsets, perst, bridge_reset ops and inbound windows count. Although, the implementation for bcm2712 needs a workaround related to the control of the bridge_reset where turning off of the root port must not shutdown the bridge_reset and this must be avoided. To implement this workaround a quirks field is introduced in pcie_cfg_data struct. Signed-off-by: Stanimir Varbanov Reviewed-by: Florian Fainelli --- v3 -> v4: - Merged "PCI: brcmstb: Avoid turn off of bridge reset" from v3 here in this patch (Bjorn) drivers/pci/controller/pcie-brcmstb.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index af01a7915c94..d970a76aa9ef 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -234,10 +234,20 @@ struct inbound_win { u64 cpu_addr; }; =20 +/* + * The RESCAL block is tied to PCIe controller #1, regardless of the numbe= r of + * controllers, and turning off PCIe controller #1 prevents access to the = RESCAL + * register blocks, therefore no other controller can access this register + * space, and depending upon the bus fabric we may get a timeout (UBUS/GIS= B), + * or a hang (AXI). + */ +#define CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN BIT(0) + struct pcie_cfg_data { const int *offsets; const enum pcie_soc_base soc_base; const bool has_phy; + const u32 quirks; u8 num_inbound_wins; int (*perst_set)(struct brcm_pcie *pcie, u32 val); int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); @@ -1534,8 +1544,9 @@ static int brcm_pcie_turn_off(struct brcm_pcie *pcie) u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MAS= K); writel(tmp, base + HARD_DEBUG(pcie)); =20 - /* Shutdown PCIe bridge */ - ret =3D pcie->bridge_sw_init_set(pcie, 1); + if (!(pcie->cfg->quirks & CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN)) + /* Shutdown PCIe bridge */ + ret =3D pcie->cfg->bridge_sw_init_set(pcie, 1); =20 return ret; } @@ -1745,6 +1756,15 @@ static const struct pcie_cfg_data bcm2711_cfg =3D { .num_inbound_wins =3D 3, }; =20 +static const struct pcie_cfg_data bcm2712_cfg =3D { + .offsets =3D pcie_offsets_bcm7712, + .soc_base =3D BCM7712, + .perst_set =3D brcm_pcie_perst_set_7278, + .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, + .quirks =3D CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN, + .num_inbound_wins =3D 10, +}; + static const struct pcie_cfg_data bcm4908_cfg =3D { .offsets =3D pcie_offsets, .soc_base =3D BCM4908, @@ -1796,6 +1816,7 @@ static const struct pcie_cfg_data bcm7712_cfg =3D { =20 static const struct of_device_id brcm_pcie_match[] =3D { { .compatible =3D "brcm,bcm2711-pcie", .data =3D &bcm2711_cfg }, + { .compatible =3D "brcm,bcm2712-pcie", .data =3D &bcm2712_cfg }, { .compatible =3D "brcm,bcm4908-pcie", .data =3D &bcm4908_cfg }, { .compatible =3D "brcm,bcm7211-pcie", .data =3D &generic_cfg }, { .compatible =3D "brcm,bcm7216-pcie", .data =3D &bcm7216_cfg }, --=20 2.43.0