From nobody Mon Nov 25 20:51:53 2024 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.223.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8458420BB20; Fri, 25 Oct 2024 12:45:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729860341; cv=none; b=P70qbvwR8vQOGTj23weh6/RiGNFfWhERR6n7kITGQ6CvKNGdx+pgJslUxPpgVLn0NIXp2r2dBEhVdIx+tGI/x7Pq6jX7LCcFSK8ubsLO9OFVwA+EVGs/HjuraKbcrPOp/cWBC7oxVnlnHWPJNOMolmt3HIsNSGHTSR42QePEwIY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729860341; c=relaxed/simple; bh=kiUiL7nhGpDyprtFl2QIfjU0EhrjMkSbhA/5IKkxOp0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=c7WFmnCx0DB/BQ8UuI0M6q/yOSQ6V038+OQSbMTM+QFaPBQBUEjTZycJiKC3joWIwaYu4kqta5VAgnD2dGVil7UVMVVFDXvhueX9NTW9xfTQXCfb98Wx1N8/GCU7PS/ukPQnftq60n1S8dv8/T3pK8v3dp2uwZ3p0RFJxqFhqYU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=suse.de; spf=pass smtp.mailfrom=suse.de; arc=none smtp.client-ip=195.135.223.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=suse.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.de Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id CA5401FE0E; Fri, 25 Oct 2024 12:45:37 +0000 (UTC) Authentication-Results: smtp-out2.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id B117F136F5; Fri, 25 Oct 2024 12:45:36 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id sJm1KPCSG2fzOAAAD6G6ig (envelope-from ); Fri, 25 Oct 2024 12:45:36 +0000 From: Stanimir Varbanov To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Broadcom internal kernel review list Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Jim Quinlan , Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , kw@linux.com, Philipp Zabel , Andrea della Porta , Phil Elwell , Jonathan Bell , Stanimir Varbanov Subject: [PATCH v4 09/10] arm64: dts: broadcom: bcm2712: Add PCIe DT nodes Date: Fri, 25 Oct 2024 15:45:14 +0300 Message-ID: <20241025124515.14066-10-svarbanov@suse.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241025124515.14066-1-svarbanov@suse.de> References: <20241025124515.14066-1-svarbanov@suse.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spam-Level: X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[]; TAGGED_RCPT(0.00)[dt]; ASN(0.00)[asn:25478, ipnet:::/0, country:RU] X-Spam-Score: -4.00 X-Spam-Flag: NO X-Rspamd-Queue-Id: CA5401FE0E X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Action: no action X-Rspamd-Server: rspamd2.dmz-prg2.suse.org Content-Type: text/plain; charset="utf-8" Add PCIe devicetree nodes, plus needed reset and mip MSI-X controllers. Signed-off-by: Stanimir Varbanov --- v3 -> v4: - Added msi-controller property required by brcm,stb-pcie.yaml schema arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 162 ++++++++++++++++++++++ 1 file changed, 162 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dt= s/broadcom/bcm2712.dtsi index 6e5a984c1d4e..8fcdf27c1221 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -192,6 +192,12 @@ soc: soc@107c000000 { #address-cells =3D <1>; #size-cells =3D <1>; =20 + pcie_rescal: reset-controller@119500 { + compatible =3D "brcm,bcm7216-pcie-sata-rescal"; + reg =3D <0x00119500 0x10>; + #reset-cells =3D <0>; + }; + sdio1: mmc@fff000 { compatible =3D "brcm,bcm2712-sdhci", "brcm,sdhci-brcmstb"; @@ -204,6 +210,12 @@ sdio1: mmc@fff000 { mmc-ddr-3_3v; }; =20 + bcm_reset: reset-controller@1504318 { + compatible =3D "brcm,brcmstb-reset"; + reg =3D <0x01504318 0x30>; + #reset-cells =3D <1>; + }; + system_timer: timer@7c003000 { compatible =3D "brcm,bcm2835-system-timer"; reg =3D <0x7c003000 0x1000>; @@ -267,6 +279,156 @@ gicv2: interrupt-controller@7fff9000 { }; }; =20 + axi@1000000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + ranges =3D <0x00 0x00000000 0x10 0x00000000 0x01 0x00000000>, + <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, + <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, + <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; + + dma-ranges =3D <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, + <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, + <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, + <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; + + pcie0: pcie@100000 { + compatible =3D "brcm,bcm2712-pcie"; + reg =3D <0x00 0x00100000 0x00 0x9310>; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + max-link-speed =3D <2>; + bus-range =3D <0x00 0xff>; + num-lanes =3D <1>; + #address-cells =3D <3>; + #interrupt-cells =3D <1>; + #size-cells =3D <2>; + interrupt-parent =3D <&gicv2>; + interrupts =3D , + ; + interrupt-names =3D "pcie", "msi"; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0 0 0 1 &gicv2 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gicv2 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gicv2 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gicv2 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; + resets =3D <&bcm_reset 42>, <&pcie_rescal>; + reset-names =3D "bridge", "rescal"; + msi-controller; + msi-parent =3D <&pcie0>; + + ranges =3D + /* ~4GB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ + <0x02000000 0x00 0x00000000 0x17 0x00000000 0x00 0xfffffffc>, + /* 12GB, 64-bit, prefetchable at PCIe 04_0000_0000 */ + <0x43000000 0x04 0x00000000 0x14 0x00000000 0x03 0x00000000>; + + dma-ranges =3D + /* 64GB, 64-bit, prefetchable at PCIe 10_0000_0000 */ + <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>; + + status =3D "disabled"; + }; + + pcie1: pcie@110000 { + compatible =3D "brcm,bcm2712-pcie"; + reg =3D <0x00 0x00110000 0x00 0x9310>; + device_type =3D "pci"; + linux,pci-domain =3D <1>; + max-link-speed =3D <2>; + bus-range =3D <0x00 0xff>; + num-lanes =3D <1>; + #address-cells =3D <3>; + #interrupt-cells =3D <1>; + #size-cells =3D <2>; + interrupt-parent =3D <&gicv2>; + interrupts =3D , + ; + interrupt-names =3D "pcie", "msi"; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0 0 0 1 &gicv2 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gicv2 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gicv2 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gicv2 GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + resets =3D <&bcm_reset 43>, <&pcie_rescal>; + reset-names =3D "bridge", "rescal"; + msi-controller; + msi-parent =3D <&mip1>; + + ranges =3D + /* ~4GB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ + <0x02000000 0x00 0x00000000 0x1b 0x00000000 0x00 0xfffffffc>, + /* 12GB, 64-bit, prefetchable at PCIe 04_0000_0000 */ + <0x43000000 0x04 0x00000000 0x18 0x00000000 0x03 0x00000000>; + + dma-ranges =3D + /* 64GB, 64-bit, non-prefetchable at PCIe 10_0000_0000 */ + <0x03000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>; + + status =3D "disabled"; + }; + + pcie2: pcie@120000 { + compatible =3D "brcm,bcm2712-pcie"; + reg =3D <0x00 0x00120000 0x00 0x9310>; + device_type =3D "pci"; + linux,pci-domain =3D <2>; + max-link-speed =3D <2>; + bus-range =3D <0x00 0xff>; + num-lanes =3D <4>; + #address-cells =3D <3>; + #interrupt-cells =3D <1>; + #size-cells =3D <2>; + interrupt-parent =3D <&gicv2>; + interrupts =3D , + ; + interrupt-names =3D "pcie", "msi"; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0 0 0 1 &gicv2 GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gicv2 GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gicv2 GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gicv2 GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; + resets =3D <&bcm_reset 44>, <&pcie_rescal>; + reset-names =3D "bridge", "rescal"; + msi-controller; + msi-parent =3D <&mip0>; + + ranges =3D + /* ~4GB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ + <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0xfffffffc>, + /* 12GB, 64-bit, prefetchable at PCIe 04_0000_0000 */ + <0x43000000 0x04 0x00000000 0x1c 0x00000000 0x03 0x00000000>; + + dma-ranges =3D + /* 4MB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ + <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0x00400000>, + /* 64GB, 64-bit, prefetchable at PCIe 10_0000_0000 */ + <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>; + + status =3D "disabled"; + }; + + mip0: msi-controller@130000 { + compatible =3D "brcm,bcm2712-mip"; + reg =3D <0x00 0x00130000 0x00 0xc0>, + <0xff 0xfffff000 0x00 0x1000>; + msi-controller; + msi-ranges =3D <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>; + brcm,msi-offset =3D <0>; + }; + + mip1: msi-controller@131000 { + compatible =3D "brcm,bcm2712-mip"; + reg =3D <0x00 0x00131000 0x00 0xc0>, + <0xff 0xfffff000 0x00 0x1000>; + msi-controller; + msi-ranges =3D <&gicv2 GIC_SPI 247 IRQ_TYPE_EDGE_RISING 8>; + brcm,msi-offset =3D <8>; + }; + }; + timer { compatible =3D "arm,armv8-timer"; interrupts =3D