From nobody Mon Nov 25 19:52:15 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC2D71632FC; Fri, 25 Oct 2024 12:36:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729859794; cv=none; b=La8zPWoglOuPwQVsDxol8bc7IlcBg005m9bfcheMtVkLcfdpGe7twHHTmkYNO0DRJD3YgwfamdY16G3S5ABeweH+z3ihU2WxS3VKE45PCzGxO9j0bXrUJwPiZbLOdouLxSga9pWtrNt4GEkSF+gMF7xGtuFdFNet6vRTWFWOJrk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729859794; c=relaxed/simple; bh=cfeurgQs2tJmtrnz/mJzzdUt96hFlpoORjHf0Mnf8fk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MkIT3bJcfxVpx79oMTCcqhhDYYx/8wOm56ZTIHP1m6NyCRf2VGbl1hcp9pmHhBrNnObtjqbGreViQcdxUyYT/RWlg/BuG8iAio43epG7F7DwLlJogeYYxTbs+vHkXljd2cb8jkKaGDCKPMJvYhsLjxqcBCWTvthkvJlTCpKk+uc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=pJZkxDnH; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="pJZkxDnH" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49P33b0C030045; Fri, 25 Oct 2024 12:36:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 2+siVXxtWwGmEQ3+YuGWJsO+mMnehjKS9yIG9E8wBhA=; b=pJZkxDnHrjuVD7vj BXKGLVE/DSSpT4sD0+GZwkNgFRm3cSeUiONd2WhbiUxW9OX3nAVJxtL3BQHIjdGd ZX3hhOnShG4sFai+1uHQ2UPFqmgG7ji0DYm2Ayn5shgTUwst29zgu4IeOc0qpxRM fJrUzJNKt05pOdU6MbFKzMEDUFE9lNZJPsHHsAnSZAlh19zocEKw2G2BeesY3IFc 066rnspAugypL60lv0UZB8XQhQI7l/5pSiqh4IeaA3RBCmEKz/10ZDXqtEiSOCkD DjwPZAlJoW6kFygW+jDfympN2AJxV5KiSIpNWHAL9BvlAlyjm+CC76f89/tkz4PS PJmDOQ== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42fdtxmu2j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 12:36:25 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49PCaOT0000589 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 12:36:24 GMT Received: from hu-sibis-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 25 Oct 2024 05:36:19 -0700 From: Sibi Sankar To: , , , , CC: , , , , , , , , , Subject: [PATCH V1 3/3] arm64: dts: qcom: x1e001de-devkit: Enable external DP support Date: Fri, 25 Oct 2024 18:05:51 +0530 Message-ID: <20241025123551.3528206-4-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025123551.3528206-1-quic_sibis@quicinc.com> References: <20241025123551.3528206-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: vIAnnQexZGHu9iKTxQK6Sow44zVfoIWF X-Proofpoint-ORIG-GUID: vIAnnQexZGHu9iKTxQK6Sow44zVfoIWF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 bulkscore=0 spamscore=0 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410250097 Content-Type: text/plain; charset="utf-8" The Qualcomm Snapdragon X Elite Devkit for Windows has the same configuration as the CRD variant i.e. all 3 of the type C ports support external DP altmode. Add all the nodes needed to enable them. Signed-off-by: Sibi Sankar --- PS: The ext display patch 3 needs pin-conf and updates from comments on the list. Just included it in the series so that people can get display up. Type c to DP was tested on all ports with [1] as the base branch. [1] https://git.codelinaro.org/abel.vesa/linux/-/commits/x1e-next-20240930 arch/arm64/boot/dts/qcom/x1e001de-devkit.dts | 444 ++++++++++++++++++- 1 file changed, 438 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot= /dts/qcom/x1e001de-devkit.dts index f169714abcd3..a1dc29a3a05e 100644 --- a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -82,7 +82,15 @@ port@1 { reg =3D <1>; =20 pmic_glink_ss0_ss_in: endpoint { - remote-endpoint =3D <&usb_1_ss0_qmpphy_out>; + remote-endpoint =3D <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint =3D <&retimer_ss0_con_sbu_out>; }; }; }; @@ -111,7 +119,15 @@ port@1 { reg =3D <1>; =20 pmic_glink_ss1_ss_in: endpoint { - remote-endpoint =3D <&usb_1_ss1_qmpphy_out>; + remote-endpoint =3D <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint =3D <&retimer_ss1_con_sbu_out>; }; }; }; @@ -140,7 +156,15 @@ port@1 { reg =3D <1>; =20 pmic_glink_ss2_ss_in: endpoint { - remote-endpoint =3D <&usb_1_ss2_qmpphy_out>; + remote-endpoint =3D <&retimer_ss2_ss_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_ss2_con_sbu_in: endpoint { + remote-endpoint =3D <&retimer_ss2_con_sbu_out>; }; }; }; @@ -213,6 +237,150 @@ vreg_nvme: regulator-nvme { regulator-boot-on; }; =20 + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR0_1P15"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1150000>; + + gpio =3D <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb0_pwr_1p15_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR0_1P8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + gpio =3D <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb0_1p8_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR0_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb0_3p3_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR1_1P15"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1150000>; + + gpio =3D <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&rtmr1_1p15_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR1_1P8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + gpio =3D <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&rtmr1_1p8_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR1_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&rtmr1_3p3_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_1p15: regulator-rtmr2-1p15 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR2_1P15"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1150000>; + + gpio =3D <&tlmm 189 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&rtmr2_1p15_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_1p8: regulator-rtmr2-1p8 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR2_1P8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + gpio =3D <&tlmm 126 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&rtmr2_1p8_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_3p3: regulator-rtmr2-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR2_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 187 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&rtmr2_3p3_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + vph_pwr: regulator-vph-pwr { compatible =3D "regulator-fixed"; =20 @@ -591,6 +759,207 @@ vreg_l3j_0p8: ldo3 { }; }; =20 +&gpu { + status =3D "okay"; + + zap-shader { + firmware-name =3D "qcom/x1e80100/Thundercomm/DEVKIT/qcdxkmsuc8380.mbn"; + }; +}; + +&i2c1 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + typec-mux@8 { + compatible =3D "parade,ps8830"; + reg =3D <0x08>; + + clocks =3D <&rpmhcc RPMH_RF_CLK5>; + clock-names =3D "xo"; + + vdd-supply =3D <&vreg_rtmr2_1p15>; + vdd33-supply =3D <&vreg_rtmr2_3p3>; + vdd33-cap-supply =3D <&vreg_rtmr2_3p3>; + vddar-supply =3D <&vreg_rtmr2_1p15>; + vddat-supply =3D <&vreg_rtmr2_1p15>; + vddio-supply =3D <&vreg_rtmr2_1p8>; + + reset-gpios =3D <&tlmm 185 GPIO_ACTIVE_HIGH>; + + orientation-switch; + retimer-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + retimer_ss2_ss_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss2_ss_in>; + }; + }; + + port@1 { + reg =3D <1>; + + retimer_ss2_ss_in: endpoint { + remote-endpoint =3D <&usb_1_ss2_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + retimer_ss2_con_sbu_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss2_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c3 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + typec-mux@8 { + compatible =3D "parade,ps8830"; + reg =3D <0x08>; + + clocks =3D <&rpmhcc RPMH_RF_CLK3>; + clock-names =3D "xo"; + + vdd-supply =3D <&vreg_rtmr0_1p15>; + vdd33-supply =3D <&vreg_rtmr0_3p3>; + vdd33-cap-supply =3D <&vreg_rtmr0_3p3>; + vddar-supply =3D <&vreg_rtmr0_1p15>; + vddat-supply =3D <&vreg_rtmr0_1p15>; + vddio-supply =3D <&vreg_rtmr0_1p8>; + + reset-gpios =3D <&pm8550_gpios 10 GPIO_ACTIVE_HIGH>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg =3D <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint =3D <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c7 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + typec-mux@8 { + compatible =3D "parade,ps8830"; + reg =3D <0x8>; + + clocks =3D <&rpmhcc RPMH_RF_CLK4>; + clock-names =3D "xo"; + + vdd-supply =3D <&vreg_rtmr1_1p15>; + vdd33-supply =3D <&vreg_rtmr1_3p3>; + vdd33-cap-supply =3D <&vreg_rtmr1_3p3>; + vddar-supply =3D <&vreg_rtmr1_1p15>; + vddat-supply =3D <&vreg_rtmr1_1p15>; + vddio-supply =3D <&vreg_rtmr1_1p8>; + + reset-gpios =3D <&tlmm 176 GPIO_ACTIVE_HIGH>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg =3D <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint =3D <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_dp0 { + status =3D "okay"; +}; + +&mdss_dp0_out { + data-lanes =3D <0 1>; +}; + +&mdss_dp1 { + status =3D "okay"; +}; + +&mdss_dp1_out { + data-lanes =3D <0 1>; +}; + +&mdss_dp2 { + status =3D "okay"; +}; + +&mdss_dp2_out { + data-lanes =3D <0 1>; +}; + &pcie4 { perst-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; @@ -646,6 +1015,27 @@ &pcie6a_phy { status =3D "okay"; }; =20 +&pm8550_gpios { + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins =3D "gpio11"; + function =3D "normal"; + }; +}; + +&pmc8380_5_gpios { + usb0_pwr_1p15_en: usb0-pwr-1p15-en-state { + pins =3D "gpio8"; + function =3D "normal"; + }; +}; + +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins =3D "gpio8"; + function =3D "normal"; + }; +}; + &qupv3_0 { status =3D "okay"; }; @@ -805,6 +1195,48 @@ wake-n-pins { }; }; =20 + rtmr1_1p15_reg_en: rtmr1-1p15-reg-en-state { + pins =3D "gpio188"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + rtmr1_1p8_reg_en: rtmr1-1p8-reg-en-state { + pins =3D "gpio175"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + rtmr1_3p3_reg_en: rtmr1-3p3-reg-en-state { + pins =3D "gpio186"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + rtmr2_1p15_reg_en: rtmr2-1p15-reg-en-state { + pins =3D "gpio189"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + rtmr2_1p8_reg_en: rtmr2-1p8-reg-en-state { + pins =3D "gpio126"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + rtmr2_3p3_reg_en: rtmr2-3p3-reg-en-state { + pins =3D "gpio187"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + sdc2_card_det_n: sdc2-card-det-state { pins =3D "gpio71"; function =3D "gpio"; @@ -863,7 +1295,7 @@ &usb_1_ss0_dwc3_hs { }; =20 &usb_1_ss0_qmpphy_out { - remote-endpoint =3D <&pmic_glink_ss0_ss_in>; + remote-endpoint =3D <&retimer_ss0_ss_in>; }; =20 &usb_1_ss1_hsphy { @@ -895,7 +1327,7 @@ &usb_1_ss1_dwc3_hs { }; =20 &usb_1_ss1_qmpphy_out { - remote-endpoint =3D <&pmic_glink_ss1_ss_in>; + remote-endpoint =3D <&retimer_ss1_ss_in>; }; =20 &usb_1_ss2_hsphy { @@ -927,5 +1359,5 @@ &usb_1_ss2_dwc3_hs { }; =20 &usb_1_ss2_qmpphy_out { - remote-endpoint =3D <&pmic_glink_ss2_ss_in>; + remote-endpoint =3D <&retimer_ss2_ss_in>; }; --=20 2.34.1