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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 11:16:31.3104 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b4cfbe03-d271-4488-39b8-08dcf4e67a72 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E60.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7914 Content-Type: text/plain; charset="utf-8" Prepare for the addition of RAPL core energy counter support. Replace the generic names with *_pkg*, to later on differentiate between=20 the scopes of the two different PMUs and their variables. No functional change. Signed-off-by: Dhananjay Ugwekar Reviewed-by: Gautham R. Shenoy Reviewed-by: Zhang Rui Tested-by: Zhang Rui --- arch/x86/events/rapl.c | 118 ++++++++++++++++++++--------------------- 1 file changed, 59 insertions(+), 59 deletions(-) diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index bf6fee114294..ae8b450caa9b 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -70,18 +70,18 @@ MODULE_LICENSE("GPL"); /* * RAPL energy status counters */ -enum perf_rapl_events { +enum perf_rapl_pkg_events { PERF_RAPL_PP0 =3D 0, /* all cores */ PERF_RAPL_PKG, /* entire package */ PERF_RAPL_RAM, /* DRAM */ PERF_RAPL_PP1, /* gpu */ PERF_RAPL_PSYS, /* psys */ =20 - PERF_RAPL_MAX, - NR_RAPL_DOMAINS =3D PERF_RAPL_MAX, + PERF_RAPL_PKG_EVENTS_MAX, + NR_RAPL_PKG_DOMAINS =3D PERF_RAPL_PKG_EVENTS_MAX, }; =20 -static const char *const rapl_domain_names[NR_RAPL_DOMAINS] __initconst = =3D { +static const char *const rapl_pkg_domain_names[NR_RAPL_PKG_DOMAINS] __init= const =3D { "pp0-core", "package", "dram", @@ -112,7 +112,7 @@ static struct perf_pmu_events_attr event_attr_##v =3D {= \ * considered as either pkg-scope or die-scope, and we are considering * them as die-scope. */ -#define rapl_pmu_is_pkg_scope() \ +#define rapl_pkg_pmu_is_pkg_scope() \ (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD || \ boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_HYGON) =20 @@ -139,16 +139,16 @@ enum rapl_unit_quirk { }; =20 struct rapl_model { - struct perf_msr *rapl_msrs; - unsigned long events; + struct perf_msr *rapl_pkg_msrs; + unsigned long pkg_events; unsigned int msr_power_unit; enum rapl_unit_quirk unit_quirk; }; =20 /* 1/2^hw_unit Joule */ -static int rapl_hw_unit[NR_RAPL_DOMAINS] __read_mostly; -static struct rapl_pmus *rapl_pmus; -static unsigned int rapl_cntr_mask; +static int rapl_pkg_hw_unit[NR_RAPL_PKG_DOMAINS] __read_mostly; +static struct rapl_pmus *rapl_pmus_pkg; +static unsigned int rapl_pkg_cntr_mask; static u64 rapl_timer_ms; static struct perf_msr *rapl_msrs; static struct rapl_model *rapl_model; @@ -159,7 +159,7 @@ static struct rapl_model *rapl_model; */ static inline unsigned int get_rapl_pmu_idx(int cpu) { - return rapl_pmu_is_pkg_scope() ? topology_logical_package_id(cpu) : + return rapl_pkg_pmu_is_pkg_scope() ? topology_logical_package_id(cpu) : topology_logical_die_id(cpu); } =20 @@ -172,7 +172,7 @@ static inline u64 rapl_read_counter(struct perf_event *= event) =20 static inline u64 rapl_scale(u64 v, int cfg) { - if (cfg > NR_RAPL_DOMAINS) { + if (cfg > NR_RAPL_PKG_DOMAINS) { pr_warn("Invalid domain %d, failed to scale data\n", cfg); return v; } @@ -182,7 +182,7 @@ static inline u64 rapl_scale(u64 v, int cfg) * or use ldexp(count, -32). * Watts =3D Joules/Time delta */ - return v << (32 - rapl_hw_unit[cfg - 1]); + return v << (32 - rapl_pkg_hw_unit[cfg - 1]); } =20 static u64 rapl_event_update(struct perf_event *event) @@ -342,7 +342,7 @@ static int rapl_pmu_event_init(struct perf_event *event) struct rapl_pmu *rapl_pmu; =20 /* only look at RAPL events */ - if (event->attr.type !=3D rapl_pmus->pmu.type) + if (event->attr.type !=3D rapl_pmus_pkg->pmu.type) return -ENOENT; =20 /* check only supported bits are set */ @@ -352,14 +352,14 @@ static int rapl_pmu_event_init(struct perf_event *eve= nt) if (event->cpu < 0) return -EINVAL; =20 - if (!cfg || cfg >=3D NR_RAPL_DOMAINS + 1) + if (!cfg || cfg >=3D NR_RAPL_PKG_DOMAINS + 1) return -EINVAL; =20 - cfg =3D array_index_nospec((long)cfg, NR_RAPL_DOMAINS + 1); + cfg =3D array_index_nospec((long)cfg, NR_RAPL_PKG_DOMAINS + 1); bit =3D cfg - 1; =20 /* check event supported */ - if (!(rapl_cntr_mask & (1 << bit))) + if (!(rapl_pkg_cntr_mask & (1 << bit))) return -EINVAL; =20 /* unsupported modes and filters */ @@ -367,11 +367,11 @@ static int rapl_pmu_event_init(struct perf_event *eve= nt) return -EINVAL; =20 rapl_pmu_idx =3D get_rapl_pmu_idx(event->cpu); - if (rapl_pmu_idx >=3D rapl_pmus->nr_rapl_pmu) + if (rapl_pmu_idx >=3D rapl_pmus_pkg->nr_rapl_pmu) return -EINVAL; =20 /* must be done before validate_group */ - rapl_pmu =3D rapl_pmus->rapl_pmu[rapl_pmu_idx]; + rapl_pmu =3D rapl_pmus_pkg->rapl_pmu[rapl_pmu_idx]; if (!rapl_pmu) return -EINVAL; =20 @@ -525,11 +525,11 @@ static struct perf_msr intel_rapl_spr_msrs[] =3D { }; =20 /* - * Force to PERF_RAPL_MAX size due to: - * - perf_msr_probe(PERF_RAPL_MAX) + * Force to PERF_RAPL_PKG_EVENTS_MAX size due to: + * - perf_msr_probe(PERF_RAPL_PKG_EVENTS_MAX) * - want to use same event codes across both architectures */ -static struct perf_msr amd_rapl_msrs[] =3D { +static struct perf_msr amd_rapl_pkg_msrs[] =3D { [PERF_RAPL_PP0] =3D { 0, &rapl_events_cores_group, NULL, false, 0 }, [PERF_RAPL_PKG] =3D { MSR_AMD_PKG_ENERGY_STATUS, &rapl_events_pkg_group= , test_msr, false, RAPL_MSR_MASK }, [PERF_RAPL_RAM] =3D { 0, &rapl_events_ram_group, NULL, false, 0 }, @@ -545,8 +545,8 @@ static int rapl_check_hw_unit(void) /* protect rdmsrl() to handle virtualization */ if (rdmsrl_safe(rapl_model->msr_power_unit, &msr_rapl_power_unit_bits)) return -1; - for (i =3D 0; i < NR_RAPL_DOMAINS; i++) - rapl_hw_unit[i] =3D (msr_rapl_power_unit_bits >> 8) & 0x1FULL; + for (i =3D 0; i < NR_RAPL_PKG_DOMAINS; i++) + rapl_pkg_hw_unit[i] =3D (msr_rapl_power_unit_bits >> 8) & 0x1FULL; =20 switch (rapl_model->unit_quirk) { /* @@ -556,11 +556,11 @@ static int rapl_check_hw_unit(void) * of 2. Datasheet, September 2014, Reference Number: 330784-001 " */ case RAPL_UNIT_QUIRK_INTEL_HSW: - rapl_hw_unit[PERF_RAPL_RAM] =3D 16; + rapl_pkg_hw_unit[PERF_RAPL_RAM] =3D 16; break; /* SPR uses a fixed energy unit for Psys domain. */ case RAPL_UNIT_QUIRK_INTEL_SPR: - rapl_hw_unit[PERF_RAPL_PSYS] =3D 0; + rapl_pkg_hw_unit[PERF_RAPL_PSYS] =3D 0; break; default: break; @@ -575,9 +575,9 @@ static int rapl_check_hw_unit(void) * if hw unit is 32, then we use 2 ms 1/200/2 */ rapl_timer_ms =3D 2; - if (rapl_hw_unit[0] < 32) { + if (rapl_pkg_hw_unit[0] < 32) { rapl_timer_ms =3D (1000 / (2 * 100)); - rapl_timer_ms *=3D (1ULL << (32 - rapl_hw_unit[0] - 1)); + rapl_timer_ms *=3D (1ULL << (32 - rapl_pkg_hw_unit[0] - 1)); } return 0; } @@ -587,12 +587,12 @@ static void __init rapl_advertise(void) int i; =20 pr_info("API unit is 2^-32 Joules, %d fixed counters, %llu ms ovfl timer\= n", - hweight32(rapl_cntr_mask), rapl_timer_ms); + hweight32(rapl_pkg_cntr_mask), rapl_timer_ms); =20 - for (i =3D 0; i < NR_RAPL_DOMAINS; i++) { - if (rapl_cntr_mask & (1 << i)) { + for (i =3D 0; i < NR_RAPL_PKG_DOMAINS; i++) { + if (rapl_pkg_cntr_mask & (1 << i)) { pr_info("hw unit of domain %s 2^-%d Joules\n", - rapl_domain_names[i], rapl_hw_unit[i]); + rapl_pkg_domain_names[i], rapl_pkg_hw_unit[i]); } } } @@ -673,71 +673,71 @@ static int __init init_rapl_pmus(struct rapl_pmus **r= apl_pmus_ptr, int rapl_pmu_ } =20 static struct rapl_model model_snb =3D { - .events =3D BIT(PERF_RAPL_PP0) | + .pkg_events =3D BIT(PERF_RAPL_PP0) | BIT(PERF_RAPL_PKG) | BIT(PERF_RAPL_PP1), .msr_power_unit =3D MSR_RAPL_POWER_UNIT, - .rapl_msrs =3D intel_rapl_msrs, + .rapl_pkg_msrs =3D intel_rapl_msrs, }; =20 static struct rapl_model model_snbep =3D { - .events =3D BIT(PERF_RAPL_PP0) | + .pkg_events =3D BIT(PERF_RAPL_PP0) | BIT(PERF_RAPL_PKG) | BIT(PERF_RAPL_RAM), .msr_power_unit =3D MSR_RAPL_POWER_UNIT, - .rapl_msrs =3D intel_rapl_msrs, + .rapl_pkg_msrs =3D intel_rapl_msrs, }; =20 static struct rapl_model model_hsw =3D { - .events =3D BIT(PERF_RAPL_PP0) | + .pkg_events =3D BIT(PERF_RAPL_PP0) | BIT(PERF_RAPL_PKG) | BIT(PERF_RAPL_RAM) | BIT(PERF_RAPL_PP1), .msr_power_unit =3D MSR_RAPL_POWER_UNIT, - .rapl_msrs =3D intel_rapl_msrs, + .rapl_pkg_msrs =3D intel_rapl_msrs, }; =20 static struct rapl_model model_hsx =3D { - .events =3D BIT(PERF_RAPL_PP0) | + .pkg_events =3D BIT(PERF_RAPL_PP0) | BIT(PERF_RAPL_PKG) | BIT(PERF_RAPL_RAM), .unit_quirk =3D RAPL_UNIT_QUIRK_INTEL_HSW, .msr_power_unit =3D MSR_RAPL_POWER_UNIT, - .rapl_msrs =3D intel_rapl_msrs, + .rapl_pkg_msrs =3D intel_rapl_msrs, }; =20 static struct rapl_model model_knl =3D { - .events =3D BIT(PERF_RAPL_PKG) | + .pkg_events =3D BIT(PERF_RAPL_PKG) | BIT(PERF_RAPL_RAM), .unit_quirk =3D RAPL_UNIT_QUIRK_INTEL_HSW, .msr_power_unit =3D MSR_RAPL_POWER_UNIT, - .rapl_msrs =3D intel_rapl_msrs, + .rapl_pkg_msrs =3D intel_rapl_msrs, }; =20 static struct rapl_model model_skl =3D { - .events =3D BIT(PERF_RAPL_PP0) | + .pkg_events =3D BIT(PERF_RAPL_PP0) | BIT(PERF_RAPL_PKG) | BIT(PERF_RAPL_RAM) | BIT(PERF_RAPL_PP1) | BIT(PERF_RAPL_PSYS), .msr_power_unit =3D MSR_RAPL_POWER_UNIT, - .rapl_msrs =3D intel_rapl_msrs, + .rapl_pkg_msrs =3D intel_rapl_msrs, }; =20 static struct rapl_model model_spr =3D { - .events =3D BIT(PERF_RAPL_PP0) | + .pkg_events =3D BIT(PERF_RAPL_PP0) | BIT(PERF_RAPL_PKG) | BIT(PERF_RAPL_RAM) | BIT(PERF_RAPL_PSYS), .unit_quirk =3D RAPL_UNIT_QUIRK_INTEL_SPR, .msr_power_unit =3D MSR_RAPL_POWER_UNIT, - .rapl_msrs =3D intel_rapl_spr_msrs, + .rapl_pkg_msrs =3D intel_rapl_spr_msrs, }; =20 static struct rapl_model model_amd_hygon =3D { - .events =3D BIT(PERF_RAPL_PKG), + .pkg_events =3D BIT(PERF_RAPL_PKG), .msr_power_unit =3D MSR_AMD_RAPL_POWER_UNIT, - .rapl_msrs =3D amd_rapl_msrs, + .rapl_pkg_msrs =3D amd_rapl_pkg_msrs, }; =20 static const struct x86_cpu_id rapl_model_match[] __initconst =3D { @@ -793,11 +793,11 @@ MODULE_DEVICE_TABLE(x86cpu, rapl_model_match); static int __init rapl_pmu_init(void) { const struct x86_cpu_id *id; - int rapl_pmu_scope =3D PERF_PMU_SCOPE_DIE; + int rapl_pkg_pmu_scope =3D PERF_PMU_SCOPE_DIE; int ret; =20 - if (rapl_pmu_is_pkg_scope()) - rapl_pmu_scope =3D PERF_PMU_SCOPE_PKG; + if (rapl_pkg_pmu_is_pkg_scope()) + rapl_pkg_pmu_scope =3D PERF_PMU_SCOPE_PKG; =20 id =3D x86_match_cpu(rapl_model_match); if (!id) @@ -805,20 +805,20 @@ static int __init rapl_pmu_init(void) =20 rapl_model =3D (struct rapl_model *) id->driver_data; =20 - rapl_msrs =3D rapl_model->rapl_msrs; + rapl_msrs =3D rapl_model->rapl_pkg_msrs; =20 - rapl_cntr_mask =3D perf_msr_probe(rapl_msrs, PERF_RAPL_MAX, - false, (void *) &rapl_model->events); + rapl_pkg_cntr_mask =3D perf_msr_probe(rapl_msrs, PERF_RAPL_PKG_EVENTS_MAX, + false, (void *) &rapl_model->pkg_events); =20 ret =3D rapl_check_hw_unit(); if (ret) return ret; =20 - ret =3D init_rapl_pmus(&rapl_pmus, rapl_pmu_scope); + ret =3D init_rapl_pmus(&rapl_pmus_pkg, rapl_pkg_pmu_scope); if (ret) return ret; =20 - ret =3D perf_pmu_register(&rapl_pmus->pmu, "power", -1); + ret =3D perf_pmu_register(&rapl_pmus_pkg->pmu, "power", -1); if (ret) goto out; =20 @@ -827,14 +827,14 @@ static int __init rapl_pmu_init(void) =20 out: pr_warn("Initialization failed (%d), disabled\n", ret); - cleanup_rapl_pmus(rapl_pmus); + cleanup_rapl_pmus(rapl_pmus_pkg); return ret; } module_init(rapl_pmu_init); =20 static void __exit intel_rapl_exit(void) { - perf_pmu_unregister(&rapl_pmus->pmu); - cleanup_rapl_pmus(rapl_pmus); + perf_pmu_unregister(&rapl_pmus_pkg->pmu); + cleanup_rapl_pmus(rapl_pmus_pkg); } module_exit(intel_rapl_exit); --=20 2.34.1