From nobody Mon Nov 25 17:38:11 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EB0121DAC90; Fri, 25 Oct 2024 10:52:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729853548; cv=none; b=aoPx2ag84cbV+JR6KCutiIVDWit8TJk6TsXKhmN7Q8ewmsHJ2fLsM8Vcij8OdJpOgrc2gNmZ3z82rBJn0oR3gstTTtLdPAu+c2trDksYhNZYZFkFrGqyv1ImUG/9gGYvdxtj2IWYw/O8V+PZGvtkzz83r/v4gFbJCDC3QJGY15k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729853548; c=relaxed/simple; bh=SkhNz5Cxy9j4StmMS3kFeTFiAuFuEeuILFkfOBbdakY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Mzk2wIDfxzgx1xY2ijksJG+sHpGK1Rd9O5gtVJW6tkGsn2kqxxIjqGZzUI55XdN2HDoZ/H4seinUxw5HtWmi9xMuzPeExhuizO00DXhs8he8h75P5D2c9rul5VUPZsAeJAaMBGO7avowxzp8UCu89xPSgYIdIfgOBc7Q9qnSZDU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 12B6E497; Fri, 25 Oct 2024 03:52:56 -0700 (PDT) Received: from VDW30FN91H.arm.com (unknown [10.57.79.117]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 144843F73B; Fri, 25 Oct 2024 03:52:23 -0700 (PDT) From: Graham Woodward To: acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com, jolsa@kernel.org, irogers@google.com, james.clark@linaro.org, mike.leach@linaro.org, leo.yan@linux.dev, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: nd@arm.com, Graham Woodward Subject: [PATCH v10 1/4] perf arm-spe: Set sample.addr to target address for instruction sample Date: Fri, 25 Oct 2024 11:52:09 +0100 Message-Id: <20241025105212.51779-2-graham.woodward@arm.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241025105212.51779-1-graham.woodward@arm.com> References: <20241025105212.51779-1-graham.woodward@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For an instruction sample, assign the target address to the field 'to_ip'. If it is a non-branch record, to_ip will be 0, presenting a non-valid target address. Signed-off-by: Graham Woodward Reviewed-by: James Clark --- tools/perf/util/arm-spe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 138ffc71b..76d41c91f 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -400,7 +400,7 @@ static int arm_spe__synth_instruction_sample(struct arm= _spe_queue *speq, =20 sample.id =3D spe_events_id; sample.stream_id =3D spe_events_id; - sample.addr =3D record->virt_addr; + sample.addr =3D record->to_ip; sample.phys_addr =3D record->phys_addr; sample.data_src =3D data_src; sample.period =3D spe->instructions_sample_period; --=20 2.40.1 From nobody Mon Nov 25 17:38:11 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AD59F1FDF90; Fri, 25 Oct 2024 10:52:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729853551; cv=none; b=MyhZLkRLE0bcpKXHQdN2CVaHw87aZ2SA0gkGkM/VpVsjmPy09JId8WJA03QYGxI78QJxQxHgPLlGwfcCaMP8N6k8xL1peA6nwPOlUnLzGLcVhVam60GgkuyVRRFG2PMA4dPnjd67BMI+ukEZEzPTwIa9evXvYdYOyQT2kYQhMGM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729853551; c=relaxed/simple; bh=+NkIU9KKnVmh+ullACqFN+6wnC1MVnt9Mw8eOxibrOE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=VU4PD2q2mMhOtMG64jMWpgDkEyoeVdnZNTDyeC+btCLb1q6MBgYpxdyf2bEWz4fPX4OWD+btmp8HxGFBxv7gHNpBeFyMBtbzWCmdjBgyRyLLAmtkpuYlAyjumdQXzYClLMzOO7zS6TBT0vkqrz6Vu1pmKu1KnyiDh5Nah06Aids= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9E7FE12FC; Fri, 25 Oct 2024 03:52:58 -0700 (PDT) Received: from VDW30FN91H.arm.com (unknown [10.57.79.117]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A71913F73B; Fri, 25 Oct 2024 03:52:26 -0700 (PDT) From: Graham Woodward To: acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com, jolsa@kernel.org, irogers@google.com, james.clark@linaro.org, mike.leach@linaro.org, leo.yan@linux.dev, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: nd@arm.com, Graham Woodward Subject: [PATCH v10 2/4] perf arm-spe: Use ARM_SPE_OP_BRANCH_ERET when synthesizing branches Date: Fri, 25 Oct 2024 11:52:10 +0100 Message-Id: <20241025105212.51779-3-graham.woodward@arm.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241025105212.51779-1-graham.woodward@arm.com> References: <20241025105212.51779-1-graham.woodward@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Instead of checking the type for just branch misses, we can instead check for the OP_BRANCH_ERET and synthesise branches as well as branch misses. Signed-off-by: Graham Woodward Reviewed-by: James Clark --- tools/perf/util/arm-spe.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 76d41c91f..d27500c53 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -69,7 +69,7 @@ struct arm_spe { u64 llc_access_id; u64 tlb_miss_id; u64 tlb_access_id; - u64 branch_miss_id; + u64 branch_id; u64 remote_access_id; u64 memory_id; u64 instructions_id; @@ -601,8 +601,8 @@ static int arm_spe_sample(struct arm_spe_queue *speq) } } =20 - if (spe->sample_branch && (record->type & ARM_SPE_BRANCH_MISS)) { - err =3D arm_spe__synth_branch_sample(speq, spe->branch_miss_id); + if (spe->sample_branch && (record->op & ARM_SPE_OP_BRANCH_ERET)) { + err =3D arm_spe__synth_branch_sample(speq, spe->branch_id); if (err) return err; } @@ -1202,12 +1202,12 @@ arm_spe_synth_events(struct arm_spe *spe, struct pe= rf_session *session) if (spe->synth_opts.branches) { spe->sample_branch =3D true; =20 - /* Branch miss */ + /* Branch */ err =3D perf_session__deliver_synth_attr_event(session, &attr, id); if (err) return err; - spe->branch_miss_id =3D id; - arm_spe_set_event_name(evlist, id, "branch-miss"); + spe->branch_id =3D id; + arm_spe_set_event_name(evlist, id, "branch"); id +=3D 1; } =20 --=20 2.40.1 From nobody Mon Nov 25 17:38:11 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 474DE2003C1; Fri, 25 Oct 2024 10:52:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729853554; cv=none; b=AQ9A/yTNCA+c4kf0FRJA/gJUkjcVkWf0qddQoijEhpVn3KR4sJ2daCcxXNcTM4ED/AqWfmITe9HgmlsSSO7XrLg9EOp0U7K5Zmo/u2OZyjwEcMMXdzvJf1IH5aBx07JoClT+V/VEp2r7u4BX9V2x/WH4BZU00QtTI2AJIMF2BAU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729853554; c=relaxed/simple; bh=zOVyKZ+ZvB/9SwbWEYIY80fMUYtlcEosf/RnEiK6BrE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=J9yUqqtIPfvGjDBgt+g2bHpMm1VkO9+wi3v9zzSgqoS5BLVMFFrROM3IQ2mc/ED9hAhg+fRwIsOPpx1wBNgcYc1IfZz6jIje7A9/gkkfYcI0Zyj4GZKEV2lfurqaxF8FOsOaEiP54iIxRdzTEVWnvRQBm9+AgwyY6bLWzhf7kCk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 36979165C; Fri, 25 Oct 2024 03:53:01 -0700 (PDT) Received: from VDW30FN91H.arm.com (unknown [10.57.79.117]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 41D993F73B; Fri, 25 Oct 2024 03:52:29 -0700 (PDT) From: Graham Woodward To: acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com, jolsa@kernel.org, irogers@google.com, james.clark@linaro.org, mike.leach@linaro.org, leo.yan@linux.dev, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: nd@arm.com, Graham Woodward Subject: [PATCH v10 3/4] perf arm-spe: Correctly set sample flags Date: Fri, 25 Oct 2024 11:52:11 +0100 Message-Id: <20241025105212.51779-4-graham.woodward@arm.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241025105212.51779-1-graham.woodward@arm.com> References: <20241025105212.51779-1-graham.woodward@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Set flags on all synthesized instruction and branch samples. Signed-off-by: Graham Woodward Reviewed-by: James Clark --- tools/perf/builtin-script.c | 1 + tools/perf/util/arm-spe.c | 17 +++++++++++++++++ tools/perf/util/event.h | 1 + 3 files changed, 19 insertions(+) diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index a644787fa..6f3db0737 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -1728,6 +1728,7 @@ static struct { {PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_TRACE_END, "tr end"}, {PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL | PERF_IP_FLAG_VMENTRY, "vmentry= "}, {PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL | PERF_IP_FLAG_VMEXIT, "vmexit"}, + {PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_BRANCH_MISS, "br miss"}, {0, NULL} }; =20 diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index d27500c53..830ab653f 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -96,6 +96,7 @@ struct arm_spe_queue { u64 timestamp; struct thread *thread; u64 period_instructions; + u32 flags; }; =20 static void arm_spe_dump(struct arm_spe *spe __maybe_unused, @@ -376,6 +377,7 @@ static int arm_spe__synth_branch_sample(struct arm_spe_= queue *speq, sample.stream_id =3D spe_events_id; sample.addr =3D record->to_ip; sample.weight =3D record->latency; + sample.flags =3D speq->flags; =20 return arm_spe_deliver_synth_event(spe, speq, event, &sample); } @@ -405,10 +407,24 @@ static int arm_spe__synth_instruction_sample(struct a= rm_spe_queue *speq, sample.data_src =3D data_src; sample.period =3D spe->instructions_sample_period; sample.weight =3D record->latency; + sample.flags =3D speq->flags; =20 return arm_spe_deliver_synth_event(spe, speq, event, &sample); } =20 +static void arm_spe__sample_flags(struct arm_spe_queue *speq) +{ + const struct arm_spe_record *record =3D &speq->decoder->record; + + speq->flags =3D 0; + if (record->op & ARM_SPE_OP_BRANCH_ERET) { + speq->flags =3D PERF_IP_FLAG_BRANCH; + + if (record->type & ARM_SPE_BRANCH_MISS) + speq->flags |=3D PERF_IP_FLAG_BRANCH_MISS; + } +} + static const struct midr_range neoverse_spe[] =3D { MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), @@ -551,6 +567,7 @@ static int arm_spe_sample(struct arm_spe_queue *speq) u64 data_src; int err; =20 + arm_spe__sample_flags(speq); data_src =3D arm_spe__synth_data_source(record, spe->midr); =20 if (spe->sample_flc) { diff --git a/tools/perf/util/event.h b/tools/perf/util/event.h index f8742e623..2744c54f4 100644 --- a/tools/perf/util/event.h +++ b/tools/perf/util/event.h @@ -66,6 +66,7 @@ enum { PERF_IP_FLAG_VMEXIT =3D 1ULL << 12, PERF_IP_FLAG_INTR_DISABLE =3D 1ULL << 13, PERF_IP_FLAG_INTR_TOGGLE =3D 1ULL << 14, + PERF_IP_FLAG_BRANCH_MISS =3D 1ULL << 15, }; =20 #define PERF_IP_FLAG_CHARS "bcrosyiABExghDt" --=20 2.40.1 From nobody Mon Nov 25 17:38:11 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9DA5D201018; Fri, 25 Oct 2024 10:52:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729853556; cv=none; b=NOyjArtmTPvnkNVWv3rmFM6Fsyd7hUCnMDo5YDvQzVzIr5BSJTXUy3pO0Q/h6Iutn0k3ovzqhUPY7gSa1uv2KKev+UUnISMZySJqPvr6JAIPCpnr7CV2RZ+zcvwoXbNyzrH5hPATdgAW6Jfny82yXOvKkTWiitb2wbpUyNyYbOU= ARC-Message-Signature: i=1; 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Fri, 25 Oct 2024 03:52:31 -0700 (PDT) From: Graham Woodward To: acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com, jolsa@kernel.org, irogers@google.com, james.clark@linaro.org, mike.leach@linaro.org, leo.yan@linux.dev, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: nd@arm.com, Graham Woodward Subject: [PATCH v10 4/4] perf arm-spe: Update --itrace help text Date: Fri, 25 Oct 2024 11:52:12 +0100 Message-Id: <20241025105212.51779-5-graham.woodward@arm.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241025105212.51779-1-graham.woodward@arm.com> References: <20241025105212.51779-1-graham.woodward@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The --itrace help now needs updating to reflect that the --itrace=3Db argument sythesises branches as well as branch misses. Signed-off-by: Graham Woodward Reviewed-by: James Clark --- tools/perf/Documentation/itrace.txt | 2 +- tools/perf/Documentation/perf-arm-spe.txt | 2 +- tools/perf/util/auxtrace.h | 3 +-- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/tools/perf/Documentation/itrace.txt b/tools/perf/Documentation= /itrace.txt index 19cc179be..40476b227 100644 --- a/tools/perf/Documentation/itrace.txt +++ b/tools/perf/Documentation/itrace.txt @@ -1,6 +1,6 @@ i synthesize instructions events y synthesize cycles events - b synthesize branches events (branch misses for Arm SPE) + b synthesize branches events c synthesize branches events (calls only) r synthesize branches events (returns only) x synthesize transactions events diff --git a/tools/perf/Documentation/perf-arm-spe.txt b/tools/perf/Documen= tation/perf-arm-spe.txt index 0a3eda482..de2b0b479 100644 --- a/tools/perf/Documentation/perf-arm-spe.txt +++ b/tools/perf/Documentation/perf-arm-spe.txt @@ -187,7 +187,7 @@ groups: 7 llc-access 2 tlb-miss 1K tlb-access - 36 branch-miss + 36 branch 0 remote-access 900 memory =20 diff --git a/tools/perf/util/auxtrace.h b/tools/perf/util/auxtrace.h index a1895a4f5..dddaf4f3f 100644 --- a/tools/perf/util/auxtrace.h +++ b/tools/perf/util/auxtrace.h @@ -75,7 +75,6 @@ enum itrace_period_type { * (not fully accurate, since CYC packets are only emitted * together with other events, such as branches) * @branches: whether to synthesize 'branches' events - * (branch misses only for Arm SPE) * @transactions: whether to synthesize events for transactions * @ptwrites: whether to synthesize events for ptwrites * @pwr_events: whether to synthesize power events @@ -650,7 +649,7 @@ bool auxtrace__evsel_is_auxtrace(struct perf_session *s= ession, #define ITRACE_HELP \ " i[period]: synthesize instructions events\n" \ " y[period]: synthesize cycles events (same period as i)\n" \ -" b: synthesize branches events (branch misses for Arm SPE)\n" \ +" b: synthesize branches events\n" \ " c: synthesize branches events (calls only)\n" \ " r: synthesize branches events (returns only)\n" \ " x: synthesize transactions events\n" \ --=20 2.40.1