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charset="utf-8" From: Stefan Eichenberger By default we expect all i2c nodes to be single-master, we do not have any module or carrier board that uses multi-master mode on any i2c controller. With this property set, we benefit from optimisations made exclusively for single-masters. Signed-off-by: Stefan Eichenberger --- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/= boot/dts/freescale/imx8mm-verdin.dtsi index 5fa3959141911..95d5d2333ca1e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -367,6 +367,7 @@ &i2c1 { pinctrl-1 =3D <&pinctrl_i2c1_gpio>; scl-gpios =3D <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios =3D <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; status =3D "okay"; =20 pca9450: pmic@25 { @@ -561,6 +562,7 @@ &i2c2 { pinctrl-1 =3D <&pinctrl_i2c2_gpio>; scl-gpios =3D <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios =3D <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; status =3D "disabled"; }; =20 @@ -574,6 +576,7 @@ &i2c3 { pinctrl-1 =3D <&pinctrl_i2c3_gpio>; scl-gpios =3D <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios =3D <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; }; =20 /* Verdin I2C_1 */ @@ -584,6 +587,7 @@ &i2c4 { pinctrl-1 =3D <&pinctrl_i2c4_gpio>; scl-gpios =3D <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios =3D <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; =20 gpio_expander_21: gpio-expander@21 { compatible =3D "nxp,pcal6416"; --=20 2.43.0 From nobody Mon Nov 25 17:41:08 2024 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADB731D90C8; Fri, 25 Oct 2024 09:59:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729850364; cv=none; b=tmcZ+QNs+tGRPHi/8wPmK7SY4ssv0UeZAZWKxmqFo/8RiufNLUQ6ZmSsi4QdfJV42NjqszWPj/1CKEhwROc8qpMRq/z8ookfyIHAraOshgCHFJ2uAXwxgsdEMwOKXMfz/fehsHRsFYvro04AFjEyO/hndBVnEvUZTxRP/W8k2Eo= ARC-Message-Signature: i=1; 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Fri, 25 Oct 2024 02:59:20 -0700 (PDT) From: Stefan Eichenberger To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, francesco.dolcini@toradex.com Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Stefan Eichenberger Subject: [PATCH v1 2/2] arm64: dts: imx8mp-verdin: add single-master property to all i2c nodes Date: Fri, 25 Oct 2024 11:58:03 +0200 Message-ID: <20241025095915.22313-3-eichest@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241025095915.22313-1-eichest@gmail.com> References: <20241025095915.22313-1-eichest@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stefan Eichenberger By default we expect all i2c nodes to be single-master, we do not have any module or carrier board that uses multi-master mode on any i2c controller. With this property set, we benefit from optimisations made exclusively for single-masters. Signed-off-by: Stefan Eichenberger --- arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/= boot/dts/freescale/imx8mp-verdin.dtsi index a19ad5ee7f792..323b45bac281e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -478,6 +478,7 @@ &i2c1 { pinctrl-1 =3D <&pinctrl_i2c1_gpio>; scl-gpios =3D <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios =3D <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; status =3D "okay"; =20 pca9450: pmic@25 { @@ -669,6 +670,7 @@ &i2c2 { pinctrl-1 =3D <&pinctrl_i2c2_gpio>; scl-gpios =3D <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios =3D <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; =20 atmel_mxt_ts_mezzanine: touch-mezzanine@4a { compatible =3D "atmel,maxtouch"; @@ -690,6 +692,7 @@ &i2c3 { pinctrl-1 =3D <&pinctrl_i2c3_gpio>; scl-gpios =3D <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios =3D <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; }; =20 /* Verdin I2C_1 */ @@ -700,6 +703,7 @@ &i2c4 { pinctrl-1 =3D <&pinctrl_i2c4_gpio>; scl-gpios =3D <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios =3D <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; =20 gpio_expander_21: gpio-expander@21 { compatible =3D "nxp,pcal6416"; @@ -788,6 +792,7 @@ &i2c5 { pinctrl-1 =3D <&pinctrl_i2c5_gpio>; scl-gpios =3D <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios =3D <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; }; =20 /* Verdin PCIE_1 */ --=20 2.43.0