From nobody Mon Nov 25 17:22:52 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70A641C9EDC for ; Fri, 25 Oct 2024 08:32:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729845122; cv=none; b=MtftZJbWvdYJQNq9zPjhidg/d34ltzWHFzcp2wNoLr0dsL0Tfxgx44hYcrvoYPniPYJjHqtWOJ9UAHFjYReFwXl17vMEKvPRzYCYVCJGphkwxtepx+6POTpR2sp8A+L6KOp5aZb0u5iVk4/KyNQGtOY8uvOhlgcxP28T4NbHTbc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729845122; c=relaxed/simple; bh=IinrIYb3AaQ6QaOFLZVDE90aCYUfecmzPpdelo4b0TE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lgWQ3OT61Iz+YxT32AYshEuN0w6pbEyyllOkjyLf1IivijWUitQtCFM24J3F1lcW0io24uEVTQuUQNJZYS8hkbjCSavKGmi5HVGAkYXF4jIsQh2ae4MfwohRHdpl8TlIi1Z82zVw7fvMooKH0qkFnO7PQGBbsHwrebd7Yi7gUbM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=Z4CPxdB6; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Z4CPxdB6" X-UUID: 921bddcc92ab11efb88477ffae1fc7a5-20241025 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=jHk7k0mLNr2tL+X1mT3LjPHy3SzInMKuWg8T+fWq1Bs=; b=Z4CPxdB6x9O2woEeRVDZeQlG06ZZl9nQlyV3vTo5Y4nVAdCk1E0rmr8Y/fR3cVTil/l5KCfjhH/ZvV0HSq+vPRA+zS1atyqGw43nIde/Wi7snaqMr7bwrrn+mdzmRzrzmq3h8eCa80hg8NMZPyRAS8Q/JqHBywC24tqL/gdYGuk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.42,REQID:181564af-7d9d-4357-a404-6f0b10386860,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:b0fcdc3,CLOUDID:ca9d192e-a7a0-4b06-8464-80be82133975,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULS X-UUID: 921bddcc92ab11efb88477ffae1fc7a5-20241025 Received: from mtkmbs09n2.mediatek.inc [(172.21.101.94)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1432290000; Fri, 25 Oct 2024 16:31:46 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 25 Oct 2024 16:31:44 +0800 Received: from mszsdclx1211.gcn.mediatek.inc (10.16.7.31) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 25 Oct 2024 16:31:44 +0800 From: Liankun Yang To: , , , , , , , , , , , , , , , CC: , , , Subject: [PATCH v2 1/3] drm/mediatek: Fix YCbCr422 color format issue for DP Date: Fri, 25 Oct 2024 16:28:27 +0800 Message-ID: <20241025083036.8829-2-liankun.yang@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241025083036.8829-1-liankun.yang@mediatek.com> References: <20241025083036.8829-1-liankun.yang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" Setting up misc0 for Pixel Encoding Format. According to the definition of YCbCr in spec 1.2a Table 2-96, 0x1 << 1 should be written to the register. Use switch case to distinguish RGB, YCbCr422, and unsupported color formats. Fixes: f70ac097a2cf ("drm/mediatek: Add MT8195 Embedded DisplayPort driver") Signed-off-by: Liankun Yang --- Change in V2 - Modify the value written to the register Per suggestion from the previous thread: https://patchwork.kernel.org/project/linux-mediatek/patch/20240510021810.19= 302-1-liankun.yang@mediatek.com/ --- drivers/gpu/drm/mediatek/mtk_dp.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/m= tk_dp.c index f0f6f402994a..613e1c842478 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp.c +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -460,18 +460,16 @@ static int mtk_dp_set_color_format(struct mtk_dp *mtk= _dp, enum dp_pixelformat color_format) { u32 val; - - /* update MISC0 */ - mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3034, - color_format << DP_TEST_COLOR_FORMAT_SHIFT, - DP_TEST_COLOR_FORMAT_MASK); + u32 misc0_color; =20 switch (color_format) { case DP_PIXELFORMAT_YUV422: val =3D PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR422; 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charset="utf-8" Fix dp mode valid issue to avoid abnormal display of limit state. After DP passes link training, it can express the lane count of the current link status is good. Calculate the maximum bandwidth supported by DP using the current lane count. The color format will select the best one based on the bandwidth requirements of the current timing mode. If the current timing mode uses RGB and meets the DP link bandwidth requirements, RGB will be used. If the timing mode uses RGB but does not meet the DP link bandwidthi requirements, it will continue to check whether YUV422 meetsi the DP link bandwidth. FEC overhead is approximately 2.4% from DP 1.4a spec 2.2.1.4.2. The down-spread amplitude shall either be disabled (0.0%) or up to 0.5% from 1.4a 3.5.2.6. Add up to approximately 3% total overhead. Because rate is already divided by 10, mode->clock does not need to be multiplied by 10. Fixes: f70ac097a2cf ("drm/mediatek: Add MT8195 Embedded DisplayPort driver") Signed-off-by: Liankun Yang --- Change in V2: - Adjust the writing style. - Add instructions. --- drivers/gpu/drm/mediatek/mtk_dp.c | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/m= tk_dp.c index 613e1c842478..ae4807823a5c 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp.c +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -2328,12 +2328,19 @@ mtk_dp_bridge_mode_valid(struct drm_bridge *bridge, { struct mtk_dp *mtk_dp =3D mtk_dp_from_bridge(bridge); u32 bpp =3D info->color_formats & DRM_COLOR_FORMAT_YCBCR422 ? 16 : 24; - u32 rate =3D min_t(u32, drm_dp_max_link_rate(mtk_dp->rx_cap) * - drm_dp_max_lane_count(mtk_dp->rx_cap), - drm_dp_bw_code_to_link_rate(mtk_dp->max_linkrate) * - mtk_dp->max_lanes); + u32 lane_count_min =3D mtk_dp->train_info.lane_count; + u32 rate =3D drm_dp_bw_code_to_link_rate(mtk_dp->train_info.link_rate) * + lane_count_min; =20 - if (rate < mode->clock * bpp / 8) + /* + *FEC overhead is approximately 2.4% from DP 1.4a spec 2.2.1.4.2. + *The down-spread amplitude shall either be disabled (0.0%) or up + *to 0.5% from 1.4a 3.5.2.6. Add up to approximately 3% total overhead. + * + *Because rate is already divided by 10, + *mode->clock does not need to be multiplied by 10 + */ + if ((rate * 97 / 100) < (mode->clock * bpp / 8)) return MODE_CLOCK_HIGH; =20 return MODE_OK; @@ -2374,10 +2381,9 @@ static u32 *mtk_dp_bridge_atomic_get_input_bus_fmts(= struct drm_bridge *bridge, struct drm_display_mode *mode =3D &crtc_state->adjusted_mode; struct drm_display_info *display_info =3D &conn_state->connector->display_info; - u32 rate =3D min_t(u32, drm_dp_max_link_rate(mtk_dp->rx_cap) * - drm_dp_max_lane_count(mtk_dp->rx_cap), - drm_dp_bw_code_to_link_rate(mtk_dp->max_linkrate) * - mtk_dp->max_lanes); + u32 lane_count_min =3D mtk_dp->train_info.lane_count; + u32 rate =3D drm_dp_bw_code_to_link_rate(mtk_dp->train_info.link_rate) * + lane_count_min; =20 *num_input_fmts =3D 0; =20 @@ -2386,8 +2392,8 @@ static u32 *mtk_dp_bridge_atomic_get_input_bus_fmts(s= truct drm_bridge *bridge, * datarate of YUV422 and sink device supports YUV422, we output YUV422 * format. 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charset="utf-8" By adjusting the order of link training and relocating it to HPD, link training can identify the usability of each lane in the current link. It also supports handling signal instability and weakness due to environmental issues, enabling the acquisition of a stable bandwidth for the current link. Subsequently, DP work can proceed based on the actual maximum bandwidth. It should training in the hpd event thread. Check the mode with lane count and link rate of training. Signed-off-by: Liankun Yang --- - Adjust DP training timing. - Adjust parse capabilities timing. - Add power on/off for connect/disconnect --- drivers/gpu/drm/mediatek/mtk_dp.c | 37 +++++++++++++++++-------------- 1 file changed, 20 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/m= tk_dp.c index ae4807823a5c..e87f6f52bcce 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp.c +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -1873,6 +1873,7 @@ static irqreturn_t mtk_dp_hpd_event_thread(int hpd, v= oid *dev) struct mtk_dp *mtk_dp =3D dev; unsigned long flags; u32 status; + int ret; =20 if (mtk_dp->need_debounce && mtk_dp->train_info.cable_plugged_in) msleep(100); @@ -1891,9 +1892,28 @@ static irqreturn_t mtk_dp_hpd_event_thread(int hpd, = void *dev) memset(&mtk_dp->info.audio_cur_cfg, 0, sizeof(mtk_dp->info.audio_cur_cfg)); =20 + mtk_dp->enabled =3D false; + /* power off aux */ + mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, + DP_PWR_STATE_BANDGAP_TPLL, + DP_PWR_STATE_MASK); + mtk_dp->need_debounce =3D false; mod_timer(&mtk_dp->debounce_timer, jiffies + msecs_to_jiffies(100) - 1); + } else { + mtk_dp_aux_panel_poweron(mtk_dp, true); + + ret =3D mtk_dp_parse_capabilities(mtk_dp); + if (ret) + drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n"); + + /* Training */ + ret =3D mtk_dp_training(mtk_dp); + if (ret) + drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret); + + mtk_dp->enabled =3D true; } } =20 @@ -2060,16 +2080,6 @@ static const struct drm_edid *mtk_dp_edid_read(struc= t drm_bridge *bridge, =20 drm_edid =3D drm_edid_read_ddc(connector, &mtk_dp->aux.ddc); =20 - /* - * Parse capability here to let atomic_get_input_bus_fmts and - * mode_valid use the capability to calculate sink bitrates. - */ - if (mtk_dp_parse_capabilities(mtk_dp)) { - drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n"); - drm_edid_free(drm_edid); - drm_edid =3D NULL; - } - if (drm_edid) { /* * FIXME: get rid of drm_edid_raw() @@ -2263,13 +2273,6 @@ static void mtk_dp_bridge_atomic_enable(struct drm_b= ridge *bridge, =20 mtk_dp_aux_panel_poweron(mtk_dp, true); =20 - /* Training */ - ret =3D mtk_dp_training(mtk_dp); - if (ret) { - drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret); - goto power_off_aux; - } - ret =3D mtk_dp_video_config(mtk_dp); if (ret) goto power_off_aux; --=20 2.45.2