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charset="utf-8" On i.MX95, the MQS module in Always-on (AON) domain only can be accessed by System Controller Management Interface (SCMI) MISC Protocol. So define a specific regmap_config for the case. Signed-off-by: Shengjiu Wang --- changes in v2: - fix compile issue when IMX_SCMI_MISC_DRV=3Dm but SND_SOC_FSL_MQS=3Dy sound/soc/fsl/Kconfig | 1 + sound/soc/fsl/fsl_mqs.c | 41 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig index bff9c6bda344..698afae46918 100644 --- a/sound/soc/fsl/Kconfig +++ b/sound/soc/fsl/Kconfig @@ -31,6 +31,7 @@ config SND_SOC_FSL_MQS tristate "Medium Quality Sound (MQS) module support" depends on SND_SOC_FSL_SAI select REGMAP_MMIO + select IMX_SCMI_MISC_DRV if IMX_SCMI_MISC_EXT !=3Dn help Say Y if you want to add Medium Quality Sound (MQS) support for the Freescale CPUs. diff --git a/sound/soc/fsl/fsl_mqs.c b/sound/soc/fsl/fsl_mqs.c index 145f9ca15e43..0513e9e8402e 100644 --- a/sound/soc/fsl/fsl_mqs.c +++ b/sound/soc/fsl/fsl_mqs.c @@ -6,6 +6,7 @@ // Copyright 2019 NXP =20 #include +#include #include #include #include @@ -74,6 +75,29 @@ struct fsl_mqs { #define FSL_MQS_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) #define FSL_MQS_FORMATS SNDRV_PCM_FMTBIT_S16_LE =20 +static int fsl_mqs_sm_read(void *context, unsigned int reg, unsigned int *= val) +{ + struct fsl_mqs *mqs_priv =3D context; + int num =3D 1; + + if (IS_ENABLED(CONFIG_IMX_SCMI_MISC_DRV) && + mqs_priv->soc->ctrl_off =3D=3D reg) + return scmi_imx_misc_ctrl_get(SCMI_IMX_CTRL_MQS1_SETTINGS, &num, val); + + return -EINVAL; +}; + +static int fsl_mqs_sm_write(void *context, unsigned int reg, unsigned int = val) +{ + struct fsl_mqs *mqs_priv =3D context; + + if (IS_ENABLED(CONFIG_IMX_SCMI_MISC_DRV) && + mqs_priv->soc->ctrl_off =3D=3D reg) + return scmi_imx_misc_ctrl_set(SCMI_IMX_CTRL_MQS1_SETTINGS, val); + + return -EINVAL; +}; + static int fsl_mqs_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) @@ -188,6 +212,13 @@ static const struct regmap_config fsl_mqs_regmap_confi= g =3D { .cache_type =3D REGCACHE_NONE, }; =20 +static const struct regmap_config fsl_mqs_sm_regmap =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_read =3D fsl_mqs_sm_read, + .reg_write =3D fsl_mqs_sm_write, +}; + static int fsl_mqs_probe(struct platform_device *pdev) { struct device_node *np =3D pdev->dev.of_node; @@ -219,6 +250,16 @@ static int fsl_mqs_probe(struct platform_device *pdev) dev_err(&pdev->dev, "failed to get gpr regmap\n"); return PTR_ERR(mqs_priv->regmap); } + } else if (mqs_priv->soc->type =3D=3D TYPE_REG_SM) { + mqs_priv->regmap =3D devm_regmap_init(&pdev->dev, + NULL, + mqs_priv, + &fsl_mqs_sm_regmap); + if (IS_ERR(mqs_priv->regmap)) { + dev_err(&pdev->dev, "failed to init regmap: %ld\n", + PTR_ERR(mqs_priv->regmap)); + return PTR_ERR(mqs_priv->regmap); + } } else { regs =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(regs)) --=20 2.34.1