From nobody Mon Nov 25 18:48:10 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9206518C344; Fri, 25 Oct 2024 03:56:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729828570; cv=none; b=L1aHXLhTFXyWG7QVl6rGgF72ZudCO1UtCfi5frYOxYvh52jZpVkKypC+Ie/C/5rN8W8WUA1XhhR3Sx9XTjAFN0jIdJrRI7JRu0VIs2ZxaZRYJFvBMF9LPy7UB7r+uTNuS/BnCZYLvBB/PFVIz1wKlC7QjerKF6mLkNKmNU8nEL0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729828570; c=relaxed/simple; bh=wBY/ArNkYkS4W/z2HYYE9M2FYlK4rPBnpcMMyfziPMo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=G5EE7hDtjW1SqVj4stXUY9LYJuL7CLcXpFXIozWM0eNN8Wwxw/FSRL6eb6lSSCkjuiOeRdOMfFZPSCDTj0IsQFcFQsdw5blF50QX49x07OJmwWYMOfyZ8pwO1dbXyVKgLm2bbJaeqLE8WTof4oo3qzJO3hWsB2PtWX0wP80XFRc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=GOycGYMA; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="GOycGYMA" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49P0mmHe004988; Fri, 25 Oct 2024 03:55:52 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= yyuCjmhe/vvzg0nAAl2KSI4Pk5szrvCWzQBWktp8hf8=; b=GOycGYMAPUpoF+OV cjl2B4clMaFYZ5k8b4r0rljWNx2I29I/01G3730+HlQUlcxuJsdc74nK4+95Nzeb UET2f3TjnIJUhVW/lDPiI5bhY9vuCJaNvxE7fgWAabBFXwE7oRjlDWZemLxmH3w/ OFaTJW9VUtFCzOGDC9EtWA8TwA02QrRMzljEdkTdFfqCKo+MUS/DUeYYg6CXqaZC SOWF2dPLG/Jh5olFrUjJnTwAhN5tflER9KqbHJdJ4BhdcRLse0Pdqsl5qrFMhGnT NiarFZ1ivID+ZQtJ3+CtFxPXUOQXlDDT2MMh+n432G2VL7GzqTMvCz4szZpsWngY WqcbAw== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42em687m24-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 03:55:51 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49P3toUO007980 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 03:55:50 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 24 Oct 2024 20:55:42 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH v8 1/7] clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574 Date: Fri, 25 Oct 2024 09:25:14 +0530 Message-ID: <20241025035520.1841792-2-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025035520.1841792-1-quic_mmanikan@quicinc.com> References: <20241025035520.1841792-1-quic_mmanikan@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 8CtkC0CVFxaP_LK095XCtXGavJi0QBc9 X-Proofpoint-GUID: 8CtkC0CVFxaP_LK095XCtXGavJi0QBc9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 priorityscore=1501 adultscore=0 bulkscore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=913 impostorscore=0 suspectscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410250026 Content-Type: text/plain; charset="utf-8" From: Devi Priya Add support for NSS Huayra alpha pll found on ipq9574 SoCs. Programming sequence is the same as that of Huayra type Alpha PLL, so we can re-use the same. Reviewed-by: Dmitry Baryshkov Signed-off-by: Devi Priya Signed-off-by: Manikanta Mylavarapu --- Changes in V8: - No change drivers/clk/qcom/clk-alpha-pll.c | 11 +++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 1 + 2 files changed, 12 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-= pll.c index be9bee6ab65f..49687512184b 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -267,6 +267,17 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] =3D { [PLL_OFF_OPMODE] =3D 0x30, [PLL_OFF_STATUS] =3D 0x3c, }, + [CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] =3D { + [PLL_OFF_L_VAL] =3D 0x04, + [PLL_OFF_ALPHA_VAL] =3D 0x08, + [PLL_OFF_TEST_CTL] =3D 0x0c, + [PLL_OFF_TEST_CTL_U] =3D 0x10, + [PLL_OFF_USER_CTL] =3D 0x14, + [PLL_OFF_CONFIG_CTL] =3D 0x18, + [PLL_OFF_CONFIG_CTL_U] =3D 0x1c, + [PLL_OFF_STATUS] =3D 0x20, + }, + }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); =20 diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-= pll.h index 55eca04b23a1..c6d1b8429f95 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -32,6 +32,7 @@ enum { CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, CLK_ALPHA_PLL_TYPE_STROMER, CLK_ALPHA_PLL_TYPE_STROMER_PLUS, + CLK_ALPHA_PLL_TYPE_NSS_HUAYRA, CLK_ALPHA_PLL_TYPE_MAX, }; =20 --=20 2.34.1 From nobody Mon Nov 25 18:48:10 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95CCF1DFD8; Fri, 25 Oct 2024 04:11:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729829509; cv=none; b=EClP3eiw78jcfyiyg69OD+Q/jyqjGWZFDbhKkDasC5ttE17jFe5uEpsGLXqI8blWdyh7xuZll98mtsMN7h4SxGz7cUDHwwhEStu8YZTMasmJlrUioYGGHIP16MnOwu4C9ZKlyt8P/f3FYbReqV+71VyfYfmj9iMFJq4oPL2F1tA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729829509; c=relaxed/simple; bh=gAsx3/kBC32Fwd7psSxhcq4OCbrCBhM6KQvnOzzIuNA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gSlsySnYfcDb0/FYSeLPUQJ0kJFibYOu2XD2+mvewU8soV5i2CP2LLNqFM2G52AdEDDqxBA6DhPyUUPmSwMzAEyxS9MpO7MnlpIyvKmL4Knlh3LMayhswb60q4U4MBB2WnPo7hH5ookXrBgsMciN5j5KXpQbeZt9UgvUmf4TeyY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=o6NwZFzc; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="o6NwZFzc" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49OL32Ko018568; Fri, 25 Oct 2024 03:55:58 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= HwMWhgwUsncIvAoBDC7Sn1syFgKztW5s/fFhnZ/XXvc=; b=o6NwZFzcmIKkNfXk WQrHYaeSPxDZGqNSNdBaHeHXu1AjVMIaeYEeNLBbhS3cUHoTsECeerCfFbu0deSK 0H4SCYFcOAnM+KD4ELG30kzoQBxZAyRdGtRvBvL6k90QqfX7RYZnCucDpJsZqcWe NoFMtERLarALlXD/Bcl9rz22njn86aeZT+WlpHngVNTy49JNqK1ReW/ULDjisYKc FgkmcnF5Nf0xAQrTKpDP3oqZBw3T32Ontan0k6/Phx/3jtQ6Dlosh5EfCsHkxffy My7cmhX11yciBEZ5iPeKeVo+BwNtKzIpW7ufa8enLoGLbHkKeaVi5Bw1QwFeEwqt Z4yYoQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42em66fp88-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 03:55:58 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49P3tvQB000682 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 03:55:57 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 24 Oct 2024 20:55:50 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH v8 2/7] dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX Date: Fri, 25 Oct 2024 09:25:15 +0530 Message-ID: <20241025035520.1841792-3-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025035520.1841792-1-quic_mmanikan@quicinc.com> References: <20241025035520.1841792-1-quic_mmanikan@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 6_2x5gh4TVYwVh4gAYn0Vlr_Rdb26_tu X-Proofpoint-GUID: 6_2x5gh4TVYwVh4gAYn0Vlr_Rdb26_tu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 phishscore=0 impostorscore=0 malwarescore=0 mlxlogscore=999 suspectscore=0 clxscore=1015 mlxscore=0 bulkscore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410250026 Content-Type: text/plain; charset="utf-8" From: Devi Priya Add the definition for GPLL0_OUT_AUX clock. Acked-by: Krzysztof Kozlowski Signed-off-by: Devi Priya Signed-off-by: Manikanta Mylavarapu --- Changes in V8: - No change include/dt-bindings/clock/qcom,ipq9574-gcc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bind= ings/clock/qcom,ipq9574-gcc.h index 52123c5a09fa..05ef3074c9da 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -220,4 +220,5 @@ #define GCC_PCIE1_PIPE_CLK 211 #define GCC_PCIE2_PIPE_CLK 212 #define GCC_PCIE3_PIPE_CLK 213 +#define GPLL0_OUT_AUX 214 #endif --=20 2.34.1 From nobody Mon Nov 25 18:48:10 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACB8618C009; Fri, 25 Oct 2024 03:56:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729828586; cv=none; b=DaBDQbi4hN5EcKOsyyUbpVtHk5xgWJwz+IVA0POesJu13rD1/couuxQkU8Uh1Lj+ihdbbLwv59U5piL6ylW1+HhzXUPqNVBQKZNRbgL/rUgmiBk2vtDYIxoLi2ffRW8LOwtbCC9lHrcWhF3WiV2GiQUOp06pL1J43pthncNCVlg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729828586; c=relaxed/simple; bh=pjkDNtLRl1TxZ8GlevZCOWRgBrcRw/LC4IONqX6y+0U=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NWK2TINl0Hiz9fd5hMD40a/7ek7ouBS9IvPXzJKTBCI4y/R23uJ+dqof9Hv2DeE8OdS881LABF3at5Fmbb8hGEL50HSwPDzPIwzUsahwcV2wjdC+Y4kVe44OBrEdVtMZf+Hvo2kMS7CmB6fGaOCCZuAVTtJqKbj3sDsbRUDNxBs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=aW6XBAgj; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="aW6XBAgj" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49OJn7JL018657; Fri, 25 Oct 2024 03:56:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= QysM8CLXknciTUXr+RGhpBn14VHz11If4slYyVFUnkg=; b=aW6XBAgjeo3lzoAw /5lIR5dgX/YMzN4g0CFjUvlWzQV8vD4/cpXUpEZTlYgWSI5XlxQJ59DAnJaehyzf V6htq1rKu+cJkD2HVrk/HRwB1NmYpn/reJ/i7xItG3+bynHr0x0OI1WGLZwn9QQH EstF2EKYg0a1DABDw+KX9NTty+A11+WLEJWauP++pyis0Gou3ibTFL51v7cPbT2q YWqjLvlvyPAPy9p5wqw86ZAPQx9P/Iz3V+sFIzi052cBqXfyIwm6qh3G1A5557ta tv5ijq9tj/H3l2yClY/lGRZVutmqzeFmA+sI3Hh6YpwXuj9cvkptsElsPjb5vHgj UZeLjg== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42em66fp8f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 03:56:06 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49P3u51x015540 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 03:56:05 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 24 Oct 2024 20:55:57 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH v8 3/7] clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock Date: Fri, 25 Oct 2024 09:25:16 +0530 Message-ID: <20241025035520.1841792-4-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025035520.1841792-1-quic_mmanikan@quicinc.com> References: <20241025035520.1841792-1-quic_mmanikan@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Z6_UI6uDbeIle-h0t14nPPUY1UawDfkV X-Proofpoint-GUID: Z6_UI6uDbeIle-h0t14nPPUY1UawDfkV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 phishscore=0 impostorscore=0 malwarescore=0 mlxlogscore=999 suspectscore=0 clxscore=1015 mlxscore=0 bulkscore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410250026 Content-Type: text/plain; charset="utf-8" From: Devi Priya Add support for gpll0_out_aux clock which acts as the parent for certain networking subsystem (nss) clocks. Reviewed-by: Dmitry Baryshkov Signed-off-by: Devi Priya Signed-off-by: Manikanta Mylavarapu --- Changes in V8: - No change drivers/clk/qcom/gcc-ipq9574.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index 0405a2473842..08921bff46da 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -108,6 +108,20 @@ static struct clk_alpha_pll_postdiv gpll0 =3D { }, }; =20 +static struct clk_alpha_pll_postdiv gpll0_out_aux =3D { + .offset =3D 0x20000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll0_out_aux", + .parent_hws =3D (const struct clk_hw *[]) { + &gpll0_main.clkr.hw + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_ro_ops, + }, +}; + static struct clk_alpha_pll gpll4_main =3D { .offset =3D 0x22000, .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], @@ -4222,6 +4236,7 @@ static struct clk_regmap *gcc_ipq9574_clks[] =3D { [GCC_PCIE1_PIPE_CLK] =3D &gcc_pcie1_pipe_clk.clkr, [GCC_PCIE2_PIPE_CLK] =3D &gcc_pcie2_pipe_clk.clkr, [GCC_PCIE3_PIPE_CLK] =3D &gcc_pcie3_pipe_clk.clkr, + [GPLL0_OUT_AUX] =3D &gpll0_out_aux.clkr, }; =20 static const struct qcom_reset_map gcc_ipq9574_resets[] =3D { --=20 2.34.1 From nobody Mon Nov 25 18:48:10 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8959718CC01; Fri, 25 Oct 2024 03:56:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729828597; cv=none; b=dqN5uKfp04FFJ8kis+nmXML/ZvppAtWO265W8LuuH78kMRVgoepNht0kFb76nduRT51wTbW4+IhUnfxTpeIjI1kO6uIHiMsIfSVF6AHylmT5Z7TH4q03C3igHKLLcnzmd2jlVyCeY/zIwG1AcuS8weCpVCe0RVKPMXEO6YMq26I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729828597; c=relaxed/simple; bh=swVVN8vPbzXywiN52yh2JmYlsgpKtyvDgt65TZIwOec=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jI7SZnb2HYXNHxceYzpXRej8mBbemEkIF/5JRKsebK9KeOBxvmaxJ0hRYcWhmRz7qSRDH1EBTyUR+CwmLESh8V3LXEQUYInoEw8KSQUMjxuVBevn39wDM+v/zl9dJCezfB3kVL8NmkynKzMSiGHgEchOqA+Y/2MW1DquceXbJno= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=l7gfeqba; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="l7gfeqba" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49P0DSNN025438; Fri, 25 Oct 2024 03:56:13 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= L1WOq3Db69yLtp90khtdv5jLW2K0MtuqUF39tiHvR+E=; b=l7gfeqbaaTgLgnnf PkrO3v+BZMCLj1sm0VqMjmaTUz8AqQtwNN8H0tsIFzzUMb7T6Y9Xzv7rAzrdB/CM Hj0A6gJIYntNAn79R6uWApVlEAQIui0dsvy74FXFP7OapD4tV2USKl/MSo+gEStC QquGz1oY99hLigw+JDFO3dcBWdkFpVe4ms0182VKm+K0eZv9Y4Eq6391XKEKV7t0 1DUZ0edVKQlnocfdhb3T1nzyzpXVlz5mFJMVFywX5aDckekh9LVyvtzfIwWupjnj S68ZHu3rJaEXIMtCCycFWV7nraRV0LZs6Skz0MKjMtcoprjwhKGoMpOM/D57/RPU +l8ACA== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42em40fn8k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 03:56:13 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49P3uCfI008810 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 03:56:12 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 24 Oct 2024 20:56:05 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH v8 4/7] dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions Date: Fri, 25 Oct 2024 09:25:17 +0530 Message-ID: <20241025035520.1841792-5-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025035520.1841792-1-quic_mmanikan@quicinc.com> References: <20241025035520.1841792-1-quic_mmanikan@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: stLe7iJwgHsai7vdGwHJ-c2jBOdlWMX8 X-Proofpoint-GUID: stLe7iJwgHsai7vdGwHJ-c2jBOdlWMX8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 impostorscore=0 spamscore=0 phishscore=0 mlxlogscore=999 lowpriorityscore=0 clxscore=1015 malwarescore=0 bulkscore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410250026 Content-Type: text/plain; charset="utf-8" From: Devi Priya Add NSSCC clock and reset definitions for ipq9574. Signed-off-by: Devi Priya Signed-off-by: Manikanta Mylavarapu Reviewed-by: Krzysztof Kozlowski --- Changes in V8: - Replace bias_pll_cc_clk, bias_pll_ubi_nc_clk with CMN_PLL NSS_1200MHZ_CLK and PPE_353MHZ_CLK - Remove bias_pll_nss_noc_clk because it's not required. - Drop R-b tag .../bindings/clock/qcom,ipq9574-nsscc.yaml | 73 +++++++++ .../dt-bindings/clock/qcom,ipq9574-nsscc.h | 152 ++++++++++++++++++ .../dt-bindings/reset/qcom,ipq9574-nsscc.h | 134 +++++++++++++++ 3 files changed, 359 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-ns= scc.yaml create mode 100644 include/dt-bindings/clock/qcom,ipq9574-nsscc.h create mode 100644 include/dt-bindings/reset/qcom,ipq9574-nsscc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yam= l b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml new file mode 100644 index 000000000000..14a320079dbf --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 + +maintainers: + - Bjorn Andersson + - Anusha Rao + +description: | + Qualcomm networking sub system clock control module provides the clocks, + resets and power domains on IPQ9574 + + See also:: + include/dt-bindings/clock/qcom,ipq9574-nsscc.h + include/dt-bindings/reset/qcom,ipq9574-nsscc.h + +properties: + compatible: + const: qcom,ipq9574-nsscc + + clocks: + items: + - description: Board XO source + - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source + - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source + - description: GCC GPLL0 OUT AUX clock source + - description: Uniphy0 NSS Rx clock source + - description: Uniphy0 NSS Tx clock source + - description: Uniphy1 NSS Rx clock source + - description: Uniphy1 NSS Tx clock source + - description: Uniphy2 NSS Rx clock source + - description: Uniphy2 NSS Tx clock source + - description: GCC NSSCC clock source + + '#interconnect-cells': + const: 1 + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + clock-controller@39b00000 { + compatible =3D "qcom,ipq9574-nsscc"; + reg =3D <0x39b00000 0x80000>; + clocks =3D <&xo_board_clk>, + <&cmn_pll NSS_1200MHZ_CLK>, + <&cmn_pll PPE_353MHZ_CLK>, + <&gcc GPLL0_OUT_AUX>, + <&uniphy 0>, + <&uniphy 1>, + <&uniphy 2>, + <&uniphy 3>, + <&uniphy 4>, + <&uniphy 5>, + <&gcc GCC_NSSCC_CLK>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,ipq9574-nsscc.h b/include/dt-bi= ndings/clock/qcom,ipq9574-nsscc.h new file mode 100644 index 000000000000..59d57d9c788c --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq9574-nsscc.h @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H +#define _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H + +#define NSS_CC_CE_APB_CLK 0 +#define NSS_CC_CE_AXI_CLK 1 +#define NSS_CC_CE_CLK_SRC 2 +#define NSS_CC_CFG_CLK_SRC 3 +#define NSS_CC_CLC_AXI_CLK 4 +#define NSS_CC_CLC_CLK_SRC 5 +#define NSS_CC_CRYPTO_CLK 6 +#define NSS_CC_CRYPTO_CLK_SRC 7 +#define NSS_CC_CRYPTO_PPE_CLK 8 +#define NSS_CC_HAQ_AHB_CLK 9 +#define NSS_CC_HAQ_AXI_CLK 10 +#define NSS_CC_HAQ_CLK_SRC 11 +#define NSS_CC_IMEM_AHB_CLK 12 +#define NSS_CC_IMEM_CLK_SRC 13 +#define NSS_CC_IMEM_QSB_CLK 14 +#define NSS_CC_INT_CFG_CLK_SRC 15 +#define NSS_CC_NSS_CSR_CLK 16 +#define NSS_CC_NSSNOC_CE_APB_CLK 17 +#define NSS_CC_NSSNOC_CE_AXI_CLK 18 +#define NSS_CC_NSSNOC_CLC_AXI_CLK 19 +#define NSS_CC_NSSNOC_CRYPTO_CLK 20 +#define NSS_CC_NSSNOC_HAQ_AHB_CLK 21 +#define NSS_CC_NSSNOC_HAQ_AXI_CLK 22 +#define NSS_CC_NSSNOC_IMEM_AHB_CLK 23 +#define NSS_CC_NSSNOC_IMEM_QSB_CLK 24 +#define NSS_CC_NSSNOC_NSS_CSR_CLK 25 +#define NSS_CC_NSSNOC_PPE_CFG_CLK 26 +#define NSS_CC_NSSNOC_PPE_CLK 27 +#define NSS_CC_NSSNOC_UBI32_AHB0_CLK 28 +#define NSS_CC_NSSNOC_UBI32_AXI0_CLK 29 +#define NSS_CC_NSSNOC_UBI32_INT0_AHB_CLK 30 +#define NSS_CC_NSSNOC_UBI32_NC_AXI0_1_CLK 31 +#define NSS_CC_NSSNOC_UBI32_NC_AXI0_CLK 32 +#define NSS_CC_PORT1_MAC_CLK 33 +#define NSS_CC_PORT1_RX_CLK 34 +#define NSS_CC_PORT1_RX_CLK_SRC 35 +#define NSS_CC_PORT1_RX_DIV_CLK_SRC 36 +#define NSS_CC_PORT1_TX_CLK 37 +#define NSS_CC_PORT1_TX_CLK_SRC 38 +#define NSS_CC_PORT1_TX_DIV_CLK_SRC 39 +#define NSS_CC_PORT2_MAC_CLK 40 +#define NSS_CC_PORT2_RX_CLK 41 +#define NSS_CC_PORT2_RX_CLK_SRC 42 +#define NSS_CC_PORT2_RX_DIV_CLK_SRC 43 +#define NSS_CC_PORT2_TX_CLK 44 +#define NSS_CC_PORT2_TX_CLK_SRC 45 +#define NSS_CC_PORT2_TX_DIV_CLK_SRC 46 +#define NSS_CC_PORT3_MAC_CLK 47 +#define NSS_CC_PORT3_RX_CLK 48 +#define NSS_CC_PORT3_RX_CLK_SRC 49 +#define NSS_CC_PORT3_RX_DIV_CLK_SRC 50 +#define NSS_CC_PORT3_TX_CLK 51 +#define NSS_CC_PORT3_TX_CLK_SRC 52 +#define NSS_CC_PORT3_TX_DIV_CLK_SRC 53 +#define NSS_CC_PORT4_MAC_CLK 54 +#define NSS_CC_PORT4_RX_CLK 55 +#define NSS_CC_PORT4_RX_CLK_SRC 56 +#define NSS_CC_PORT4_RX_DIV_CLK_SRC 57 +#define NSS_CC_PORT4_TX_CLK 58 +#define NSS_CC_PORT4_TX_CLK_SRC 59 +#define NSS_CC_PORT4_TX_DIV_CLK_SRC 60 +#define NSS_CC_PORT5_MAC_CLK 61 +#define NSS_CC_PORT5_RX_CLK 62 +#define NSS_CC_PORT5_RX_CLK_SRC 63 +#define NSS_CC_PORT5_RX_DIV_CLK_SRC 64 +#define NSS_CC_PORT5_TX_CLK 65 +#define NSS_CC_PORT5_TX_CLK_SRC 66 +#define NSS_CC_PORT5_TX_DIV_CLK_SRC 67 +#define NSS_CC_PORT6_MAC_CLK 68 +#define NSS_CC_PORT6_RX_CLK 69 +#define NSS_CC_PORT6_RX_CLK_SRC 70 +#define NSS_CC_PORT6_RX_DIV_CLK_SRC 71 +#define NSS_CC_PORT6_TX_CLK 72 +#define NSS_CC_PORT6_TX_CLK_SRC 73 +#define NSS_CC_PORT6_TX_DIV_CLK_SRC 74 +#define NSS_CC_PPE_CLK_SRC 75 +#define NSS_CC_PPE_EDMA_CFG_CLK 76 +#define NSS_CC_PPE_EDMA_CLK 77 +#define NSS_CC_PPE_SWITCH_BTQ_CLK 78 +#define NSS_CC_PPE_SWITCH_CFG_CLK 79 +#define NSS_CC_PPE_SWITCH_CLK 80 +#define NSS_CC_PPE_SWITCH_IPE_CLK 81 +#define NSS_CC_UBI0_CLK_SRC 82 +#define NSS_CC_UBI0_DIV_CLK_SRC 83 +#define NSS_CC_UBI1_CLK_SRC 84 +#define NSS_CC_UBI1_DIV_CLK_SRC 85 +#define NSS_CC_UBI2_CLK_SRC 86 +#define NSS_CC_UBI2_DIV_CLK_SRC 87 +#define NSS_CC_UBI32_AHB0_CLK 88 +#define NSS_CC_UBI32_AHB1_CLK 89 +#define NSS_CC_UBI32_AHB2_CLK 90 +#define NSS_CC_UBI32_AHB3_CLK 91 +#define NSS_CC_UBI32_AXI0_CLK 92 +#define NSS_CC_UBI32_AXI1_CLK 93 +#define NSS_CC_UBI32_AXI2_CLK 94 +#define NSS_CC_UBI32_AXI3_CLK 95 +#define NSS_CC_UBI32_CORE0_CLK 96 +#define NSS_CC_UBI32_CORE1_CLK 97 +#define NSS_CC_UBI32_CORE2_CLK 98 +#define NSS_CC_UBI32_CORE3_CLK 99 +#define NSS_CC_UBI32_INTR0_AHB_CLK 100 +#define NSS_CC_UBI32_INTR1_AHB_CLK 101 +#define NSS_CC_UBI32_INTR2_AHB_CLK 102 +#define NSS_CC_UBI32_INTR3_AHB_CLK 103 +#define NSS_CC_UBI32_NC_AXI0_CLK 104 +#define NSS_CC_UBI32_NC_AXI1_CLK 105 +#define NSS_CC_UBI32_NC_AXI2_CLK 106 +#define NSS_CC_UBI32_NC_AXI3_CLK 107 +#define NSS_CC_UBI32_UTCM0_CLK 108 +#define NSS_CC_UBI32_UTCM1_CLK 109 +#define NSS_CC_UBI32_UTCM2_CLK 110 +#define NSS_CC_UBI32_UTCM3_CLK 111 +#define NSS_CC_UBI3_CLK_SRC 112 +#define NSS_CC_UBI3_DIV_CLK_SRC 113 +#define NSS_CC_UBI_AXI_CLK_SRC 114 +#define NSS_CC_UBI_NC_AXI_BFDCD_CLK_SRC 115 +#define NSS_CC_UNIPHY_PORT1_RX_CLK 116 +#define NSS_CC_UNIPHY_PORT1_TX_CLK 117 +#define NSS_CC_UNIPHY_PORT2_RX_CLK 118 +#define NSS_CC_UNIPHY_PORT2_TX_CLK 119 +#define NSS_CC_UNIPHY_PORT3_RX_CLK 120 +#define NSS_CC_UNIPHY_PORT3_TX_CLK 121 +#define NSS_CC_UNIPHY_PORT4_RX_CLK 122 +#define NSS_CC_UNIPHY_PORT4_TX_CLK 123 +#define NSS_CC_UNIPHY_PORT5_RX_CLK 124 +#define NSS_CC_UNIPHY_PORT5_TX_CLK 125 +#define NSS_CC_UNIPHY_PORT6_RX_CLK 126 +#define NSS_CC_UNIPHY_PORT6_TX_CLK 127 +#define NSS_CC_XGMAC0_PTP_REF_CLK 128 +#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 129 +#define NSS_CC_XGMAC1_PTP_REF_CLK 130 +#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 131 +#define NSS_CC_XGMAC2_PTP_REF_CLK 132 +#define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC 133 +#define NSS_CC_XGMAC3_PTP_REF_CLK 134 +#define NSS_CC_XGMAC3_PTP_REF_DIV_CLK_SRC 135 +#define NSS_CC_XGMAC4_PTP_REF_CLK 136 +#define NSS_CC_XGMAC4_PTP_REF_DIV_CLK_SRC 137 +#define NSS_CC_XGMAC5_PTP_REF_CLK 138 +#define NSS_CC_XGMAC5_PTP_REF_DIV_CLK_SRC 139 +#define UBI32_PLL 140 +#define UBI32_PLL_MAIN 141 + +#endif diff --git a/include/dt-bindings/reset/qcom,ipq9574-nsscc.h b/include/dt-bi= ndings/reset/qcom,ipq9574-nsscc.h new file mode 100644 index 000000000000..6910db0cff51 --- /dev/null +++ b/include/dt-bindings/reset/qcom,ipq9574-nsscc.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H +#define _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H + +#define EDMA_HW_RESET 0 +#define NSS_CC_CE_BCR 1 +#define NSS_CC_CLC_BCR 2 +#define NSS_CC_EIP197_BCR 3 +#define NSS_CC_HAQ_BCR 4 +#define NSS_CC_IMEM_BCR 5 +#define NSS_CC_MAC_BCR 6 +#define NSS_CC_PPE_BCR 7 +#define NSS_CC_UBI_BCR 8 +#define NSS_CC_UNIPHY_BCR 9 +#define UBI3_CLKRST_CLAMP_ENABLE 10 +#define UBI3_CORE_CLAMP_ENABLE 11 +#define UBI2_CLKRST_CLAMP_ENABLE 12 +#define UBI2_CORE_CLAMP_ENABLE 13 +#define UBI1_CLKRST_CLAMP_ENABLE 14 +#define UBI1_CORE_CLAMP_ENABLE 15 +#define UBI0_CLKRST_CLAMP_ENABLE 16 +#define UBI0_CORE_CLAMP_ENABLE 17 +#define NSSNOC_NSS_CSR_ARES 18 +#define NSS_CSR_ARES 19 +#define PPE_BTQ_ARES 20 +#define PPE_IPE_ARES 21 +#define PPE_ARES 22 +#define PPE_CFG_ARES 23 +#define PPE_EDMA_ARES 24 +#define PPE_EDMA_CFG_ARES 25 +#define CRY_PPE_ARES 26 +#define NSSNOC_PPE_ARES 27 +#define NSSNOC_PPE_CFG_ARES 28 +#define PORT1_MAC_ARES 29 +#define PORT2_MAC_ARES 30 +#define PORT3_MAC_ARES 31 +#define PORT4_MAC_ARES 32 +#define PORT5_MAC_ARES 33 +#define PORT6_MAC_ARES 34 +#define XGMAC0_PTP_REF_ARES 35 +#define XGMAC1_PTP_REF_ARES 36 +#define XGMAC2_PTP_REF_ARES 37 +#define XGMAC3_PTP_REF_ARES 38 +#define XGMAC4_PTP_REF_ARES 39 +#define XGMAC5_PTP_REF_ARES 40 +#define HAQ_AHB_ARES 41 +#define HAQ_AXI_ARES 42 +#define NSSNOC_HAQ_AHB_ARES 43 +#define NSSNOC_HAQ_AXI_ARES 44 +#define CE_APB_ARES 45 +#define CE_AXI_ARES 46 +#define NSSNOC_CE_APB_ARES 47 +#define NSSNOC_CE_AXI_ARES 48 +#define CRYPTO_ARES 49 +#define NSSNOC_CRYPTO_ARES 50 +#define NSSNOC_NC_AXI0_1_ARES 51 +#define UBI0_CORE_ARES 52 +#define UBI1_CORE_ARES 53 +#define UBI2_CORE_ARES 54 +#define UBI3_CORE_ARES 55 +#define NC_AXI0_ARES 56 +#define UTCM0_ARES 57 +#define NC_AXI1_ARES 58 +#define UTCM1_ARES 59 +#define NC_AXI2_ARES 60 +#define UTCM2_ARES 61 +#define NC_AXI3_ARES 62 +#define UTCM3_ARES 63 +#define NSSNOC_NC_AXI0_ARES 64 +#define AHB0_ARES 65 +#define INTR0_AHB_ARES 66 +#define AHB1_ARES 67 +#define INTR1_AHB_ARES 68 +#define AHB2_ARES 69 +#define INTR2_AHB_ARES 70 +#define AHB3_ARES 71 +#define INTR3_AHB_ARES 72 +#define NSSNOC_AHB0_ARES 73 +#define NSSNOC_INT0_AHB_ARES 74 +#define AXI0_ARES 75 +#define AXI1_ARES 76 +#define AXI2_ARES 77 +#define AXI3_ARES 78 +#define NSSNOC_AXI0_ARES 79 +#define IMEM_QSB_ARES 80 +#define NSSNOC_IMEM_QSB_ARES 81 +#define IMEM_AHB_ARES 82 +#define NSSNOC_IMEM_AHB_ARES 83 +#define UNIPHY_PORT1_RX_ARES 84 +#define UNIPHY_PORT1_TX_ARES 85 +#define UNIPHY_PORT2_RX_ARES 86 +#define UNIPHY_PORT2_TX_ARES 87 +#define UNIPHY_PORT3_RX_ARES 88 +#define UNIPHY_PORT3_TX_ARES 89 +#define UNIPHY_PORT4_RX_ARES 90 +#define UNIPHY_PORT4_TX_ARES 91 +#define UNIPHY_PORT5_RX_ARES 92 +#define UNIPHY_PORT5_TX_ARES 93 +#define UNIPHY_PORT6_RX_ARES 94 +#define UNIPHY_PORT6_TX_ARES 95 +#define PORT1_RX_ARES 96 +#define PORT1_TX_ARES 97 +#define PORT2_RX_ARES 98 +#define PORT2_TX_ARES 99 +#define PORT3_RX_ARES 100 +#define PORT3_TX_ARES 101 +#define PORT4_RX_ARES 102 +#define PORT4_TX_ARES 103 +#define PORT5_RX_ARES 104 +#define PORT5_TX_ARES 105 +#define PORT6_RX_ARES 106 +#define PORT6_TX_ARES 107 +#define PPE_FULL_RESET 108 +#define UNIPHY0_SOFT_RESET 109 +#define UNIPHY1_SOFT_RESET 110 +#define UNIPHY2_SOFT_RESET 111 +#define UNIPHY_PORT1_ARES 112 +#define UNIPHY_PORT2_ARES 113 +#define UNIPHY_PORT3_ARES 114 +#define UNIPHY_PORT4_ARES 115 +#define UNIPHY_PORT5_ARES 116 +#define UNIPHY_PORT6_ARES 117 +#define NSSPORT1_RESET 118 +#define NSSPORT2_RESET 119 +#define NSSPORT3_RESET 120 +#define NSSPORT4_RESET 121 +#define NSSPORT5_RESET 122 +#define NSSPORT6_RESET 123 + +#endif --=20 2.34.1 From nobody Mon Nov 25 18:48:10 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5E7A18C034; Fri, 25 Oct 2024 03:56:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729828621; cv=none; b=UshlwrTbupZl/ZLguNBvA9QU/GE7WU8OlguLQCIYJnz5BgIUsi1DvQgOzMNvPT35IHl/7mWIPMuIkmR+kUOPqsFaJlbP6n56bjnSIzCUhs1uX314IlCRIgF3Je0H3DsgP9vDtfwcwghQAvYrwPjro9xEc8+Cf8hfu0RURrOv6UI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729828621; c=relaxed/simple; bh=cZNG1QQ66muHS/81zemxE607DxRhQrYiMcKkqsCwstQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XGqc77sUPdi2N0m0T2SMHa4oKPQ1GVTD2nKjThZsY+xSsyrm1QrXUhXNqX79wlt1FJWNun0WJd3D2LM79AB2RjUb7UYJCnV49FmWNHx0LLAQq0z5ua9iMUkHJKPW2f2zgC8YUC3mT3+zQOnAj8r0rcXfAI2fburFgYJz+m+dsN0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=KxVizqum; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="KxVizqum" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49P2hgS4028787; Fri, 25 Oct 2024 03:56:22 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= dMSe1pqVysZQW+YE5JNg1Vc0VqZGfrTuyjtmpK4t/Pk=; b=KxVizqum9z3lNXPw 8kpMAPW3cXwFnUVFxzFLMBx1V6J310WCWxLmZFyklGHif5BlBv2qlvJfpYuHyT/k iacCEI8ePi3WHj1f5+uNEONFOg3adfUyvVcPnOcbos9UVszV2w2pPZEd+U8EoX5I t72THtQaRlMG1vkm/iiyKXckIbJUXdv7vxCQdH8mgr7vK/UIzkCVj/Bo63FY4Chz jCGhe5iU8BxbV11Y6z6ke//wMPten3Z3gNtBZHIplafjDuW8ijB+Ehswa7P8/7Co fMkG3SdkMLmYCTaEybAqThXHqoGR3lWdCEhBI6m+DMACd+r+mxszpiw4QFW58E1E p41Jlw== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42fdtxkgp6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 03:56:21 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49P3uK7f015928 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 03:56:20 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 24 Oct 2024 20:56:12 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH v8 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574 Date: Fri, 25 Oct 2024 09:25:18 +0530 Message-ID: <20241025035520.1841792-6-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025035520.1841792-1-quic_mmanikan@quicinc.com> References: <20241025035520.1841792-1-quic_mmanikan@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: bs5jDdlavvpAZpQa0xxHFuXultTvad27 X-Proofpoint-ORIG-GUID: bs5jDdlavvpAZpQa0xxHFuXultTvad27 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 bulkscore=0 spamscore=0 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410250026 Content-Type: text/plain; charset="utf-8" From: Devi Priya Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574 based devices. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202410101431.tjpSRNTY-lkp@int= el.com/ Signed-off-by: Devi Priya Signed-off-by: Manikanta Mylavarapu --- Changes in V8: - Remove DT_BIAS_PLL_NSS_NOC_CLK and P_BIAS_PLL_NSS_NOC_CLK because these are not required drivers/clk/qcom/Kconfig | 7 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/nsscc-ipq9574.c | 3080 ++++++++++++++++++++++++++++++ 3 files changed, 3088 insertions(+) create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 6e0ecb204855..fcdd461d52b6 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -265,6 +265,13 @@ config IPQ_GCC_9574 i2c, USB, SD/eMMC, etc. Select this for the root clock of ipq9574. =20 +config IPQ_NSSCC_9574 + tristate "IPQ9574 NSS Clock Controller" + depends on ARM64 || COMPILE_TEST + depends on IPQ_GCC_9574 + help + Support for NSS clock controller on ipq9574 devices. + config IPQ_NSSCC_QCA8K tristate "QCA8K(QCA8386 or QCA8084) NSS Clock Controller" depends on MDIO_BUS diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 4e7577f11730..2fdf8260d1ec 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_IPQ_GCC_6018) +=3D gcc-ipq6018.o obj-$(CONFIG_IPQ_GCC_806X) +=3D gcc-ipq806x.o obj-$(CONFIG_IPQ_GCC_8074) +=3D gcc-ipq8074.o obj-$(CONFIG_IPQ_GCC_9574) +=3D gcc-ipq9574.o +obj-$(CONFIG_IPQ_NSSCC_9574) +=3D nsscc-ipq9574.o obj-$(CONFIG_IPQ_LCC_806X) +=3D lcc-ipq806x.o obj-$(CONFIG_IPQ_NSSCC_QCA8K) +=3D nsscc-qca8k.o obj-$(CONFIG_MDM_GCC_9607) +=3D gcc-mdm9607.o diff --git a/drivers/clk/qcom/nsscc-ipq9574.c b/drivers/clk/qcom/nsscc-ipq9= 574.c new file mode 100644 index 000000000000..d3e9aa391236 --- /dev/null +++ b/drivers/clk/qcom/nsscc-ipq9574.c @@ -0,0 +1,3080 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "reset.h" + +/* Need to match the order of clocks in DT binding */ +enum { + DT_XO, + DT_BIAS_PLL_CC_CLK, + DT_BIAS_PLL_UBI_NC_CLK, + DT_GCC_GPLL0_OUT_AUX, + DT_UNIPHY0_NSS_RX_CLK, + DT_UNIPHY0_NSS_TX_CLK, + DT_UNIPHY1_NSS_RX_CLK, + DT_UNIPHY1_NSS_TX_CLK, + DT_UNIPHY2_NSS_RX_CLK, + DT_UNIPHY2_NSS_TX_CLK, +}; + +enum { + P_XO, + P_BIAS_PLL_CC_CLK, + P_BIAS_PLL_UBI_NC_CLK, + P_GCC_GPLL0_OUT_AUX, + P_UBI32_PLL_OUT_MAIN, + P_UNIPHY0_NSS_RX_CLK, + P_UNIPHY0_NSS_TX_CLK, + P_UNIPHY1_NSS_RX_CLK, + P_UNIPHY1_NSS_TX_CLK, + P_UNIPHY2_NSS_RX_CLK, + P_UNIPHY2_NSS_TX_CLK, +}; + +static const struct alpha_pll_config ubi32_pll_config =3D { + .l =3D 0x3e, + .alpha =3D 0x6666, + .config_ctl_val =3D 0x200d4aa8, + .config_ctl_hi_val =3D 0x3c, + .main_output_mask =3D BIT(0), + .aux_output_mask =3D BIT(1), + .pre_div_val =3D 0x0, + .pre_div_mask =3D BIT(12), + .post_div_val =3D 0x0, + .post_div_mask =3D GENMASK(9, 8), + .alpha_en_mask =3D BIT(24), + .test_ctl_val =3D 0x1c0000c0, + .test_ctl_hi_val =3D 0x4000, +}; + +static struct clk_alpha_pll ubi32_pll_main =3D { + .offset =3D 0x28000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA], + .flags =3D SUPPORTS_DYNAMIC_UPDATE, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "ubi32_pll_main", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_XO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_huayra_ops, + }, + }, +}; + +static struct clk_alpha_pll_postdiv ubi32_pll =3D { + .offset =3D 0x28000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA], + .width =3D 2, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "ubi32_pll", + .parent_hws =3D (const struct clk_hw *[]) { + &ubi32_pll_main.clkr.hw + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_ro_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct parent_map nss_cc_parent_map_0[] =3D { + { P_XO, 0 }, + { P_BIAS_PLL_CC_CLK, 1 }, + { P_UNIPHY0_NSS_RX_CLK, 2 }, + { P_UNIPHY0_NSS_TX_CLK, 3 }, + { P_UNIPHY1_NSS_RX_CLK, 4 }, + { P_UNIPHY1_NSS_TX_CLK, 5 }, +}; + +static const struct clk_parent_data nss_cc_parent_data_0[] =3D { + { .index =3D DT_XO }, + { .index =3D DT_BIAS_PLL_CC_CLK }, + { .index =3D DT_UNIPHY0_NSS_RX_CLK }, + { .index =3D DT_UNIPHY0_NSS_TX_CLK }, + { .index =3D DT_UNIPHY1_NSS_RX_CLK }, + { .index =3D DT_UNIPHY1_NSS_TX_CLK }, +}; + +static const struct parent_map nss_cc_parent_map_1[] =3D { + { P_XO, 0 }, + { P_BIAS_PLL_UBI_NC_CLK, 1 }, + { P_GCC_GPLL0_OUT_AUX, 2 }, + { P_BIAS_PLL_CC_CLK, 6 }, +}; + +static const struct clk_parent_data nss_cc_parent_data_1[] =3D { + { .index =3D DT_XO }, + { .index =3D DT_BIAS_PLL_UBI_NC_CLK }, + { .index =3D DT_GCC_GPLL0_OUT_AUX }, + { .index =3D DT_BIAS_PLL_CC_CLK }, +}; + +static const struct parent_map nss_cc_parent_map_2[] =3D { + { P_XO, 0 }, + { P_UBI32_PLL_OUT_MAIN, 1 }, + { P_GCC_GPLL0_OUT_AUX, 2 }, +}; + +static const struct clk_parent_data nss_cc_parent_data_2[] =3D { + { .index =3D DT_XO }, + { .hw =3D &ubi32_pll.clkr.hw }, + { .index =3D DT_GCC_GPLL0_OUT_AUX }, +}; + +static const struct parent_map nss_cc_parent_map_3[] =3D { + { P_XO, 0 }, + { P_BIAS_PLL_CC_CLK, 1 }, + { P_GCC_GPLL0_OUT_AUX, 2 }, +}; + +static const struct clk_parent_data nss_cc_parent_data_3[] =3D { + { .index =3D DT_XO }, + { .index =3D DT_BIAS_PLL_CC_CLK }, + { .index =3D DT_GCC_GPLL0_OUT_AUX }, +}; + +static const struct parent_map nss_cc_parent_map_4[] =3D { + { P_XO, 0 }, + { P_BIAS_PLL_CC_CLK, 1 }, + { P_UNIPHY0_NSS_RX_CLK, 2 }, + { P_UNIPHY0_NSS_TX_CLK, 3 }, +}; + +static const struct clk_parent_data nss_cc_parent_data_4[] =3D { + { .index =3D DT_XO }, + { .index =3D DT_BIAS_PLL_CC_CLK }, + { .index =3D DT_UNIPHY0_NSS_RX_CLK }, + { .index =3D DT_UNIPHY0_NSS_TX_CLK }, +}; + +static const struct parent_map nss_cc_parent_map_5[] =3D { + { P_XO, 0 }, + { P_BIAS_PLL_CC_CLK, 1 }, + { P_UNIPHY2_NSS_RX_CLK, 2 }, + { P_UNIPHY2_NSS_TX_CLK, 3 }, +}; + +static const struct clk_parent_data nss_cc_parent_data_5[] =3D { + { .index =3D DT_XO }, + { .index =3D DT_BIAS_PLL_CC_CLK }, + { .index =3D DT_UNIPHY2_NSS_RX_CLK }, + { .index =3D DT_UNIPHY2_NSS_TX_CLK }, +}; + +static const struct parent_map nss_cc_parent_map_6[] =3D { + { P_XO, 0 }, + { P_GCC_GPLL0_OUT_AUX, 2 }, + { P_BIAS_PLL_CC_CLK, 6 }, +}; + +static const struct clk_parent_data nss_cc_parent_data_6[] =3D { + { .index =3D DT_XO }, + { .index =3D DT_GCC_GPLL0_OUT_AUX }, + { .index =3D DT_BIAS_PLL_CC_CLK }, +}; + +static const struct parent_map nss_cc_parent_map_7[] =3D { + { P_XO, 0 }, + { P_UBI32_PLL_OUT_MAIN, 1 }, + { P_GCC_GPLL0_OUT_AUX, 2 }, + { P_BIAS_PLL_CC_CLK, 6 }, +}; + +static const struct clk_parent_data nss_cc_parent_data_7[] =3D { + { .index =3D DT_XO }, + { .hw =3D &ubi32_pll.clkr.hw }, + { .index =3D DT_GCC_GPLL0_OUT_AUX }, + { .index =3D DT_BIAS_PLL_CC_CLK }, +}; + +static const struct freq_tbl ftbl_nss_cc_ce_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + F(353000000, P_BIAS_PLL_UBI_NC_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_ce_clk_src =3D { + .cmd_rcgr =3D 0x28404, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_1, + .freq_tbl =3D ftbl_nss_cc_ce_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ce_clk_src", + .parent_data =3D nss_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_nss_cc_cfg_clk_src[] =3D { + F(100000000, P_GCC_GPLL0_OUT_AUX, 8, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_cfg_clk_src =3D { + .cmd_rcgr =3D 0x28104, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_3, + .freq_tbl =3D ftbl_nss_cc_cfg_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_cfg_clk_src", + .parent_data =3D nss_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_3), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_nss_cc_clc_clk_src[] =3D { + F(533333333, P_GCC_GPLL0_OUT_AUX, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_clc_clk_src =3D { + .cmd_rcgr =3D 0x28604, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_6, + .freq_tbl =3D ftbl_nss_cc_clc_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_clc_clk_src", + .parent_data =3D nss_cc_parent_data_6, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_6), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_nss_cc_crypto_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + F(300000000, P_BIAS_PLL_CC_CLK, 4, 0, 0), + F(600000000, P_BIAS_PLL_CC_CLK, 2, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_crypto_clk_src =3D { + .cmd_rcgr =3D 0x16008, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_3, + .freq_tbl =3D ftbl_nss_cc_crypto_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_crypto_clk_src", + .parent_data =3D nss_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 nss_cc_haq_clk_src =3D { + .cmd_rcgr =3D 0x28304, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_1, + .freq_tbl =3D ftbl_nss_cc_ce_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_haq_clk_src", + .parent_data =3D nss_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 nss_cc_imem_clk_src =3D { + .cmd_rcgr =3D 0xe008, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_1, + .freq_tbl =3D ftbl_nss_cc_ce_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_imem_clk_src", + .parent_data =3D nss_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_nss_cc_int_cfg_clk_src[] =3D { + F(200000000, P_GCC_GPLL0_OUT_AUX, 4, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_int_cfg_clk_src =3D { + .cmd_rcgr =3D 0x287b4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_3, + .freq_tbl =3D ftbl_nss_cc_int_cfg_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_int_cfg_clk_src", + .parent_data =3D nss_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_3), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] =3D { + C(P_UNIPHY0_NSS_RX_CLK, 12.5, 0, 0), + C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_125[] =3D { + C(P_UNIPHY0_NSS_RX_CLK, 2.5, 0, 0), + C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0), +}; + +static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] =3D { + FMS(24000000, P_XO, 1, 0, 0), + FM(25000000, ftbl_nss_cc_port1_rx_clk_src_25), + FMS(78125000, P_UNIPHY0_NSS_RX_CLK, 4, 0, 0), + FM(125000000, ftbl_nss_cc_port1_rx_clk_src_125), + FMS(312500000, P_UNIPHY0_NSS_RX_CLK, 1, 0, 0), + { } +}; + +static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_25[] =3D { + C(P_UNIPHY0_NSS_TX_CLK, 12.5, 0, 0), + C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_125[] =3D { + C(P_UNIPHY0_NSS_TX_CLK, 2.5, 0, 0), + C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0), +}; + +static const struct freq_multi_tbl ftbl_nss_cc_port1_tx_clk_src[] =3D { + FMS(24000000, P_XO, 1, 0, 0), + FM(25000000, ftbl_nss_cc_port1_tx_clk_src_25), + FMS(78125000, P_UNIPHY0_NSS_TX_CLK, 4, 0, 0), + FM(125000000, ftbl_nss_cc_port1_tx_clk_src_125), + FMS(312500000, P_UNIPHY0_NSS_TX_CLK, 1, 0, 0), + { } +}; + +static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_25[] =3D { + C(P_UNIPHY1_NSS_RX_CLK, 12.5, 0, 0), + C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_125[] =3D { + C(P_UNIPHY1_NSS_RX_CLK, 2.5, 0, 0), + C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_312p5[] =3D { + C(P_UNIPHY1_NSS_RX_CLK, 1, 0, 0), + C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0), +}; + +static const struct freq_multi_tbl ftbl_nss_cc_port5_rx_clk_src[] =3D { + FMS(24000000, P_XO, 1, 0, 0), + FM(25000000, ftbl_nss_cc_port5_rx_clk_src_25), + FMS(78125000, P_UNIPHY1_NSS_RX_CLK, 4, 0, 0), + FM(125000000, ftbl_nss_cc_port5_rx_clk_src_125), + FMS(156250000, P_UNIPHY1_NSS_RX_CLK, 2, 0, 0), + FM(312500000, ftbl_nss_cc_port5_rx_clk_src_312p5), + { } +}; + +static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_25[] =3D { + C(P_UNIPHY1_NSS_TX_CLK, 12.5, 0, 0), + C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_125[] =3D { + C(P_UNIPHY1_NSS_TX_CLK, 2.5, 0, 0), + C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_312p5[] =3D { + C(P_UNIPHY1_NSS_TX_CLK, 1, 0, 0), + C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0), +}; + +static const struct freq_multi_tbl ftbl_nss_cc_port5_tx_clk_src[] =3D { + FMS(24000000, P_XO, 1, 0, 0), + FM(25000000, ftbl_nss_cc_port5_tx_clk_src_25), + FMS(78125000, P_UNIPHY1_NSS_TX_CLK, 4, 0, 0), + FM(125000000, ftbl_nss_cc_port5_tx_clk_src_125), + FMS(156250000, P_UNIPHY1_NSS_TX_CLK, 2, 0, 0), + FM(312500000, ftbl_nss_cc_port5_tx_clk_src_312p5), + { } +}; + +static const struct freq_conf ftbl_nss_cc_port6_rx_clk_src_25[] =3D { + C(P_UNIPHY2_NSS_RX_CLK, 12.5, 0, 0), + C(P_UNIPHY2_NSS_RX_CLK, 5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_port6_rx_clk_src_125[] =3D { + C(P_UNIPHY2_NSS_RX_CLK, 2.5, 0, 0), + C(P_UNIPHY2_NSS_RX_CLK, 1, 0, 0), +}; + +static const struct freq_multi_tbl ftbl_nss_cc_port6_rx_clk_src[] =3D { + FMS(24000000, P_XO, 1, 0, 0), + FM(25000000, ftbl_nss_cc_port6_rx_clk_src_25), + FMS(78125000, P_UNIPHY2_NSS_RX_CLK, 4, 0, 0), + FM(125000000, ftbl_nss_cc_port6_rx_clk_src_125), + FMS(156250000, P_UNIPHY2_NSS_RX_CLK, 2, 0, 0), + FMS(312500000, P_UNIPHY2_NSS_RX_CLK, 1, 0, 0), + { } +}; + +static const struct freq_conf ftbl_nss_cc_port6_tx_clk_src_25[] =3D { + C(P_UNIPHY2_NSS_TX_CLK, 12.5, 0, 0), + C(P_UNIPHY2_NSS_TX_CLK, 5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_port6_tx_clk_src_125[] =3D { + C(P_UNIPHY2_NSS_TX_CLK, 2.5, 0, 0), + C(P_UNIPHY2_NSS_TX_CLK, 1, 0, 0), +}; + +static const struct freq_multi_tbl ftbl_nss_cc_port6_tx_clk_src[] =3D { + FMS(24000000, P_XO, 1, 0, 0), + FM(25000000, ftbl_nss_cc_port6_tx_clk_src_25), + FMS(78125000, P_UNIPHY2_NSS_TX_CLK, 4, 0, 0), + FM(125000000, ftbl_nss_cc_port6_tx_clk_src_125), + FMS(156250000, P_UNIPHY2_NSS_TX_CLK, 2, 0, 0), + FMS(312500000, P_UNIPHY2_NSS_TX_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_port1_rx_clk_src =3D { + .cmd_rcgr =3D 0x28110, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_4, + .freq_multi_tbl =3D ftbl_nss_cc_port1_rx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port1_rx_clk_src", + .parent_data =3D nss_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_4), + .ops =3D &clk_rcg2_fm_ops, + }, +}; + +static struct clk_rcg2 nss_cc_port1_tx_clk_src =3D { + .cmd_rcgr =3D 0x2811c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_4, + .freq_multi_tbl =3D ftbl_nss_cc_port1_tx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port1_tx_clk_src", + .parent_data =3D nss_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_4), + .ops =3D &clk_rcg2_fm_ops, + }, +}; + +static struct clk_rcg2 nss_cc_port2_rx_clk_src =3D { + .cmd_rcgr =3D 0x28128, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_4, + .freq_multi_tbl =3D ftbl_nss_cc_port1_rx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port2_rx_clk_src", + .parent_data =3D nss_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_4), + .ops =3D &clk_rcg2_fm_ops, + }, +}; + +static struct clk_rcg2 nss_cc_port2_tx_clk_src =3D { + .cmd_rcgr =3D 0x28134, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_4, + .freq_multi_tbl =3D ftbl_nss_cc_port1_tx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port2_tx_clk_src", + .parent_data =3D nss_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_4), + .ops =3D &clk_rcg2_fm_ops, + }, +}; + +static struct clk_rcg2 nss_cc_port3_rx_clk_src =3D { + .cmd_rcgr =3D 0x28140, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_4, + .freq_multi_tbl =3D ftbl_nss_cc_port1_rx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port3_rx_clk_src", + .parent_data =3D nss_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_4), + .ops =3D &clk_rcg2_fm_ops, + }, +}; + +static struct clk_rcg2 nss_cc_port3_tx_clk_src =3D { + .cmd_rcgr =3D 0x2814c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_4, + .freq_multi_tbl =3D ftbl_nss_cc_port1_tx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port3_tx_clk_src", + .parent_data =3D nss_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_4), + .ops =3D &clk_rcg2_fm_ops, + }, +}; + +static struct clk_rcg2 nss_cc_port4_rx_clk_src =3D { + .cmd_rcgr =3D 0x28158, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_4, + .freq_multi_tbl =3D ftbl_nss_cc_port1_rx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port4_rx_clk_src", + .parent_data =3D nss_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_4), + .ops =3D &clk_rcg2_fm_ops, + }, +}; + +static struct clk_rcg2 nss_cc_port4_tx_clk_src =3D { + .cmd_rcgr =3D 0x28164, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_4, + .freq_multi_tbl =3D ftbl_nss_cc_port1_tx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port4_tx_clk_src", + .parent_data =3D nss_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_4), + .ops =3D &clk_rcg2_fm_ops, + }, +}; + +static struct clk_rcg2 nss_cc_port5_rx_clk_src =3D { + .cmd_rcgr =3D 0x28170, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_0, + .freq_multi_tbl =3D ftbl_nss_cc_port5_rx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port5_rx_clk_src", + .parent_data =3D nss_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_0), + .ops =3D &clk_rcg2_fm_ops, + }, +}; + +static struct clk_rcg2 nss_cc_port5_tx_clk_src =3D { + .cmd_rcgr =3D 0x2817c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_0, + .freq_multi_tbl =3D ftbl_nss_cc_port5_tx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port5_tx_clk_src", + .parent_data =3D nss_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_0), + .ops =3D &clk_rcg2_fm_ops, + }, +}; + +static struct clk_rcg2 nss_cc_port6_rx_clk_src =3D { + .cmd_rcgr =3D 0x28188, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_5, + .freq_multi_tbl =3D ftbl_nss_cc_port6_rx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port6_rx_clk_src", + .parent_data =3D nss_cc_parent_data_5, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_5), + .ops =3D &clk_rcg2_fm_ops, + }, +}; + +static struct clk_rcg2 nss_cc_port6_tx_clk_src =3D { + .cmd_rcgr =3D 0x28194, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_5, + .freq_multi_tbl =3D ftbl_nss_cc_port6_tx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port6_tx_clk_src", + .parent_data =3D nss_cc_parent_data_5, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_5), + .ops =3D &clk_rcg2_fm_ops, + }, +}; + +static struct clk_rcg2 nss_cc_ppe_clk_src =3D { + .cmd_rcgr =3D 0x28204, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_1, + .freq_tbl =3D ftbl_nss_cc_ce_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ppe_clk_src", + .parent_data =3D nss_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_nss_cc_ubi0_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + F(187200000, P_UBI32_PLL_OUT_MAIN, 8, 0, 0), + F(748800000, P_UBI32_PLL_OUT_MAIN, 2, 0, 0), + F(1497600000, P_UBI32_PLL_OUT_MAIN, 1, 0, 0), + F(1689600000, P_UBI32_PLL_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_ubi0_clk_src =3D { + .cmd_rcgr =3D 0x28704, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_2, + .freq_tbl =3D ftbl_nss_cc_ubi0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi0_clk_src", + .parent_data =3D nss_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 nss_cc_ubi1_clk_src =3D { + .cmd_rcgr =3D 0x2870c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_2, + .freq_tbl =3D ftbl_nss_cc_ubi0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi1_clk_src", + .parent_data =3D nss_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 nss_cc_ubi2_clk_src =3D { + .cmd_rcgr =3D 0x28714, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_2, + .freq_tbl =3D ftbl_nss_cc_ubi0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi2_clk_src", + .parent_data =3D nss_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 nss_cc_ubi3_clk_src =3D { + .cmd_rcgr =3D 0x2871c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_2, + .freq_tbl =3D ftbl_nss_cc_ubi0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi3_clk_src", + .parent_data =3D nss_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 nss_cc_ubi_axi_clk_src =3D { + .cmd_rcgr =3D 0x28724, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_7, + .freq_tbl =3D ftbl_nss_cc_clc_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi_axi_clk_src", + .parent_data =3D nss_cc_parent_data_7, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_7), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 nss_cc_ubi_nc_axi_bfdcd_clk_src =3D { + .cmd_rcgr =3D 0x2872c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_1, + .freq_tbl =3D ftbl_nss_cc_ce_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi_nc_axi_bfdcd_clk_src", + .parent_data =3D nss_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port1_rx_div_clk_src =3D { + .reg =3D 0x28118, + .shift =3D 0, + .width =3D 9, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port1_rx_div_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port1_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port1_tx_div_clk_src =3D { + .reg =3D 0x28124, + .shift =3D 0, + .width =3D 9, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port1_tx_div_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port1_tx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port2_rx_div_clk_src =3D { + .reg =3D 0x28130, + .shift =3D 0, + .width =3D 9, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port2_rx_div_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port2_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port2_tx_div_clk_src =3D { + .reg =3D 0x2813c, + .shift =3D 0, + .width =3D 9, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port2_tx_div_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port2_tx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port3_rx_div_clk_src =3D { + .reg =3D 0x28148, + .shift =3D 0, + .width =3D 9, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port3_rx_div_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port3_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port3_tx_div_clk_src =3D { + .reg =3D 0x28154, + .shift =3D 0, + .width =3D 9, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port3_tx_div_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port3_tx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port4_rx_div_clk_src =3D { + .reg =3D 0x28160, + .shift =3D 0, + .width =3D 9, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port4_rx_div_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port4_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port4_tx_div_clk_src =3D { + .reg =3D 0x2816c, + .shift =3D 0, + .width =3D 9, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port4_tx_div_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port4_tx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port5_rx_div_clk_src =3D { + .reg =3D 0x28178, + .shift =3D 0, + .width =3D 9, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port5_rx_div_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port5_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port5_tx_div_clk_src =3D { + .reg =3D 0x28184, + .shift =3D 0, + .width =3D 9, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port5_tx_div_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port5_tx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port6_rx_div_clk_src =3D { + .reg =3D 0x28190, + .shift =3D 0, + .width =3D 9, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port6_rx_div_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port6_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port6_tx_div_clk_src =3D { + .reg =3D 0x2819c, + .shift =3D 0, + .width =3D 9, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port6_tx_div_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port6_tx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_ubi0_div_clk_src =3D { + .reg =3D 0x287a4, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi0_div_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ubi0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div nss_cc_ubi1_div_clk_src =3D { + .reg =3D 0x287a8, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi1_div_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ubi1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div nss_cc_ubi2_div_clk_src =3D { + .reg =3D 0x287ac, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi2_div_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ubi2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div nss_cc_ubi3_div_clk_src =3D { + .reg =3D 0x287b0, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi3_div_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ubi3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div nss_cc_xgmac0_ptp_ref_div_clk_src =3D { + .reg =3D 0x28214, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_xgmac0_ptp_ref_div_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div nss_cc_xgmac1_ptp_ref_div_clk_src =3D { + .reg =3D 0x28218, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_xgmac1_ptp_ref_div_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div nss_cc_xgmac2_ptp_ref_div_clk_src =3D { + .reg =3D 0x2821c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_xgmac2_ptp_ref_div_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div nss_cc_xgmac3_ptp_ref_div_clk_src =3D { + .reg =3D 0x28220, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_xgmac3_ptp_ref_div_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div nss_cc_xgmac4_ptp_ref_div_clk_src =3D { + .reg =3D 0x28224, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_xgmac4_ptp_ref_div_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div nss_cc_xgmac5_ptp_ref_div_clk_src =3D { + .reg =3D 0x28228, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_xgmac5_ptp_ref_div_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch nss_cc_ce_apb_clk =3D { + .halt_reg =3D 0x2840c, + .clkr =3D { + .enable_reg =3D 0x2840c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ce_apb_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ce_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ce_axi_clk =3D { + .halt_reg =3D 0x28410, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28410, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ce_axi_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ce_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_clc_axi_clk =3D { + .halt_reg =3D 0x2860c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2860c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_clc_axi_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_clc_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_crypto_clk =3D { + .halt_reg =3D 0x1601c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1601c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_crypto_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_crypto_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_crypto_ppe_clk =3D { + .halt_reg =3D 0x28240, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28240, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_crypto_ppe_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_haq_ahb_clk =3D { + .halt_reg =3D 0x2830c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2830c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_haq_ahb_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_haq_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_haq_axi_clk =3D { + .halt_reg =3D 0x28310, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28310, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_haq_axi_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_haq_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_imem_ahb_clk =3D { + .halt_reg =3D 0xe018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xe018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_imem_ahb_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_cfg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_imem_qsb_clk =3D { + .halt_reg =3D 0xe010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xe010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_imem_qsb_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_imem_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nss_csr_clk =3D { + .halt_reg =3D 0x281d0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x281d0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_nss_csr_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_cfg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_ce_apb_clk =3D { + .halt_reg =3D 0x28414, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28414, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_nssnoc_ce_apb_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ce_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_ce_axi_clk =3D { + .halt_reg =3D 0x28418, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28418, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_nssnoc_ce_axi_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ce_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_clc_axi_clk =3D { + .halt_reg =3D 0x28610, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28610, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_nssnoc_clc_axi_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_clc_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_crypto_clk =3D { + .halt_reg =3D 0x16020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x16020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_nssnoc_crypto_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_crypto_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_haq_ahb_clk =3D { + .halt_reg =3D 0x28314, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28314, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_nssnoc_haq_ahb_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_haq_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_haq_axi_clk =3D { + .halt_reg =3D 0x28318, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28318, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_nssnoc_haq_axi_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_haq_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_imem_ahb_clk =3D { + .halt_reg =3D 0xe01c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xe01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_nssnoc_imem_ahb_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_cfg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_imem_qsb_clk =3D { + .halt_reg =3D 0xe014, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xe014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_nssnoc_imem_qsb_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_imem_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_nss_csr_clk =3D { + .halt_reg =3D 0x281d4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x281d4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_nssnoc_nss_csr_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_cfg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_ppe_cfg_clk =3D { + .halt_reg =3D 0x28248, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28248, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_nssnoc_ppe_cfg_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_ppe_clk =3D { + .halt_reg =3D 0x28244, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28244, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_nssnoc_ppe_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_ubi32_ahb0_clk =3D { + .halt_reg =3D 0x28788, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28788, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_nssnoc_ubi32_ahb0_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_cfg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_ubi32_axi0_clk =3D { + .halt_reg =3D 0x287a0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x287a0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_nssnoc_ubi32_axi0_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ubi_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_ubi32_int0_ahb_clk =3D { + .halt_reg =3D 0x2878c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2878c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_nssnoc_ubi32_int0_ahb_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_int_cfg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_ubi32_nc_axi0_1_clk =3D { + .halt_reg =3D 0x287bc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x287bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_nssnoc_ubi32_nc_axi0_1_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_ubi32_nc_axi0_clk =3D { + .halt_reg =3D 0x28764, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28764, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_nssnoc_ubi32_nc_axi0_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port1_mac_clk =3D { + .halt_reg =3D 0x2824c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2824c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port1_mac_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port1_rx_clk =3D { + .halt_reg =3D 0x281a0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x281a0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port1_rx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port1_rx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port1_tx_clk =3D { + .halt_reg =3D 0x281a4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x281a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port1_tx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port1_tx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port2_mac_clk =3D { + .halt_reg =3D 0x28250, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28250, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port2_mac_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port2_rx_clk =3D { + .halt_reg =3D 0x281a8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x281a8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port2_rx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port2_rx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port2_tx_clk =3D { + .halt_reg =3D 0x281ac, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x281ac, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port2_tx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port2_tx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port3_mac_clk =3D { + .halt_reg =3D 0x28254, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28254, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port3_mac_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port3_rx_clk =3D { + .halt_reg =3D 0x281b0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x281b0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port3_rx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port3_rx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port3_tx_clk =3D { + .halt_reg =3D 0x281b4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x281b4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port3_tx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port3_tx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port4_mac_clk =3D { + .halt_reg =3D 0x28258, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28258, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port4_mac_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port4_rx_clk =3D { + .halt_reg =3D 0x281b8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x281b8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port4_rx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port4_rx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port4_tx_clk =3D { + .halt_reg =3D 0x281bc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x281bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port4_tx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port4_tx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port5_mac_clk =3D { + .halt_reg =3D 0x2825c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2825c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port5_mac_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port5_rx_clk =3D { + .halt_reg =3D 0x281c0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x281c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port5_rx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port5_rx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port5_tx_clk =3D { + .halt_reg =3D 0x281c4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x281c4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port5_tx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port5_tx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port6_mac_clk =3D { + .halt_reg =3D 0x28260, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28260, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port6_mac_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port6_rx_clk =3D { + .halt_reg =3D 0x281c8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x281c8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port6_rx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port6_rx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port6_tx_clk =3D { + .halt_reg =3D 0x281cc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x281cc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port6_tx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port6_tx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_edma_cfg_clk =3D { + .halt_reg =3D 0x2823c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2823c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ppe_edma_cfg_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_edma_clk =3D { + .halt_reg =3D 0x28238, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28238, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ppe_edma_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_switch_btq_clk =3D { + .halt_reg =3D 0x2827c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2827c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ppe_switch_btq_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_switch_cfg_clk =3D { + .halt_reg =3D 0x28234, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28234, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ppe_switch_cfg_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_switch_clk =3D { + .halt_reg =3D 0x28230, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28230, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ppe_switch_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_switch_ipe_clk =3D { + .halt_reg =3D 0x2822c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2822c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ppe_switch_ipe_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_ahb0_clk =3D { + .halt_reg =3D 0x28768, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28768, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_ahb0_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_cfg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_ahb1_clk =3D { + .halt_reg =3D 0x28770, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28770, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_ahb1_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_cfg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_ahb2_clk =3D { + .halt_reg =3D 0x28778, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28778, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_ahb2_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_cfg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_ahb3_clk =3D { + .halt_reg =3D 0x28780, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28780, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_ahb3_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_cfg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_axi0_clk =3D { + .halt_reg =3D 0x28790, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28790, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_axi0_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ubi_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_axi1_clk =3D { + .halt_reg =3D 0x28794, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28794, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_axi1_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ubi_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_axi2_clk =3D { + .halt_reg =3D 0x28798, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28798, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_axi2_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ubi_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_axi3_clk =3D { + .halt_reg =3D 0x2879c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2879c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_axi3_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ubi_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_core0_clk =3D { + .halt_reg =3D 0x28734, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28734, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_core0_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ubi0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_core1_clk =3D { + .halt_reg =3D 0x28738, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28738, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_core1_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ubi1_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_core2_clk =3D { + .halt_reg =3D 0x2873c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2873c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_core2_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ubi2_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_core3_clk =3D { + .halt_reg =3D 0x28740, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28740, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_core3_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ubi3_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_intr0_ahb_clk =3D { + .halt_reg =3D 0x2876c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2876c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_intr0_ahb_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_int_cfg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_intr1_ahb_clk =3D { + .halt_reg =3D 0x28774, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28774, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_intr1_ahb_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_int_cfg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_intr2_ahb_clk =3D { + .halt_reg =3D 0x2877c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2877c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_intr2_ahb_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_int_cfg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_intr3_ahb_clk =3D { + .halt_reg =3D 0x28784, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28784, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_intr3_ahb_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_int_cfg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_nc_axi0_clk =3D { + .halt_reg =3D 0x28744, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28744, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_nc_axi0_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_nc_axi1_clk =3D { + .halt_reg =3D 0x2874c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2874c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_nc_axi1_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_nc_axi2_clk =3D { + .halt_reg =3D 0x28754, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28754, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_nc_axi2_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_nc_axi3_clk =3D { + .halt_reg =3D 0x2875c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2875c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_nc_axi3_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_utcm0_clk =3D { + .halt_reg =3D 0x28748, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28748, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_utcm0_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_utcm1_clk =3D { + .halt_reg =3D 0x28750, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28750, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_utcm1_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_utcm2_clk =3D { + .halt_reg =3D 0x28758, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28758, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_utcm2_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ubi32_utcm3_clk =3D { + .halt_reg =3D 0x28760, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28760, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_ubi32_utcm3_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port1_rx_clk =3D { + .halt_reg =3D 0x28904, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28904, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_uniphy_port1_rx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port1_rx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port1_tx_clk =3D { + .halt_reg =3D 0x28908, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28908, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_uniphy_port1_tx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port1_tx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port2_rx_clk =3D { + .halt_reg =3D 0x2890c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2890c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_uniphy_port2_rx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port2_rx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port2_tx_clk =3D { + .halt_reg =3D 0x28910, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28910, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_uniphy_port2_tx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port2_tx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port3_rx_clk =3D { + .halt_reg =3D 0x28914, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28914, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_uniphy_port3_rx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port3_rx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port3_tx_clk =3D { + .halt_reg =3D 0x28918, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28918, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_uniphy_port3_tx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port3_tx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port4_rx_clk =3D { + .halt_reg =3D 0x2891c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2891c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_uniphy_port4_rx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port4_rx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port4_tx_clk =3D { + .halt_reg =3D 0x28920, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28920, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_uniphy_port4_tx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port4_tx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port5_rx_clk =3D { + .halt_reg =3D 0x28924, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28924, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_uniphy_port5_rx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port5_rx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port5_tx_clk =3D { + .halt_reg =3D 0x28928, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28928, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_uniphy_port5_tx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port5_tx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port6_rx_clk =3D { + .halt_reg =3D 0x2892c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2892c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_uniphy_port6_rx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port6_rx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port6_tx_clk =3D { + .halt_reg =3D 0x28930, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28930, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_uniphy_port6_tx_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_port6_tx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_xgmac0_ptp_ref_clk =3D { + .halt_reg =3D 0x28264, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28264, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_xgmac0_ptp_ref_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_xgmac1_ptp_ref_clk =3D { + .halt_reg =3D 0x28268, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28268, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_xgmac1_ptp_ref_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_xgmac2_ptp_ref_clk =3D { + .halt_reg =3D 0x2826c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2826c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_xgmac2_ptp_ref_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_xgmac2_ptp_ref_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_xgmac3_ptp_ref_clk =3D { + .halt_reg =3D 0x28270, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28270, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_xgmac3_ptp_ref_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_xgmac3_ptp_ref_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_xgmac4_ptp_ref_clk =3D { + .halt_reg =3D 0x28274, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28274, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_xgmac4_ptp_ref_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_xgmac4_ptp_ref_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_xgmac5_ptp_ref_clk =3D { + .halt_reg =3D 0x28278, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28278, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_xgmac5_ptp_ref_clk", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &nss_cc_xgmac5_ptp_ref_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *nss_cc_ipq9574_clocks[] =3D { + [NSS_CC_CE_APB_CLK] =3D &nss_cc_ce_apb_clk.clkr, + [NSS_CC_CE_AXI_CLK] =3D &nss_cc_ce_axi_clk.clkr, + [NSS_CC_CE_CLK_SRC] =3D &nss_cc_ce_clk_src.clkr, + [NSS_CC_CFG_CLK_SRC] =3D &nss_cc_cfg_clk_src.clkr, + [NSS_CC_CLC_AXI_CLK] =3D &nss_cc_clc_axi_clk.clkr, + [NSS_CC_CLC_CLK_SRC] =3D &nss_cc_clc_clk_src.clkr, + [NSS_CC_CRYPTO_CLK] =3D &nss_cc_crypto_clk.clkr, + [NSS_CC_CRYPTO_CLK_SRC] =3D &nss_cc_crypto_clk_src.clkr, + [NSS_CC_CRYPTO_PPE_CLK] =3D &nss_cc_crypto_ppe_clk.clkr, + [NSS_CC_HAQ_AHB_CLK] =3D &nss_cc_haq_ahb_clk.clkr, + [NSS_CC_HAQ_AXI_CLK] =3D &nss_cc_haq_axi_clk.clkr, + [NSS_CC_HAQ_CLK_SRC] =3D &nss_cc_haq_clk_src.clkr, + [NSS_CC_IMEM_AHB_CLK] =3D &nss_cc_imem_ahb_clk.clkr, + [NSS_CC_IMEM_CLK_SRC] =3D &nss_cc_imem_clk_src.clkr, + [NSS_CC_IMEM_QSB_CLK] =3D &nss_cc_imem_qsb_clk.clkr, + [NSS_CC_INT_CFG_CLK_SRC] =3D &nss_cc_int_cfg_clk_src.clkr, + [NSS_CC_NSS_CSR_CLK] =3D &nss_cc_nss_csr_clk.clkr, + [NSS_CC_NSSNOC_CE_APB_CLK] =3D &nss_cc_nssnoc_ce_apb_clk.clkr, + [NSS_CC_NSSNOC_CE_AXI_CLK] =3D &nss_cc_nssnoc_ce_axi_clk.clkr, + [NSS_CC_NSSNOC_CLC_AXI_CLK] =3D &nss_cc_nssnoc_clc_axi_clk.clkr, + [NSS_CC_NSSNOC_CRYPTO_CLK] =3D &nss_cc_nssnoc_crypto_clk.clkr, + [NSS_CC_NSSNOC_HAQ_AHB_CLK] =3D &nss_cc_nssnoc_haq_ahb_clk.clkr, + [NSS_CC_NSSNOC_HAQ_AXI_CLK] =3D &nss_cc_nssnoc_haq_axi_clk.clkr, + [NSS_CC_NSSNOC_IMEM_AHB_CLK] =3D &nss_cc_nssnoc_imem_ahb_clk.clkr, + [NSS_CC_NSSNOC_IMEM_QSB_CLK] =3D &nss_cc_nssnoc_imem_qsb_clk.clkr, + [NSS_CC_NSSNOC_NSS_CSR_CLK] =3D &nss_cc_nssnoc_nss_csr_clk.clkr, + [NSS_CC_NSSNOC_PPE_CFG_CLK] =3D &nss_cc_nssnoc_ppe_cfg_clk.clkr, + [NSS_CC_NSSNOC_PPE_CLK] =3D &nss_cc_nssnoc_ppe_clk.clkr, + [NSS_CC_NSSNOC_UBI32_AHB0_CLK] =3D &nss_cc_nssnoc_ubi32_ahb0_clk.clkr, + [NSS_CC_NSSNOC_UBI32_AXI0_CLK] =3D &nss_cc_nssnoc_ubi32_axi0_clk.clkr, + [NSS_CC_NSSNOC_UBI32_INT0_AHB_CLK] =3D + &nss_cc_nssnoc_ubi32_int0_ahb_clk.clkr, + [NSS_CC_NSSNOC_UBI32_NC_AXI0_1_CLK] =3D + &nss_cc_nssnoc_ubi32_nc_axi0_1_clk.clkr, + [NSS_CC_NSSNOC_UBI32_NC_AXI0_CLK] =3D + &nss_cc_nssnoc_ubi32_nc_axi0_clk.clkr, + [NSS_CC_PORT1_MAC_CLK] =3D &nss_cc_port1_mac_clk.clkr, + [NSS_CC_PORT1_RX_CLK] =3D &nss_cc_port1_rx_clk.clkr, + [NSS_CC_PORT1_RX_CLK_SRC] =3D &nss_cc_port1_rx_clk_src.clkr, + [NSS_CC_PORT1_RX_DIV_CLK_SRC] =3D &nss_cc_port1_rx_div_clk_src.clkr, + [NSS_CC_PORT1_TX_CLK] =3D &nss_cc_port1_tx_clk.clkr, + [NSS_CC_PORT1_TX_CLK_SRC] =3D &nss_cc_port1_tx_clk_src.clkr, + [NSS_CC_PORT1_TX_DIV_CLK_SRC] =3D &nss_cc_port1_tx_div_clk_src.clkr, + [NSS_CC_PORT2_MAC_CLK] =3D &nss_cc_port2_mac_clk.clkr, + [NSS_CC_PORT2_RX_CLK] =3D &nss_cc_port2_rx_clk.clkr, + [NSS_CC_PORT2_RX_CLK_SRC] =3D &nss_cc_port2_rx_clk_src.clkr, + [NSS_CC_PORT2_RX_DIV_CLK_SRC] =3D &nss_cc_port2_rx_div_clk_src.clkr, + [NSS_CC_PORT2_TX_CLK] =3D &nss_cc_port2_tx_clk.clkr, + [NSS_CC_PORT2_TX_CLK_SRC] =3D &nss_cc_port2_tx_clk_src.clkr, + [NSS_CC_PORT2_TX_DIV_CLK_SRC] =3D &nss_cc_port2_tx_div_clk_src.clkr, + [NSS_CC_PORT3_MAC_CLK] =3D &nss_cc_port3_mac_clk.clkr, + [NSS_CC_PORT3_RX_CLK] =3D &nss_cc_port3_rx_clk.clkr, + [NSS_CC_PORT3_RX_CLK_SRC] =3D &nss_cc_port3_rx_clk_src.clkr, + [NSS_CC_PORT3_RX_DIV_CLK_SRC] =3D &nss_cc_port3_rx_div_clk_src.clkr, + [NSS_CC_PORT3_TX_CLK] =3D &nss_cc_port3_tx_clk.clkr, + [NSS_CC_PORT3_TX_CLK_SRC] =3D &nss_cc_port3_tx_clk_src.clkr, + [NSS_CC_PORT3_TX_DIV_CLK_SRC] =3D &nss_cc_port3_tx_div_clk_src.clkr, + [NSS_CC_PORT4_MAC_CLK] =3D &nss_cc_port4_mac_clk.clkr, + [NSS_CC_PORT4_RX_CLK] =3D &nss_cc_port4_rx_clk.clkr, + [NSS_CC_PORT4_RX_CLK_SRC] =3D &nss_cc_port4_rx_clk_src.clkr, + [NSS_CC_PORT4_RX_DIV_CLK_SRC] =3D &nss_cc_port4_rx_div_clk_src.clkr, + [NSS_CC_PORT4_TX_CLK] =3D &nss_cc_port4_tx_clk.clkr, + [NSS_CC_PORT4_TX_CLK_SRC] =3D &nss_cc_port4_tx_clk_src.clkr, + [NSS_CC_PORT4_TX_DIV_CLK_SRC] =3D &nss_cc_port4_tx_div_clk_src.clkr, + [NSS_CC_PORT5_MAC_CLK] =3D &nss_cc_port5_mac_clk.clkr, + [NSS_CC_PORT5_RX_CLK] =3D &nss_cc_port5_rx_clk.clkr, + [NSS_CC_PORT5_RX_CLK_SRC] =3D &nss_cc_port5_rx_clk_src.clkr, + [NSS_CC_PORT5_RX_DIV_CLK_SRC] =3D &nss_cc_port5_rx_div_clk_src.clkr, + [NSS_CC_PORT5_TX_CLK] =3D &nss_cc_port5_tx_clk.clkr, + [NSS_CC_PORT5_TX_CLK_SRC] =3D &nss_cc_port5_tx_clk_src.clkr, + [NSS_CC_PORT5_TX_DIV_CLK_SRC] =3D &nss_cc_port5_tx_div_clk_src.clkr, + [NSS_CC_PORT6_MAC_CLK] =3D &nss_cc_port6_mac_clk.clkr, + [NSS_CC_PORT6_RX_CLK] =3D &nss_cc_port6_rx_clk.clkr, + [NSS_CC_PORT6_RX_CLK_SRC] =3D &nss_cc_port6_rx_clk_src.clkr, + [NSS_CC_PORT6_RX_DIV_CLK_SRC] =3D &nss_cc_port6_rx_div_clk_src.clkr, + [NSS_CC_PORT6_TX_CLK] =3D &nss_cc_port6_tx_clk.clkr, + [NSS_CC_PORT6_TX_CLK_SRC] =3D &nss_cc_port6_tx_clk_src.clkr, + [NSS_CC_PORT6_TX_DIV_CLK_SRC] =3D &nss_cc_port6_tx_div_clk_src.clkr, + [NSS_CC_PPE_CLK_SRC] =3D &nss_cc_ppe_clk_src.clkr, + [NSS_CC_PPE_EDMA_CFG_CLK] =3D &nss_cc_ppe_edma_cfg_clk.clkr, + [NSS_CC_PPE_EDMA_CLK] =3D &nss_cc_ppe_edma_clk.clkr, + [NSS_CC_PPE_SWITCH_BTQ_CLK] =3D &nss_cc_ppe_switch_btq_clk.clkr, + [NSS_CC_PPE_SWITCH_CFG_CLK] =3D &nss_cc_ppe_switch_cfg_clk.clkr, + [NSS_CC_PPE_SWITCH_CLK] =3D &nss_cc_ppe_switch_clk.clkr, + [NSS_CC_PPE_SWITCH_IPE_CLK] =3D &nss_cc_ppe_switch_ipe_clk.clkr, + [NSS_CC_UBI0_CLK_SRC] =3D &nss_cc_ubi0_clk_src.clkr, + [NSS_CC_UBI0_DIV_CLK_SRC] =3D &nss_cc_ubi0_div_clk_src.clkr, + [NSS_CC_UBI1_CLK_SRC] =3D &nss_cc_ubi1_clk_src.clkr, + [NSS_CC_UBI1_DIV_CLK_SRC] =3D &nss_cc_ubi1_div_clk_src.clkr, + [NSS_CC_UBI2_CLK_SRC] =3D &nss_cc_ubi2_clk_src.clkr, + [NSS_CC_UBI2_DIV_CLK_SRC] =3D &nss_cc_ubi2_div_clk_src.clkr, + [NSS_CC_UBI32_AHB0_CLK] =3D &nss_cc_ubi32_ahb0_clk.clkr, + [NSS_CC_UBI32_AHB1_CLK] =3D &nss_cc_ubi32_ahb1_clk.clkr, + [NSS_CC_UBI32_AHB2_CLK] =3D &nss_cc_ubi32_ahb2_clk.clkr, + [NSS_CC_UBI32_AHB3_CLK] =3D &nss_cc_ubi32_ahb3_clk.clkr, + [NSS_CC_UBI32_AXI0_CLK] =3D &nss_cc_ubi32_axi0_clk.clkr, + [NSS_CC_UBI32_AXI1_CLK] =3D &nss_cc_ubi32_axi1_clk.clkr, + [NSS_CC_UBI32_AXI2_CLK] =3D &nss_cc_ubi32_axi2_clk.clkr, + [NSS_CC_UBI32_AXI3_CLK] =3D &nss_cc_ubi32_axi3_clk.clkr, + [NSS_CC_UBI32_CORE0_CLK] =3D &nss_cc_ubi32_core0_clk.clkr, + [NSS_CC_UBI32_CORE1_CLK] =3D &nss_cc_ubi32_core1_clk.clkr, + [NSS_CC_UBI32_CORE2_CLK] =3D &nss_cc_ubi32_core2_clk.clkr, + [NSS_CC_UBI32_CORE3_CLK] =3D &nss_cc_ubi32_core3_clk.clkr, + [NSS_CC_UBI32_INTR0_AHB_CLK] =3D &nss_cc_ubi32_intr0_ahb_clk.clkr, + [NSS_CC_UBI32_INTR1_AHB_CLK] =3D &nss_cc_ubi32_intr1_ahb_clk.clkr, + [NSS_CC_UBI32_INTR2_AHB_CLK] =3D &nss_cc_ubi32_intr2_ahb_clk.clkr, + [NSS_CC_UBI32_INTR3_AHB_CLK] =3D &nss_cc_ubi32_intr3_ahb_clk.clkr, + [NSS_CC_UBI32_NC_AXI0_CLK] =3D &nss_cc_ubi32_nc_axi0_clk.clkr, + [NSS_CC_UBI32_NC_AXI1_CLK] =3D &nss_cc_ubi32_nc_axi1_clk.clkr, + [NSS_CC_UBI32_NC_AXI2_CLK] =3D &nss_cc_ubi32_nc_axi2_clk.clkr, + [NSS_CC_UBI32_NC_AXI3_CLK] =3D &nss_cc_ubi32_nc_axi3_clk.clkr, + [NSS_CC_UBI32_UTCM0_CLK] =3D &nss_cc_ubi32_utcm0_clk.clkr, + [NSS_CC_UBI32_UTCM1_CLK] =3D &nss_cc_ubi32_utcm1_clk.clkr, + [NSS_CC_UBI32_UTCM2_CLK] =3D &nss_cc_ubi32_utcm2_clk.clkr, + [NSS_CC_UBI32_UTCM3_CLK] =3D &nss_cc_ubi32_utcm3_clk.clkr, + [NSS_CC_UBI3_CLK_SRC] =3D &nss_cc_ubi3_clk_src.clkr, + [NSS_CC_UBI3_DIV_CLK_SRC] =3D &nss_cc_ubi3_div_clk_src.clkr, + [NSS_CC_UBI_AXI_CLK_SRC] =3D &nss_cc_ubi_axi_clk_src.clkr, + [NSS_CC_UBI_NC_AXI_BFDCD_CLK_SRC] =3D + &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr, + [NSS_CC_UNIPHY_PORT1_RX_CLK] =3D &nss_cc_uniphy_port1_rx_clk.clkr, + [NSS_CC_UNIPHY_PORT1_TX_CLK] =3D &nss_cc_uniphy_port1_tx_clk.clkr, + [NSS_CC_UNIPHY_PORT2_RX_CLK] =3D &nss_cc_uniphy_port2_rx_clk.clkr, + [NSS_CC_UNIPHY_PORT2_TX_CLK] =3D &nss_cc_uniphy_port2_tx_clk.clkr, + [NSS_CC_UNIPHY_PORT3_RX_CLK] =3D &nss_cc_uniphy_port3_rx_clk.clkr, + [NSS_CC_UNIPHY_PORT3_TX_CLK] =3D &nss_cc_uniphy_port3_tx_clk.clkr, + [NSS_CC_UNIPHY_PORT4_RX_CLK] =3D &nss_cc_uniphy_port4_rx_clk.clkr, + [NSS_CC_UNIPHY_PORT4_TX_CLK] =3D &nss_cc_uniphy_port4_tx_clk.clkr, + [NSS_CC_UNIPHY_PORT5_RX_CLK] =3D &nss_cc_uniphy_port5_rx_clk.clkr, + [NSS_CC_UNIPHY_PORT5_TX_CLK] =3D &nss_cc_uniphy_port5_tx_clk.clkr, + [NSS_CC_UNIPHY_PORT6_RX_CLK] =3D &nss_cc_uniphy_port6_rx_clk.clkr, + [NSS_CC_UNIPHY_PORT6_TX_CLK] =3D &nss_cc_uniphy_port6_tx_clk.clkr, + [NSS_CC_XGMAC0_PTP_REF_CLK] =3D &nss_cc_xgmac0_ptp_ref_clk.clkr, + [NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC] =3D + &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr, + [NSS_CC_XGMAC1_PTP_REF_CLK] =3D &nss_cc_xgmac1_ptp_ref_clk.clkr, + [NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC] =3D + &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr, + [NSS_CC_XGMAC2_PTP_REF_CLK] =3D &nss_cc_xgmac2_ptp_ref_clk.clkr, + [NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC] =3D + &nss_cc_xgmac2_ptp_ref_div_clk_src.clkr, + [NSS_CC_XGMAC3_PTP_REF_CLK] =3D &nss_cc_xgmac3_ptp_ref_clk.clkr, + [NSS_CC_XGMAC3_PTP_REF_DIV_CLK_SRC] =3D + &nss_cc_xgmac3_ptp_ref_div_clk_src.clkr, + [NSS_CC_XGMAC4_PTP_REF_CLK] =3D &nss_cc_xgmac4_ptp_ref_clk.clkr, + [NSS_CC_XGMAC4_PTP_REF_DIV_CLK_SRC] =3D + &nss_cc_xgmac4_ptp_ref_div_clk_src.clkr, + [NSS_CC_XGMAC5_PTP_REF_CLK] =3D &nss_cc_xgmac5_ptp_ref_clk.clkr, + [NSS_CC_XGMAC5_PTP_REF_DIV_CLK_SRC] =3D + &nss_cc_xgmac5_ptp_ref_div_clk_src.clkr, + [UBI32_PLL] =3D &ubi32_pll.clkr, + [UBI32_PLL_MAIN] =3D &ubi32_pll_main.clkr, +}; + +static const struct qcom_reset_map nss_cc_ipq9574_resets[] =3D { + [NSS_CC_CE_BCR] =3D { 0x28400, 0 }, + [NSS_CC_CLC_BCR] =3D { 0x28600, 0 }, + [NSS_CC_EIP197_BCR] =3D { 0x16004, 0 }, + [NSS_CC_HAQ_BCR] =3D { 0x28300, 0 }, + [NSS_CC_IMEM_BCR] =3D { 0xe004, 0 }, + [NSS_CC_MAC_BCR] =3D { 0x28100, 0 }, + [NSS_CC_PPE_BCR] =3D { 0x28200, 0 }, + [NSS_CC_UBI_BCR] =3D { 0x28700, 0 }, + [NSS_CC_UNIPHY_BCR] =3D { 0x28900, 0 }, + [UBI3_CLKRST_CLAMP_ENABLE] =3D { 0x28a04, 9 }, + [UBI3_CORE_CLAMP_ENABLE] =3D { 0x28a04, 8 }, + [UBI2_CLKRST_CLAMP_ENABLE] =3D { 0x28a04, 7 }, + [UBI2_CORE_CLAMP_ENABLE] =3D { 0x28a04, 6 }, + [UBI1_CLKRST_CLAMP_ENABLE] =3D { 0x28a04, 5 }, + [UBI1_CORE_CLAMP_ENABLE] =3D { 0x28a04, 4 }, + [UBI0_CLKRST_CLAMP_ENABLE] =3D { 0x28a04, 3 }, + [UBI0_CORE_CLAMP_ENABLE] =3D { 0x28a04, 2 }, + [NSSNOC_NSS_CSR_ARES] =3D { 0x28a04, 1 }, + [NSS_CSR_ARES] =3D { 0x28a04, 0 }, + [PPE_BTQ_ARES] =3D { 0x28a08, 20 }, + [PPE_IPE_ARES] =3D { 0x28a08, 19 }, + [PPE_ARES] =3D { 0x28a08, 18 }, + [PPE_CFG_ARES] =3D { 0x28a08, 17 }, + [PPE_EDMA_ARES] =3D { 0x28a08, 16 }, + [PPE_EDMA_CFG_ARES] =3D { 0x28a08, 15 }, + [CRY_PPE_ARES] =3D { 0x28a08, 14 }, + [NSSNOC_PPE_ARES] =3D { 0x28a08, 13 }, + [NSSNOC_PPE_CFG_ARES] =3D { 0x28a08, 12 }, + [PORT1_MAC_ARES] =3D { 0x28a08, 11 }, + [PORT2_MAC_ARES] =3D { 0x28a08, 10 }, + [PORT3_MAC_ARES] =3D { 0x28a08, 9 }, + [PORT4_MAC_ARES] =3D { 0x28a08, 8 }, + [PORT5_MAC_ARES] =3D { 0x28a08, 7 }, + [PORT6_MAC_ARES] =3D { 0x28a08, 6 }, + [XGMAC0_PTP_REF_ARES] =3D { 0x28a08, 5 }, + [XGMAC1_PTP_REF_ARES] =3D { 0x28a08, 4 }, + [XGMAC2_PTP_REF_ARES] =3D { 0x28a08, 3 }, + [XGMAC3_PTP_REF_ARES] =3D { 0x28a08, 2 }, + [XGMAC4_PTP_REF_ARES] =3D { 0x28a08, 1 }, + [XGMAC5_PTP_REF_ARES] =3D { 0x28a08, 0 }, + [HAQ_AHB_ARES] =3D { 0x28a0c, 3 }, + [HAQ_AXI_ARES] =3D { 0x28a0c, 2 }, + [NSSNOC_HAQ_AHB_ARES] =3D { 0x28a0c, 1 }, + [NSSNOC_HAQ_AXI_ARES] =3D { 0x28a0c, 0 }, + [CE_APB_ARES] =3D { 0x28a10, 3 }, + [CE_AXI_ARES] =3D { 0x28a10, 2 }, + [NSSNOC_CE_APB_ARES] =3D { 0x28a10, 1 }, + [NSSNOC_CE_AXI_ARES] =3D { 0x28a10, 0 }, + [CRYPTO_ARES] =3D { 0x28a14, 1 }, + [NSSNOC_CRYPTO_ARES] =3D { 0x28a14, 0 }, + [NSSNOC_NC_AXI0_1_ARES] =3D { 0x28a1c, 28 }, + [UBI0_CORE_ARES] =3D { 0x28a1c, 27 }, + [UBI1_CORE_ARES] =3D { 0x28a1c, 26 }, + [UBI2_CORE_ARES] =3D { 0x28a1c, 25 }, + [UBI3_CORE_ARES] =3D { 0x28a1c, 24 }, + [NC_AXI0_ARES] =3D { 0x28a1c, 23 }, + [UTCM0_ARES] =3D { 0x28a1c, 22 }, + [NC_AXI1_ARES] =3D { 0x28a1c, 21 }, + [UTCM1_ARES] =3D { 0x28a1c, 20 }, + [NC_AXI2_ARES] =3D { 0x28a1c, 19 }, + [UTCM2_ARES] =3D { 0x28a1c, 18 }, + [NC_AXI3_ARES] =3D { 0x28a1c, 17 }, + [UTCM3_ARES] =3D { 0x28a1c, 16 }, + [NSSNOC_NC_AXI0_ARES] =3D { 0x28a1c, 15 }, + [AHB0_ARES] =3D { 0x28a1c, 14 }, + [INTR0_AHB_ARES] =3D { 0x28a1c, 13 }, + [AHB1_ARES] =3D { 0x28a1c, 12 }, + [INTR1_AHB_ARES] =3D { 0x28a1c, 11 }, + [AHB2_ARES] =3D { 0x28a1c, 10 }, + [INTR2_AHB_ARES] =3D { 0x28a1c, 9 }, + [AHB3_ARES] =3D { 0x28a1c, 8 }, + [INTR3_AHB_ARES] =3D { 0x28a1c, 7 }, + [NSSNOC_AHB0_ARES] =3D { 0x28a1c, 6 }, + [NSSNOC_INT0_AHB_ARES] =3D { 0x28a1c, 5 }, + [AXI0_ARES] =3D { 0x28a1c, 4 }, + [AXI1_ARES] =3D { 0x28a1c, 3 }, + [AXI2_ARES] =3D { 0x28a1c, 2 }, + [AXI3_ARES] =3D { 0x28a1c, 1 }, + [NSSNOC_AXI0_ARES] =3D { 0x28a1c, 0 }, + [IMEM_QSB_ARES] =3D { 0x28a20, 3 }, + [NSSNOC_IMEM_QSB_ARES] =3D { 0x28a20, 2 }, + [IMEM_AHB_ARES] =3D { 0x28a20, 1 }, + [NSSNOC_IMEM_AHB_ARES] =3D { 0x28a20, 0 }, + [UNIPHY_PORT1_RX_ARES] =3D { 0x28a24, 23 }, + [UNIPHY_PORT1_TX_ARES] =3D { 0x28a24, 22 }, + [UNIPHY_PORT2_RX_ARES] =3D { 0x28a24, 21 }, + [UNIPHY_PORT2_TX_ARES] =3D { 0x28a24, 20 }, + [UNIPHY_PORT3_RX_ARES] =3D { 0x28a24, 19 }, + [UNIPHY_PORT3_TX_ARES] =3D { 0x28a24, 18 }, + [UNIPHY_PORT4_RX_ARES] =3D { 0x28a24, 17 }, + [UNIPHY_PORT4_TX_ARES] =3D { 0x28a24, 16 }, + [UNIPHY_PORT5_RX_ARES] =3D { 0x28a24, 15 }, + [UNIPHY_PORT5_TX_ARES] =3D { 0x28a24, 14 }, + [UNIPHY_PORT6_RX_ARES] =3D { 0x28a24, 13 }, + [UNIPHY_PORT6_TX_ARES] =3D { 0x28a24, 12 }, + [PORT1_RX_ARES] =3D { 0x28a24, 11 }, + [PORT1_TX_ARES] =3D { 0x28a24, 10 }, + [PORT2_RX_ARES] =3D { 0x28a24, 9 }, + [PORT2_TX_ARES] =3D { 0x28a24, 8 }, + [PORT3_RX_ARES] =3D { 0x28a24, 7 }, + [PORT3_TX_ARES] =3D { 0x28a24, 6 }, + [PORT4_RX_ARES] =3D { 0x28a24, 5 }, + [PORT4_TX_ARES] =3D { 0x28a24, 4 }, + [PORT5_RX_ARES] =3D { 0x28a24, 3 }, + [PORT5_TX_ARES] =3D { 0x28a24, 2 }, + [PORT6_RX_ARES] =3D { 0x28a24, 1 }, + [PORT6_TX_ARES] =3D { 0x28a24, 0 }, + [PPE_FULL_RESET] =3D { .reg =3D 0x28a08, .bitmask =3D GENMASK(20, 17) }, + [UNIPHY0_SOFT_RESET] =3D { .reg =3D 0x28a24, .bitmask =3D GENMASK(23, 14)= }, + [UNIPHY1_SOFT_RESET] =3D { .reg =3D 0x28a24, .bitmask =3D GENMASK(15, 14)= }, + [UNIPHY2_SOFT_RESET] =3D { .reg =3D 0x28a24, .bitmask =3D GENMASK(13, 12)= }, + [UNIPHY_PORT1_ARES] =3D { .reg =3D 0x28a24, .bitmask =3D GENMASK(23, 22) = }, + [UNIPHY_PORT2_ARES] =3D { .reg =3D 0x28a24, .bitmask =3D GENMASK(21, 20) = }, + [UNIPHY_PORT3_ARES] =3D { .reg =3D 0x28a24, .bitmask =3D GENMASK(19, 18) = }, + [UNIPHY_PORT4_ARES] =3D { .reg =3D 0x28a24, .bitmask =3D GENMASK(17, 16) = }, + [UNIPHY_PORT5_ARES] =3D { .reg =3D 0x28a24, .bitmask =3D GENMASK(15, 14) = }, + [UNIPHY_PORT6_ARES] =3D { .reg =3D 0x28a24, .bitmask =3D GENMASK(13, 12) = }, + [NSSPORT1_RESET] =3D { .reg =3D 0x28a24, .bitmask =3D GENMASK(11, 10) }, + [NSSPORT2_RESET] =3D { .reg =3D 0x28a24, .bitmask =3D GENMASK(9, 8) }, + [NSSPORT3_RESET] =3D { .reg =3D 0x28a24, .bitmask =3D GENMASK(7, 6) }, + [NSSPORT4_RESET] =3D { .reg =3D 0x28a24, .bitmask =3D GENMASK(5, 4) }, + [NSSPORT5_RESET] =3D { .reg =3D 0x28a24, .bitmask =3D GENMASK(3, 2) }, + [NSSPORT6_RESET] =3D { .reg =3D 0x28a24, .bitmask =3D GENMASK(1, 0) }, + [EDMA_HW_RESET] =3D { .reg =3D 0x28a08, .bitmask =3D GENMASK(16, 15) }, +}; + +static const struct regmap_config nss_cc_ipq9574_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x28a34, + .fast_io =3D true, +}; + +static struct qcom_icc_hws_data icc_ipq9574_nss_hws[] =3D { + { MASTER_NSSNOC_PPE, SLAVE_NSSNOC_PPE, NSS_CC_NSSNOC_PPE_CLK }, + { MASTER_NSSNOC_PPE_CFG, SLAVE_NSSNOC_PPE_CFG, NSS_CC_NSSNOC_PPE_CFG_CLK = }, + { MASTER_NSSNOC_NSS_CSR, SLAVE_NSSNOC_NSS_CSR, NSS_CC_NSSNOC_NSS_CSR_CLK = }, + { MASTER_NSSNOC_IMEM_QSB, SLAVE_NSSNOC_IMEM_QSB, NSS_CC_NSSNOC_IMEM_QSB_C= LK }, + { MASTER_NSSNOC_IMEM_AHB, SLAVE_NSSNOC_IMEM_AHB, NSS_CC_NSSNOC_IMEM_AHB_C= LK }, +}; + +#define IPQ_NSSCC_ID (9574 * 2) /* some unique value */ + +static const struct qcom_cc_desc nss_cc_ipq9574_desc =3D { + .config =3D &nss_cc_ipq9574_regmap_config, + .clks =3D nss_cc_ipq9574_clocks, + .num_clks =3D ARRAY_SIZE(nss_cc_ipq9574_clocks), + .resets =3D nss_cc_ipq9574_resets, + .num_resets =3D ARRAY_SIZE(nss_cc_ipq9574_resets), + .icc_hws =3D icc_ipq9574_nss_hws, + .num_icc_hws =3D ARRAY_SIZE(icc_ipq9574_nss_hws), + .icc_first_node_id =3D IPQ_NSSCC_ID, +}; + +static const struct of_device_id nss_cc_ipq9574_match_table[] =3D { + { .compatible =3D "qcom,ipq9574-nsscc" }, + { } +}; +MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_match_table); + +static int nss_cc_ipq9574_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap =3D qcom_cc_map(pdev, &nss_cc_ipq9574_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); + + return qcom_cc_really_probe(&pdev->dev, &nss_cc_ipq9574_desc, regmap); +} + +static struct platform_driver nss_cc_ipq9574_driver =3D { + .probe =3D nss_cc_ipq9574_probe, + .driver =3D { + .name =3D "qcom,nsscc-ipq9574", + .of_match_table =3D nss_cc_ipq9574_match_table, + .sync_state =3D icc_sync_state, + }, +}; + +module_platform_driver(nss_cc_ipq9574_driver); + +MODULE_DESCRIPTION("QTI NSS_CC IPQ9574 Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Mon Nov 25 18:48:10 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 093D118DF85; Fri, 25 Oct 2024 03:56:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729828608; cv=none; b=etUI9/pNUiWrpu7AaKxza1LxdB0ahc3AyDTYYKgW/qGTGtOuSm3xo9RE5iFVX/Jl99aJDMco5XQfsEZu8naKP2ttWXWXKYTDUkI3bfD/3BFlaZOjFk6Lc/2V13IiREXZKLprx6/LxxdfizGnWEPaQn2PEv9trvg9vuNUDDlDbKQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729828608; c=relaxed/simple; bh=AH+HHGIO/o/sWWxoRxnAqmcRxBlMELbR8LBmt0WOCRw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pzrUDi80M0unkx2vZQD2xquP5neJXL/wY0XspqbGv8iAghtY3fJJnWyez/usjYdy7NtzvM6q5zSHn97WmKTalWyCbb/HvBHrnmQCtDD6ca7ggO1vBtGxvLHEa9oJS2FeSaKTaGkrKBORZ2AnkJ0GBPElP1pebukYaV3bnXRhu7c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=OehNgjUZ; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="OehNgjUZ" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49ON81YA025869; Fri, 25 Oct 2024 03:56:29 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= UzSiYHDIHbp9WCtwmEtL8yd4p2kGpD5VUSm+JHqQ1R4=; b=OehNgjUZIhwwJuzH 6SVTf83Ql7pnN9tbKKFhFdu9fa4p2QnB6c1BzpWxsaPl5/O0bpd5RytHyubnOmVe 6Bb46/D5JqyavEtyzZEG6kh6OfBw+N050XwPwWISci9GpI3XKKq8ytXb/JobbVoU YEHhSbl1fVBxGoZ7W/lXyNI/pLQd7XY4kojtI6EJCHFGajhnlT9h2QIKpznF71AD SV6I17AoJwR2ZMaUqj+6zNL4bbz/bcoYVF/NjcsAVn6v2lgWjCKXT5hnsPdYKJPT /glBhKKr8tLNJw+hwirsrIiBgCDLhI2F6R/aKDgwRYLUt6deomWcH8nWLiwjxbSt ++pDhg== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42em3wqmen-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 03:56:29 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49P3uStK001731 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 03:56:28 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 24 Oct 2024 20:56:20 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH v8 6/7] arm64: dts: qcom: ipq9574: Add nsscc node Date: Fri, 25 Oct 2024 09:25:19 +0530 Message-ID: <20241025035520.1841792-7-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025035520.1841792-1-quic_mmanikan@quicinc.com> References: <20241025035520.1841792-1-quic_mmanikan@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ajpfDWd9V4Y-PW1vOajmYi5qGx6dkNUy X-Proofpoint-ORIG-GUID: ajpfDWd9V4Y-PW1vOajmYi5qGx6dkNUy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 mlxlogscore=960 lowpriorityscore=0 malwarescore=0 suspectscore=0 spamscore=0 mlxscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410250026 Content-Type: text/plain; charset="utf-8" From: Devi Priya Add a node for the nss clock controller found on ipq9574 based devices. Signed-off-by: Devi Priya Signed-off-by: Manikanta Mylavarapu --- Changes in V8: - Add cmn_pll NSS_1200MHZ_CLK and PPE_353MHZ_CLK arch/arm64/boot/dts/qcom/ipq9574.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qc= om/ipq9574.dtsi index 93f66bb83c5a..34f3510ea7ec 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -12,6 +12,8 @@ #include #include #include +#include +#include #include =20 / { @@ -774,6 +776,26 @@ frame@b128000 { status =3D "disabled"; }; }; + + nsscc: clock-controller@39b00000 { + compatible =3D "qcom,ipq9574-nsscc"; + reg =3D <0x39b00000 0x80000>; + clocks =3D <&xo_board_clk>, + <&cmn_pll NSS_1200MHZ_CLK>, + <&cmn_pll PPE_353MHZ_CLK>, + <&gcc GPLL0_OUT_AUX>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&gcc GCC_NSSCC_CLK>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + #interconnect-cells =3D <1>; + }; }; =20 thermal-zones { --=20 2.34.1 From nobody Mon Nov 25 18:48:10 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FB8318E056; Fri, 25 Oct 2024 03:56:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729828615; cv=none; b=OTBi5Opf1gA0gCLK9X9C6P2ptEHgVBr1AedZasnab+MgX2nnHwmzVhr5LwQWxdlBd+vmFxCA7JMH3iEh+sbVmawg/Aq8OI/ZY+QFWKIwFMfdjU/rnCOGs166ESmlEpIv939vj+VK7p/cb56jjqbdN9a/rtth0MKjn7uaVmVlsq0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729828615; c=relaxed/simple; bh=VtWSGEiD4gEb1u8Ffeu5L3k/EsqVQcCny6MFSXIzQ58=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DnuN9z8/0WgziWAYwktDgcyURNv4NJP4WgZXP8R5QhC20ctO5F1rJ1UwHj1eb6W135lju2zXrNTL1Ux9uNaIDJSVE7MB+Z4gC3FEdkE/S6NQliUyeg92KIFLw9/n+3/COYXvWWzpnJ1wvcwZ+v6syHdwiOZo2hTMM7OX1IjbFns= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=cF3Xxqf1; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="cF3Xxqf1" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49P1nCnG028685; Fri, 25 Oct 2024 03:56:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= euG3zxgLa0YJs9k5VfGPvwsB7+E/wXLh/+6SGH2tEfs=; b=cF3Xxqf1+gdGt2TQ s+JPfjnKNO/VL2WDDfqRB/QGQeGNk+XPWfKYzEz2nH52oihRvqQOW/bgcMmdWfmG 9W7bGKJ+PToWUPh1kZeZ2uiowqA1neQ/azWy/0khpjYRAKhTZOBQcZrfX2TZV2mV vRcH1HpxRW0SQUIYBu/KIpiu7LsHK8AA++3nqfunOvsOL4NLi1Q/zFE9HdwjkqMU qGoVdTcnIVYp7T5VLuCe/Lb3BOeeON617hDiweqhsFvWj0RhPQ+fog1wZ+Q/azaC dwnvzF1JzpALzgVhwFq9LhW+7b+ogUVQKFk4r6I6hvYYbnrfuLa0JUsZCADbxPuI bQ6UnQ== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42fdtxkgpw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 03:56:36 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49P3uZlX016425 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 03:56:35 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 24 Oct 2024 20:56:28 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH v8 7/7] arm64: defconfig: Build NSS Clock Controller driver for IPQ9574 Date: Fri, 25 Oct 2024 09:25:20 +0530 Message-ID: <20241025035520.1841792-8-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025035520.1841792-1-quic_mmanikan@quicinc.com> References: <20241025035520.1841792-1-quic_mmanikan@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 6Yxxx9GrxMWZLTYo5gIjMw57HIDCUZR2 X-Proofpoint-ORIG-GUID: 6Yxxx9GrxMWZLTYo5gIjMw57HIDCUZR2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 mlxlogscore=881 priorityscore=1501 impostorscore=0 bulkscore=0 spamscore=0 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410250026 Content-Type: text/plain; charset="utf-8" From: Devi Priya NSSCC driver is needed to enable the ethernet interfaces present in RDP433 based on IPQ9574. Since this is not necessary for bootup enabling it as a module. Signed-off-by: Devi Priya Signed-off-by: Manikanta Mylavarapu --- Changes in V8: - No change arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5663ebf39748..da33e5c197d4 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1314,6 +1314,7 @@ CONFIG_IPQ_GCC_5332=3Dy CONFIG_IPQ_GCC_6018=3Dy CONFIG_IPQ_GCC_8074=3Dy CONFIG_IPQ_GCC_9574=3Dy +CONFIG_IPQ_NSSCC_9574=3Dm CONFIG_MSM_GCC_8916=3Dy CONFIG_MSM_MMCC_8994=3Dm CONFIG_MSM_GCC_8994=3Dy --=20 2.34.1