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[2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2fcb46017bdsm2135721fa.104.2024.10.25.08.23.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 08:23:01 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 25 Oct 2024 18:22:53 +0300 Subject: [PATCH v2 1/2] dt-bindings: cache: qcom,llcc: document SAR2130P and SAR1130P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241025-sar2130p-llcc-v2-1-7455dc40e952@linaro.org> References: <20241025-sar2130p-llcc-v2-0-7455dc40e952@linaro.org> In-Reply-To: <20241025-sar2130p-llcc-v2-0-7455dc40e952@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Conor Dooley , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2065; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=SxzqUFuvQeeNvZs+W4DmL3KehVYMr+8uYq67jXqmhRc=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnG7fOm1q1Vd3yFZMwizAnp7TyTaf/TKKfO/afv mFk1IgZOVCJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZxu3zgAKCRAU23LtvoBl uDo0D/oDifmuBsFRQww+YaQ7ZgLbKcHlqRjgKtKI4EDT+wXWcDdZRxV+9Ft5yIBeT2y2FER+8tb shSdKLBrbncMHbd0ECReqKCnihRB8HIh1CDAHRzMJCgroCvwllflA8g97nzn4zKmWhfgGXjN78h U8Wk02VbzBJD+0BuvVIP9vrEYehOjv1bsVNn9TgsCznHn86GB0VjFgKEeZxOjRa9EQhFLsJjb/v WbTjAaoHj4DA+kH/FuB8vsLr4So0X+6GiFKKATHoFynzs+GHErJMRUrSS5xJjR7KtyRfq5RJCOX TzC82xEUofYI0+FrhZlYLG9AQA7I3d/pSN2UzwWiPQRekPU0QXIy8oaoylO5Y49D8HZtwH9qiNT KdUGcoa3mqo+h/JcIrO0NmnI/I49sohaKd1XJruDkxfjeuBYm/Zk4fQfNs9/ePgtHclwwo3OM0u NO9pHjMIxeh8sdW+7eje4oqBS3QzzRavb/KjKts8KzdpVlmtgzRF4Udjj71aIRoxhPfMdl0ciTu foStW8l7blYhDUehxJipeqbpjy+7nFCv48lxTAqcGnjPICUEhW9BBl/EwXQJVwO7mST4O2T+V8Q NAwazvgNmD+K8XS5Mq0Kplbz6eGYrVaXc5pFBsv171Kv15DEg7EWr56EpqqwK1Xodl8ExV5jgnk xPqlrIDL5sskbwg== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Describe the last level cache controller on the SAR2130P and SAR1130P platforms. They have 2 banks and also a separate register set to control scratchpad slice. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/cache/qcom,llcc.yaml | 28 ++++++++++++++++++= ++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Docum= entation/devicetree/bindings/cache/qcom,llcc.yaml index 68ea5f70b75f031cd8b23cf48d566c3a760dab77..2edacf28944c78b53b51744d787= f5d529ad83f3c 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -22,6 +22,8 @@ properties: enum: - qcom,qdu1000-llcc - qcom,sa8775p-llcc + - qcom,sar1130p-llcc + - qcom,sar2130p-llcc - qcom,sc7180-llcc - qcom,sc7280-llcc - qcom,sc8180x-llcc @@ -62,6 +64,32 @@ required: - reg-names =20 allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sar1130p-llcc + - qcom,sar2130p-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC broadcast OR register region + - description: LLCC broadcast AND register region + - description: LLCC scratchpad broadcast OR register region + - description: LLCC scratchpad broadcast AND register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc_broadcast_base + - const: llcc_broadcast_and_base + - const: llcc_scratchpad_broadcast_base + - const: llcc_scratchpad_broadcast_and_base + - if: properties: compatible: --=20 2.39.5 From nobody Mon Nov 25 17:32:41 2024 Received: from mail-lj1-f174.google.com (mail-lj1-f174.google.com [209.85.208.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EEFF20D4E4 for ; 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[2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2fcb46017bdsm2135721fa.104.2024.10.25.08.23.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 08:23:05 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 25 Oct 2024 18:22:54 +0300 Subject: [PATCH v2 2/2] soc: qcom: llcc: add support for SAR2130P and SAR1130P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241025-sar2130p-llcc-v2-2-7455dc40e952@linaro.org> References: <20241025-sar2130p-llcc-v2-0-7455dc40e952@linaro.org> In-Reply-To: <20241025-sar2130p-llcc-v2-0-7455dc40e952@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Conor Dooley , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=13837; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=8FbeicR87fUKKJuKBDf5OiGYnoTGgTDP768BkLjnows=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnG7fP0YqsE/JOEf2MgIk/aicNopE/N6HwEiRny S+NiqtnEveJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZxu3zwAKCRAU23LtvoBl uCO2EADAz5LE9YpH9WKIT3z3KBepk2dxGH8qbSjm8trAhHCGeulGwKDcuu2bYCTNmGKuaDm8+L8 tfmzGNyTEA0naacr7liogC9jYZQPJzOESppXJDWfry/SpycgZP4mWJq+d4LrwZpw2hx10mvcWDY ISxhWXt7RfVstYAeTngVrMeaZmOZQwXGf8UXlOCMB4IYs6PYOxeD3bVcsk2WYOcFP+ULmTf2u/L QWV70hVk1YEkE1vJ5klHPyCeKaoZHGLq8Rz0npKuQpoBwMNULOunDMML48TRvHGT4HwopLV2pIY LLCIiyj81FFguu3k0BoNhdKuqzrr4DgLj7f0YWYUB7C0C4OYUY33hiaQ3z5pb/9OzkA2GboeZGK zaowolFsMcY9lLgQbddKF5QDnV36kMw/dDLafpbooKAqTXH/vKw/yNcZtQROjV05wig6fTz46yz FgltI2hTDXajB2Tmmbls28ihsuUmnzWwhPz09n9m2ybvpfUSB3A/YS4vCAWJB8I8N84XE9Ll+RM KraHwZhOZ7Tem+gg5y3oLT5I4SxNhx6+LF/HWEn6aH85bZZFXPU90ZkS5P4VHBW7+fRRwAdFH/g yQPqfx3laXV2VB/8JIaQlWVsD8D8eoZFBUayeFkDAGo6q6cjvFDFH3L0PmXDTzVUUXu8M2/mo9R uAim5uZlR2heP7A== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Implement necessary support for the LLCC control on the SAR1130P and SAR2130P platforms. These two platforms use different ATTR1_MAX_CAP shift and also require manual override for num_banks. Signed-off-by: Dmitry Baryshkov --- drivers/soc/qcom/llcc-qcom.c | 460 +++++++++++++++++++++++++++++++++= +++- include/linux/soc/qcom/llcc-qcom.h | 12 + 2 files changed, 466 insertions(+), 6 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index a470285f54a875bf2262aac7b0f84ed8fd028ef1..49526486d1025995eb7678e8bbd= 3facf313721ea 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -136,6 +136,8 @@ struct qcom_llcc_config { const struct llcc_slice_config *sct_data; const u32 *reg_offset; const struct llcc_edac_reg_offset *edac_reg_offset; + u32 max_cap_shift; /* instead of ATTR1_MAX_CAP_SHIFT */ + u32 num_banks; int size; bool need_llcc_cfg; bool no_edac; @@ -298,6 +300,408 @@ static const struct llcc_slice_config sa8775p_data[] = =3D { }, }; =20 +static const struct llcc_slice_config sar1130p_data[] =3D { + { + .usecase_id =3D LLCC_CPUSS, + .slice_id =3D 1, + .max_cap =3D 4096, + .priority =3D 1, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + .activate_on_init =3D true, + }, { + .usecase_id =3D LLCC_VIDSC0, + .slice_id =3D 2, + .max_cap =3D 512, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_AUDIO, + .slice_id =3D 6, + .max_cap =3D 1024, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_CMPT, + .slice_id =3D 10, + .max_cap =3D 1024, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_GPUHTW, + .slice_id =3D 11, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_GPU, + .slice_id =3D 12, + .max_cap =3D 3072, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + .write_scid_en =3D true, + }, { + .usecase_id =3D LLCC_MMUHWT, + .slice_id =3D 13, + .max_cap =3D 512, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + }, { + .usecase_id =3D LLCC_DISP, + .slice_id =3D 16, + .max_cap =3D 12800, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_CVP, + .slice_id =3D 28, + .max_cap =3D 256, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_APTCM, + .slice_id =3D 26, + .max_cap =3D 2048, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x3, + .cache_mode =3D true, + .dis_cap_alloc =3D true, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_WRCACHE, + .slice_id =3D 31, + .max_cap =3D 256, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .activate_on_init =3D true, + }, { + .usecase_id =3D LLCC_AENPU, + .slice_id =3D 30, + .max_cap =3D 3072, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x1fff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_DISP_LEFT, + .slice_id =3D 17, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_DISP_RIGHT, + .slice_id =3D 18, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_EVCS_LEFT, + .slice_id =3D 22, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_EVCS_RIGHT, + .slice_id =3D 23, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, +}; + +static const struct llcc_slice_config sar2130p_data[] =3D { + { + .usecase_id =3D LLCC_CPUSS, + .slice_id =3D 1, + .max_cap =3D 6144, + .priority =3D 1, + .fixed_size =3D 0, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + .activate_on_init =3D true, + }, { + .usecase_id =3D LLCC_VIDSC0, + .slice_id =3D 2, + .max_cap =3D 128, + .priority =3D 2, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_AUDIO, + .slice_id =3D 6, + .max_cap =3D 1024, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_CMPT, + .slice_id =3D 10, + .max_cap =3D 1024, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_GPUHTW, + .slice_id =3D 11, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_GPU, + .slice_id =3D 12, + .max_cap =3D 1536, + .priority =3D 2, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + .write_scid_en =3D true, + }, { + .usecase_id =3D LLCC_MMUHWT, + .slice_id =3D 13, + .max_cap =3D 1024, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .activate_on_init =3D true, + }, { + .usecase_id =3D LLCC_DISP, + .slice_id =3D 16, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_APTCM, + .slice_id =3D 26, + .max_cap =3D 2048, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x3, + .cache_mode =3D true, + .dis_cap_alloc =3D true, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_WRCACHE, + .slice_id =3D 31, + .max_cap =3D 256, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .activate_on_init =3D true, + }, { + .usecase_id =3D LLCC_VIEYE, + .slice_id =3D 7, + .max_cap =3D 7168, + .priority =3D 4, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_VIDPTH, + .slice_id =3D 8, + .max_cap =3D 7168, + .priority =3D 4, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_GPUMV, + .slice_id =3D 9, + .max_cap =3D 2048, + .priority =3D 2, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_EVA_LEFT, + .slice_id =3D 20, + .max_cap =3D 7168, + .priority =3D 5, + .fixed_size =3D true, + .bonus_ways =3D 0x3ffffffc, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_EVA_RIGHT, + .slice_id =3D 21, + .max_cap =3D 7168, + .priority =3D 5, + .fixed_size =3D true, + .bonus_ways =3D 0x3ffffffc, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_EVAGAIN, + .slice_id =3D 25, + .max_cap =3D 1024, + .priority =3D 2, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_AENPU, + .slice_id =3D 30, + .max_cap =3D 3072, + .priority =3D 3, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_VIPTH, + .slice_id =3D 29, + .max_cap =3D 1024, + .priority =3D 4, + .fixed_size =3D true, + .bonus_ways =3D 0x3fffffff, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_DISP_LEFT, + .slice_id =3D 17, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_DISP_RIGHT, + .slice_id =3D 18, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_EVCS_LEFT, + .slice_id =3D 22, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_EVCS_RIGHT, + .slice_id =3D 23, + .max_cap =3D 0, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, { + .usecase_id =3D LLCC_SPAD, + .slice_id =3D 24, + .max_cap =3D 7168, + .priority =3D 1, + .fixed_size =3D true, + .bonus_ways =3D 0x0, + .res_ways =3D 0x0, + .cache_mode =3D 0, + .retain_on_pc =3D true, + }, +}; + static const struct llcc_slice_config sc7180_data[] =3D { { .usecase_id =3D LLCC_CPUSS, @@ -2687,6 +3091,30 @@ static const struct qcom_llcc_config sa8775p_cfg[] = =3D { }, }; =20 +static const struct qcom_llcc_config sar1130p_cfg[] =3D { + { + .sct_data =3D sar1130p_data, + .size =3D ARRAY_SIZE(sar1130p_data), + .need_llcc_cfg =3D true, + .reg_offset =3D llcc_v2_1_reg_offset, + .edac_reg_offset =3D &llcc_v2_1_edac_reg_offset, + .max_cap_shift =3D 0x0e, + .num_banks =3D 2, + }, +}; + +static const struct qcom_llcc_config sar2130p_cfg[] =3D { + { + .sct_data =3D sar2130p_data, + .size =3D ARRAY_SIZE(sar2130p_data), + .need_llcc_cfg =3D true, + .reg_offset =3D llcc_v2_1_reg_offset, + .edac_reg_offset =3D &llcc_v2_1_edac_reg_offset, + .max_cap_shift =3D 0x0e, + .num_banks =3D 2, + }, +}; + static const struct qcom_llcc_config sc7180_cfg[] =3D { { .sct_data =3D sc7180_data, @@ -2839,6 +3267,16 @@ static const struct qcom_sct_config sa8775p_cfgs =3D= { .num_config =3D ARRAY_SIZE(sa8775p_cfg), }; =20 +static const struct qcom_sct_config sar1130p_cfgs =3D { + .llcc_config =3D sar1130p_cfg, + .num_config =3D ARRAY_SIZE(sar1130p_cfg), +}; + +static const struct qcom_sct_config sar2130p_cfgs =3D { + .llcc_config =3D sar2130p_cfg, + .num_config =3D ARRAY_SIZE(sar2130p_cfg), +}; + static const struct qcom_sct_config sc7180_cfgs =3D { .llcc_config =3D sc7180_cfg, .num_config =3D ARRAY_SIZE(sc7180_cfg), @@ -3146,7 +3584,10 @@ static int _qcom_llcc_cfg_program(const struct llcc_= slice_config *config, */ max_cap_cacheline =3D max_cap_cacheline / drv_data->num_banks; max_cap_cacheline >>=3D CACHE_LINE_SIZE_SHIFT; - attr1_val |=3D max_cap_cacheline << ATTR1_MAX_CAP_SHIFT; + if (cfg->max_cap_shift) + attr1_val |=3D max_cap_cacheline << cfg->max_cap_shift; + else + attr1_val |=3D max_cap_cacheline << ATTR1_MAX_CAP_SHIFT; =20 attr1_cfg =3D LLCC_TRP_ATTR1_CFGn(config->slice_id); =20 @@ -3383,12 +3824,17 @@ static int qcom_llcc_probe(struct platform_device *= pdev) goto err; cfg =3D &cfgs->llcc_config[cfg_index]; =20 - ret =3D regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_ba= nks); - if (ret) - goto err; + if (cfg->num_banks) { + num_banks =3D cfg->num_banks; + } else { + ret =3D regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_b= anks); + if (ret) + goto err; + + num_banks &=3D LLCC_LB_CNT_MASK; + num_banks >>=3D LLCC_LB_CNT_SHIFT; + } =20 - num_banks &=3D LLCC_LB_CNT_MASK; - num_banks >>=3D LLCC_LB_CNT_SHIFT; drv_data->num_banks =3D num_banks; =20 drv_data->regmaps =3D devm_kcalloc(dev, num_banks, sizeof(*drv_data->regm= aps), GFP_KERNEL); @@ -3486,6 +3932,8 @@ static int qcom_llcc_probe(struct platform_device *pd= ev) static const struct of_device_id qcom_llcc_of_match[] =3D { { .compatible =3D "qcom,qdu1000-llcc", .data =3D &qdu1000_cfgs}, { .compatible =3D "qcom,sa8775p-llcc", .data =3D &sa8775p_cfgs }, + { .compatible =3D "qcom,sar1130p-llcc", .data =3D &sar1130p_cfgs }, + { .compatible =3D "qcom,sar2130p-llcc", .data =3D &sar2130p_cfgs }, { .compatible =3D "qcom,sc7180-llcc", .data =3D &sc7180_cfgs }, { .compatible =3D "qcom,sc7280-llcc", .data =3D &sc7280_cfgs }, { .compatible =3D "qcom,sc8180x-llcc", .data =3D &sc8180x_cfgs }, diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/ll= cc-qcom.h index 2f20281d4ad4352ef59e7b19148cd324c7991012..8e5d78fb4847a232ab17a66c277= 5552dcb287752 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -54,7 +54,19 @@ #define LLCC_CAMEXP4 52 #define LLCC_DISP_WB 53 #define LLCC_DISP_1 54 +#define LLCC_VIEYE 57 +#define LLCC_VIDPTH 58 +#define LLCC_GPUMV 59 +#define LLCC_EVA_LEFT 60 +#define LLCC_EVA_RIGHT 61 +#define LLCC_EVAGAIN 62 +#define LLCC_VIPTH 63 #define LLCC_VIDVSP 64 +#define LLCC_DISP_LEFT 65 +#define LLCC_DISP_RIGHT 66 +#define LLCC_EVCS_LEFT 67 +#define LLCC_EVCS_RIGHT 68 +#define LLCC_SPAD 69 =20 /** * struct llcc_slice_desc - Cache slice descriptor --=20 2.39.5