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[2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53b2e10a915sm209542e87.12.2024.10.25.08.04.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 08:04:13 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 25 Oct 2024 18:03:43 +0300 Subject: [PATCH v3 09/11] clk: qcom: tcsrcc-sm8550: add SAR2130P support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241025-sar2130p-clocks-v3-9-48f1842fd156@linaro.org> References: <20241025-sar2130p-clocks-v3-0-48f1842fd156@linaro.org> In-Reply-To: <20241025-sar2130p-clocks-v3-0-48f1842fd156@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Neil Armstrong , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2386; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=J01aZfvomEsVQEi/Nl/mHvq41KMRorLHAPm15NwwtBA=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnG7NVcO+TfaucfkkCZs49mJGy/3tSuSuD+ndpO NK9pIJyiOKJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZxuzVQAKCRAU23LtvoBl uCLDD/9wA7GtCzWO+qyhZpXE5uI+kquhx6JJFbQS/NrIsB1Ygyw2vA/9lZnLjk8Jsge5QcJuf6w 6jFvmFSDBK/RHQJiJyPZnCb3sf7dHt66j4nCtASJ3sAe1xS28c+dJ+ByTtz/tvFGg778aviaplt uEvZzdL4hbfDicw5mIn/rgBIIcPw8WF0Su8M1s/tBWegaNOoTCSKfsU3DBnuITV5TWsgzQ4VpAz Oj69t3+x2pxh5DEgsooHDBJcKBJI6qfcpIu4oyLLoF0ZVEGm7hqymm/L6S5Xx7TbPyfjWIi7Jzz 03T3J0JB3n46mAMNL+a0KdsNB5FqTinRRmRopLJbvRUb7l/yBt++G5eWJBijt9/gsDBYSHnah2Y wIu46ym4HlF2aUl2SJGmc5A0JS3w8AfJIvhSto567U+kSlyeUANOcrXrAUvFdn3v98DwXXIQhl2 +ykPAaBF0uGLDZzit4ea2SLr4OTE65WLp3rumNbTbckjGWpalyjcyrHWk3YJ6O0r8KRWF20Qz7V nehaCRxcE21vrRdY3Y+z/Da/ojvf0LRJW+aN9bb3NcDFSYYG3UFfFL5sp0jvMLCQZq2hQEYMEXh jOhQQwWrmtAERrnerIOp7IrpC9YrkQjXlw22F7INOCzZIkW3rYA5Xds1DEcD6eLwlkzeP3FXtWU ELrUMfdAD3LnUPg== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SAR2130P platform has the same TCSR Clock Controller as the SM8550, except for the lack of the UFS clocks. Extend the SM8550 TCSRCC driver to support SAR2130P. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/tcsrcc-sm8550.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/tcsrcc-sm8550.c b/drivers/clk/qcom/tcsrcc-sm8= 550.c index e5e8f2e82b949dae592ec3dda585138bf89cab37..41d73f92a000ab924560a0c2c9d= 8e85a9aaeb1b0 100644 --- a/drivers/clk/qcom/tcsrcc-sm8550.c +++ b/drivers/clk/qcom/tcsrcc-sm8550.c @@ -129,6 +129,13 @@ static struct clk_branch tcsr_usb3_clkref_en =3D { }, }; =20 +static struct clk_regmap *tcsr_cc_sar2130p_clocks[] =3D { + [TCSR_PCIE_0_CLKREF_EN] =3D &tcsr_pcie_0_clkref_en.clkr, + [TCSR_PCIE_1_CLKREF_EN] =3D &tcsr_pcie_1_clkref_en.clkr, + [TCSR_USB2_CLKREF_EN] =3D &tcsr_usb2_clkref_en.clkr, + [TCSR_USB3_CLKREF_EN] =3D &tcsr_usb3_clkref_en.clkr, +}; + static struct clk_regmap *tcsr_cc_sm8550_clocks[] =3D { [TCSR_PCIE_0_CLKREF_EN] =3D &tcsr_pcie_0_clkref_en.clkr, [TCSR_PCIE_1_CLKREF_EN] =3D &tcsr_pcie_1_clkref_en.clkr, @@ -146,6 +153,12 @@ static const struct regmap_config tcsr_cc_sm8550_regma= p_config =3D { .fast_io =3D true, }; =20 +static const struct qcom_cc_desc tcsr_cc_sar2130p_desc =3D { + .config =3D &tcsr_cc_sm8550_regmap_config, + .clks =3D tcsr_cc_sar2130p_clocks, + .num_clks =3D ARRAY_SIZE(tcsr_cc_sar2130p_clocks), +}; + static const struct qcom_cc_desc tcsr_cc_sm8550_desc =3D { .config =3D &tcsr_cc_sm8550_regmap_config, .clks =3D tcsr_cc_sm8550_clocks, @@ -153,7 +166,8 @@ static const struct qcom_cc_desc tcsr_cc_sm8550_desc = =3D { }; =20 static const struct of_device_id tcsr_cc_sm8550_match_table[] =3D { - { .compatible =3D "qcom,sm8550-tcsr" }, + { .compatible =3D "qcom,sar2130p-tcsr", .data =3D &tcsr_cc_sar2130p_desc = }, + { .compatible =3D "qcom,sm8550-tcsr", .data =3D &tcsr_cc_sm8550_desc }, { } }; MODULE_DEVICE_TABLE(of, tcsr_cc_sm8550_match_table); @@ -162,7 +176,7 @@ static int tcsr_cc_sm8550_probe(struct platform_device = *pdev) { struct regmap *regmap; =20 - regmap =3D qcom_cc_map(pdev, &tcsr_cc_sm8550_desc); + regmap =3D qcom_cc_map(pdev, of_device_get_match_data(&pdev->dev)); if (IS_ERR(regmap)) return PTR_ERR(regmap); =20 --=20 2.39.5