From nobody Mon Nov 25 16:49:28 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F49429CE5; Sat, 26 Oct 2024 00:06:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729901163; cv=none; b=Lv5wGfE64ZsZZ74CEdC39ZDJvHcFLYUOh9JukfzdFfnRUTPIYY/hOLqepdAl8OGjXR3YdPLvvaQWRdHPGHQEgEBTmkzpCyymsREW6jvkncgA/tGTtwbu8GHdSgf90MqobxCpQct7VG9r5c4exczNrg2DNnnf6wT8r37Mx+2PxcM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729901163; c=relaxed/simple; bh=ZwPg6ckOodnhLL6Qa5LKRiqPs1eFLPv7yR0MzR4z+Gg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YXxth0O7bbhqEnsMegoPvAiBL+6fIR4YmZDAt+Vye8HZaUwXYdpGSwUoqioeLJGRVTrrnzxQousR7ijLoMB2ox4r+uRWldN4cPZSpHdnoG4PCS96XidIGESSi6E6Llo/2zyeK8ZvNlvPJjELGUMFXkv+wzxRjSfNuZf4S5Nh5CY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=iu6hgcB3; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="iu6hgcB3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729901161; x=1761437161; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=ZwPg6ckOodnhLL6Qa5LKRiqPs1eFLPv7yR0MzR4z+Gg=; b=iu6hgcB3z0ZNfbDSbfG+UIg+5pJWo/DHaNpmEDCBw46218uNxcdMqCSP xZGG3//z18TJ8j9LQNSBU16pHUk1+TW2Uwx7t1jdritiri6+tnFvFGIad G6NQR9nkmQfGOU5kK1fwY7ekQpVU9/yheTdx1wsa8VGZ60h+WVx85mntB tPJ5XwGriWiL28a5ROAhykY7QClAKlQeVFaDitAnAG1yL3P8DOQMdMwKp 3HRJzSUWsXkW3WQUfO97XkP0HAT0XBEljnX5VNEYW3z20Yir3mMxDBu0/ tXz53jvZ/BMUBabwgTP2h33gdqXYaMxQM+AUbZpgabISemFB3k6gHYs9x A==; X-CSE-ConnectionGUID: z85Pb6fJShC/Se66hAUt9Q== X-CSE-MsgGUID: fVDEP/USRPGg3me3hDKG7Q== X-IronPort-AV: E=McAfee;i="6700,10204,11236"; a="40959167" X-IronPort-AV: E=Sophos;i="6.11,233,1725346800"; d="scan'208";a="40959167" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 17:05:55 -0700 X-CSE-ConnectionGUID: 7UjH2T7/T5m/7dfj43b5fQ== X-CSE-MsgGUID: Ts7PdoDtRGmcJzXXf0zdEA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,233,1725346800"; d="scan'208";a="104386866" Received: from jekeller-desk.jf.intel.com ([10.166.241.20]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 17:05:55 -0700 From: Jacob Keller Date: Fri, 25 Oct 2024 17:05:01 -0700 Subject: [PATCH net-next v2 9/9] ice: cleanup Rx queue context programming functions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241025-packing-pack-fields-and-ice-implementation-v2-9-734776c88e40@intel.com> References: <20241025-packing-pack-fields-and-ice-implementation-v2-0-734776c88e40@intel.com> In-Reply-To: <20241025-packing-pack-fields-and-ice-implementation-v2-0-734776c88e40@intel.com> To: Vladimir Oltean , Andrew Morton , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Tony Nguyen , Przemek Kitszel , Masahiro Yamada Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Jacob Keller X-Mailer: b4 0.14.1 The ice_copy_rxq_ctx_to_hw() and ice_write_rxq_ctx() functions perform some defensive checks which are typically frowned upon by kernel style guidelines. In particular, NULL checks on buffers which point to the stack are discouraged, especially when the functions are static and only called once. Checks of this sort only serve to hide potential programming error, as we will not produce the normal crash dump on a NULL access. In addition, ice_copy_rxq_ctx_to_hw() cannot fail in another way, so could be made void. Future support for VF Live Migration will need to introduce an inverse function for reading Rx queue context from HW registers to unpack it, as well as functions to pack and unpack Tx queue context from HW. Rather than copying these style issues into the new functions, lets first cleanup the existing code. For the ice_copy_rxq_ctx_to_hw() function: * Move the Rx queue index check out of this function. * Convert the function to a void return. * Use a simple int variable instead of a u8 for the for loop index, and initialize it inside the for loop. * Update the function description to better align with kernel doc style. For the ice_write_rxq_ctx() function: * Move the Rx queue index check into this function. * Update the function description with a Returns: to align with kernel doc style. These changes align the existing write functions to current kernel style, and will align with the style of the new functions added when we implement live migration in a future series. Signed-off-by: Jacob Keller --- drivers/net/ethernet/intel/ice/ice_common.c | 28 +++++++++++--------------= --- 1 file changed, 11 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethe= rnet/intel/ice/ice_common.c index 3cc56b85a480..54ebd2969203 100644 --- a/drivers/net/ethernet/intel/ice/ice_common.c +++ b/drivers/net/ethernet/intel/ice/ice_common.c @@ -1358,32 +1358,23 @@ int ice_reset(struct ice_hw *hw, enum ice_reset_req= req) } =20 /** - * ice_copy_rxq_ctx_to_hw + * ice_copy_rxq_ctx_to_hw - Copy packed Rx queue context to HW registers * @hw: pointer to the hardware structure * @rxq_ctx: pointer to the packed Rx queue context * @rxq_index: the index of the Rx queue - * - * Copies rxq context from dense structure to HW register space */ -static int ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, - const ice_rxq_ctx_buf_t *rxq_ctx, - u32 rxq_index) +static void ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, + const ice_rxq_ctx_buf_t *rxq_ctx, + u32 rxq_index) { - u8 i; - - if (rxq_index > QRX_CTRL_MAX_INDEX) - return -EINVAL; - /* Copy each dword separately to HW */ - for (i =3D 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { + for (int i =3D 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { u32 ctx =3D ((const u32 *)rxq_ctx)[i]; =20 wr32(hw, QRX_CONTEXT(i, rxq_index), ctx); =20 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, ctx); } - - return 0; } =20 #define ICE_CTX_STORE(struct_name, struct_field, width, lsb) \ @@ -1435,23 +1426,26 @@ static void ice_pack_rxq_ctx(const struct ice_rlan_= ctx *ctx, /** * ice_write_rxq_ctx - Write Rx Queue context to hardware * @hw: pointer to the hardware structure - * @rlan_ctx: pointer to the rxq context + * @rlan_ctx: pointer to the unpacked Rx queue context * @rxq_index: the index of the Rx queue * * Pack the sparse Rx Queue context into dense hardware format and write it * into the HW register space. + * + * Return: 0 on success, or -EINVAL if the Rx queue index is invalid. */ int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, u32 rxq_index) { ice_rxq_ctx_buf_t buf =3D {}; =20 - if (!rlan_ctx) + if (rxq_index > QRX_CTRL_MAX_INDEX) return -EINVAL; =20 ice_pack_rxq_ctx(rlan_ctx, &buf); + ice_copy_rxq_ctx_to_hw(hw, &buf, rxq_index); =20 - return ice_copy_rxq_ctx_to_hw(hw, &buf, rxq_index); + return 0; } =20 /* LAN Tx Queue Context */ --=20 2.47.0.265.g4ca455297942