From nobody Mon Nov 25 14:31:40 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A44220BB35; Fri, 25 Oct 2024 19:46:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729885574; cv=none; b=sqyuFMkVQRLYC7QqBfpN/I6cx9KcxKpi27MfEm+BH0ejp7hjj4M4BNBgnI15n0m/L55+Dq2fag8k2yP5uh5PjXuRQoZbuIrK8a/V6e5J8sc3M5MJjekiYKHNTo3sietVbx6Ev9Okv6dt7RDfhfTUttFI9p4AkcOsocwsL3Bl3BU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729885574; c=relaxed/simple; bh=xueF8NL4biPM6Tjkyld4sBVF/E87RcWAqU59Qy6ahiw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BAZPYnFYpufV7IdqB2IHcoO7GKQC3zHMoesedzFjPsLV08jlhTTGQhIsyN4S9JJ/+ASJgN0zrF1NIDHnbAhp5Vk73WEUdZ10SX4DiC7vo2KPGs74zPgkXHcyW6dzwaVZ2aK5MeF3O3bdp0EO37V8Hl3GvykEvGzRMtA9+VcPG4M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=JfRE3Bf5; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="JfRE3Bf5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1729885570; bh=xueF8NL4biPM6Tjkyld4sBVF/E87RcWAqU59Qy6ahiw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=JfRE3Bf5Gfu+OpGxQvbs1PSFqG70Pn28Sq2qOU7LQ4hw4W+nB67hd9iDvxcsSREL8 p1A7xZIQW0LnL0uAlmfFuyju47fyw5wCkybqvrQ0iysKmk0CNN/IeRPvsgskBfFpfb cRQGmn6gx9uvcSH/pBtOzK0eVcgHQZikWjxJHsRD4O9G6cSR18lERuuHtsvdKEB1UM uM+ELKf6iGPCJBfwkMCVILAsdRpXs271f0T1OL3D5U5/vJpffLXEoCfyUxbhT1VLTt Y38wrzXU4n1z55CNULfAO3TrDzcM8kEj5S+zjESHfZhrVuLDf2sx0Hg4KTI6Y9mBIK CtVOFr7/XZBLA== Received: from [192.168.1.54] (pool-100-2-116-133.nycmny.fios.verizon.net [100.2.116.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id BFB6817E3706; Fri, 25 Oct 2024 21:46:08 +0200 (CEST) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Fri, 25 Oct 2024 15:45:36 -0400 Subject: [PATCH RFC v2 1/5] pinctrl: mediatek: paris: Expose more configurations to GPIO set_config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241025-kselftest-gpio-set-get-config-v2-1-040d748840bb@collabora.com> References: <20241025-kselftest-gpio-set-get-config-v2-0-040d748840bb@collabora.com> In-Reply-To: <20241025-kselftest-gpio-set-get-config-v2-0-040d748840bb@collabora.com> To: Sean Wang , Linus Walleij , Matthias Brugger , AngeloGioacchino Del Regno , Bamvor Jian Zhang , Shuah Khan Cc: kernel@collabora.com, linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, kernelci@lists.linux.dev, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.2 Currently the set_config callback in the gpio_chip registered by the pinctrl_paris driver only supports configuring a single parameter on specific pins (the input debounce of the EINT controller, on pins that support it), even though many other configurations are already implemented and available through the pinctrl API for configuration of pins by the Devicetree and other drivers. Expose all configurations currently implemented through the GPIO API so they can also be set from userspace, which is particularly useful to allow testing them from userspace. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Chen-Yu Tsai --- drivers/pinctrl/mediatek/pinctrl-paris.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/med= iatek/pinctrl-paris.c index 87e958d827bf939aa6006794287698be4936f25e..c9455de266a447ab7f5446c1511= bef0ef9c9128e 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -255,10 +255,9 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, return err; } =20 -static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, - enum pin_config_param param, u32 arg) +static int mtk_paris_pin_config_set(struct mtk_pinctrl *hw, unsigned int p= in, + enum pin_config_param param, u32 arg) { - struct mtk_pinctrl *hw =3D pinctrl_dev_get_drvdata(pctldev); const struct mtk_pin_desc *desc; int err =3D -ENOTSUPP; u32 reg; @@ -795,9 +794,9 @@ static int mtk_pconf_group_set(struct pinctrl_dev *pctl= dev, unsigned group, int i, ret; =20 for (i =3D 0; i < num_configs; i++) { - ret =3D mtk_pinconf_set(pctldev, grp->pin, - pinconf_to_config_param(configs[i]), - pinconf_to_config_argument(configs[i])); + ret =3D mtk_paris_pin_config_set(hw, grp->pin, + pinconf_to_config_param(configs[i]), + pinconf_to_config_argument(configs[i])); if (ret < 0) return ret; =20 @@ -937,18 +936,19 @@ static int mtk_gpio_set_config(struct gpio_chip *chip= , unsigned int offset, { struct mtk_pinctrl *hw =3D gpiochip_get_data(chip); const struct mtk_pin_desc *desc; - u32 debounce; + enum pin_config_param param =3D pinconf_to_config_param(config); + u32 arg =3D pinconf_to_config_argument(config); =20 desc =3D (const struct mtk_pin_desc *)&hw->soc->pins[offset]; =20 - if (!hw->eint || - pinconf_to_config_param(config) !=3D PIN_CONFIG_INPUT_DEBOUNCE || - desc->eint.eint_n =3D=3D EINT_NA) - return -ENOTSUPP; + if (param =3D=3D PIN_CONFIG_INPUT_DEBOUNCE) { + if (!hw->eint || desc->eint.eint_n =3D=3D EINT_NA) + return -ENOTSUPP; =20 - debounce =3D pinconf_to_config_argument(config); + return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, arg); + } =20 - return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce); + return mtk_paris_pin_config_set(hw, offset, param, arg); } =20 static int mtk_build_gpiochip(struct mtk_pinctrl *hw) --=20 2.47.0 From nobody Mon Nov 25 14:31:40 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0209B20F3F6; Fri, 25 Oct 2024 19:46:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729885576; cv=none; b=aKY6ZGo94ITrATZfhMYkI+2pdfvNGVA0xd20JTTKkafIUj6+6GpBsk4WBLgN/7A8t5tr3iYcU6uGIigEHv0dzGZax0y4qthAs/NLdMPNvKK+34IF5n+omXdum9z3jStE/y4Exxvxgc+6O5RsblqS6qRdmCX65wtFoCw9spdN+MY= ARC-Message-Signature: i=1; a=rsa-sha256; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241025-kselftest-gpio-set-get-config-v2-2-040d748840bb@collabora.com> References: <20241025-kselftest-gpio-set-get-config-v2-0-040d748840bb@collabora.com> In-Reply-To: <20241025-kselftest-gpio-set-get-config-v2-0-040d748840bb@collabora.com> To: Sean Wang , Linus Walleij , Matthias Brugger , AngeloGioacchino Del Regno , Bamvor Jian Zhang , Shuah Khan Cc: kernel@collabora.com, linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, kernelci@lists.linux.dev, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.2 Currently the set_config callback in the gpio_chip registered by the pinctrl_moore driver only supports configuring a single parameter on specific pins (the input debounce of the EINT controller, on pins that support it), even though many other configurations are already implemented and available through the pinctrl API for configuration of pins by the Devicetree and other drivers. Expose all configurations currently implemented through the GPIO API so they can also be set from userspace, which is particularly useful to allow testing them from userspace. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Chen-Yu Tsai --- drivers/pinctrl/mediatek/pinctrl-moore.c | 283 ++++++++++++++++-----------= ---- 1 file changed, 144 insertions(+), 139 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/med= iatek/pinctrl-moore.c index aad4891223d3e060431a990bfabb6bd2cbb82087..de3494e9f228cef7f2eadf6a6ea= 2b3b708f1fb25 100644 --- a/drivers/pinctrl/mediatek/pinctrl-moore.c +++ b/drivers/pinctrl/mediatek/pinctrl-moore.c @@ -246,156 +246,160 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctl= dev, return 0; } =20 -static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long *configs, unsigned int num_configs) +static int mtk_moore_pin_config_set(struct mtk_pinctrl *hw, unsigned int p= in, + enum pin_config_param param, u32 arg) { - struct mtk_pinctrl *hw =3D pinctrl_dev_get_drvdata(pctldev); const struct mtk_pin_desc *desc; - u32 reg, param, arg; - int cfg, err =3D 0; + u32 reg; + int err =3D 0; =20 desc =3D (const struct mtk_pin_desc *)&hw->soc->pins[pin]; if (!desc->name) return -ENOTSUPP; =20 - for (cfg =3D 0; cfg < num_configs; cfg++) { - param =3D pinconf_to_config_param(configs[cfg]); - arg =3D pinconf_to_config_argument(configs[cfg]); - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - if (hw->soc->bias_set_combo) { - err =3D hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE); - if (err) - return err; - } else if (hw->soc->bias_disable_set) { - err =3D hw->soc->bias_disable_set(hw, desc); - if (err) - return err; - } else { - return -ENOTSUPP; - } - break; - case PIN_CONFIG_BIAS_PULL_UP: - if (hw->soc->bias_set_combo) { - err =3D hw->soc->bias_set_combo(hw, desc, 1, arg); - if (err) - return err; - } else if (hw->soc->bias_set) { - err =3D hw->soc->bias_set(hw, desc, 1); - if (err) - return err; - } else { - return -ENOTSUPP; - } - break; - case PIN_CONFIG_BIAS_PULL_DOWN: - if (hw->soc->bias_set_combo) { - err =3D hw->soc->bias_set_combo(hw, desc, 0, arg); - if (err) - return err; - } else if (hw->soc->bias_set) { - err =3D hw->soc->bias_set(hw, desc, 0); - if (err) - return err; - } else { - return -ENOTSUPP; - } - break; - case PIN_CONFIG_OUTPUT_ENABLE: - err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, - MTK_DISABLE); - if (err) - goto err; - - err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, - MTK_OUTPUT); + switch ((u32)param) { + case PIN_CONFIG_BIAS_DISABLE: + if (hw->soc->bias_set_combo) { + err =3D hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE); if (err) - goto err; - break; - case PIN_CONFIG_INPUT_ENABLE: - - if (hw->soc->ies_present) { - mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES, - MTK_ENABLE); - } - - err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, - MTK_INPUT); + return err; + } else if (hw->soc->bias_disable_set) { + err =3D hw->soc->bias_disable_set(hw, desc); if (err) - goto err; - break; - case PIN_CONFIG_SLEW_RATE: - err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR, - arg); + return err; + } else { + return -ENOTSUPP; + } + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (hw->soc->bias_set_combo) { + err =3D hw->soc->bias_set_combo(hw, desc, 1, arg); if (err) - goto err; - - break; - case PIN_CONFIG_OUTPUT: - err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, - MTK_OUTPUT); + return err; + } else if (hw->soc->bias_set) { + err =3D hw->soc->bias_set(hw, desc, 1); if (err) - goto err; - - err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, - arg); + return err; + } else { + return -ENOTSUPP; + } + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (hw->soc->bias_set_combo) { + err =3D hw->soc->bias_set_combo(hw, desc, 0, arg); if (err) - goto err; - break; - case PIN_CONFIG_INPUT_SCHMITT_ENABLE: - /* arg =3D 1: Input mode & SMT enable ; - * arg =3D 0: Output mode & SMT disable - */ - arg =3D arg ? 2 : 1; - err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, - arg & 1); + return err; + } else if (hw->soc->bias_set) { + err =3D hw->soc->bias_set(hw, desc, 0); if (err) - goto err; + return err; + } else { + return -ENOTSUPP; + } + break; + case PIN_CONFIG_OUTPUT_ENABLE: + err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, MTK_DISABLE); + if (err) + return err; + + err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_OUTPUT); + if (err) + return err; + break; + case PIN_CONFIG_INPUT_ENABLE: + + if (hw->soc->ies_present) { + mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES, MTK_ENABLE); + } + + err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_INPUT); + if (err) + return err; + break; + case PIN_CONFIG_SLEW_RATE: + err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR, arg); + if (err) + return err; + + break; + case PIN_CONFIG_OUTPUT: + err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_OUTPUT); + if (err) + return err; + + err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, arg); + if (err) + return err; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + /* arg =3D 1: Input mode & SMT enable ; + * arg =3D 0: Output mode & SMT disable + */ + arg =3D arg ? 2 : 1; + err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, arg & 1); + if (err) + return err; =20 - err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, - !!(arg & 2)); + err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, !!(arg & 2)); + if (err) + return err; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + if (hw->soc->drive_set) { + err =3D hw->soc->drive_set(hw, desc, arg); if (err) - goto err; - break; - case PIN_CONFIG_DRIVE_STRENGTH: - if (hw->soc->drive_set) { - err =3D hw->soc->drive_set(hw, desc, arg); - if (err) - return err; - } else { - err =3D -ENOTSUPP; - } - break; - case MTK_PIN_CONFIG_TDSEL: - case MTK_PIN_CONFIG_RDSEL: - reg =3D (param =3D=3D MTK_PIN_CONFIG_TDSEL) ? - PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL; - - err =3D mtk_hw_set_value(hw, desc, reg, arg); + return err; + } else { + return -ENOTSUPP; + } + break; + case MTK_PIN_CONFIG_TDSEL: + case MTK_PIN_CONFIG_RDSEL: + reg =3D (param =3D=3D MTK_PIN_CONFIG_TDSEL) ? + PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL; + + err =3D mtk_hw_set_value(hw, desc, reg, arg); + if (err) + return err; + break; + case MTK_PIN_CONFIG_PU_ADV: + case MTK_PIN_CONFIG_PD_ADV: + if (hw->soc->adv_pull_set) { + bool pullup; + + pullup =3D param =3D=3D MTK_PIN_CONFIG_PU_ADV; + err =3D hw->soc->adv_pull_set(hw, desc, pullup, arg); if (err) - goto err; - break; - case MTK_PIN_CONFIG_PU_ADV: - case MTK_PIN_CONFIG_PD_ADV: - if (hw->soc->adv_pull_set) { - bool pullup; - - pullup =3D param =3D=3D MTK_PIN_CONFIG_PU_ADV; - err =3D hw->soc->adv_pull_set(hw, desc, pullup, - arg); - if (err) - return err; - } else { - return -ENOTSUPP; - } - break; - default: - err =3D -ENOTSUPP; + return err; + } else { + return -ENOTSUPP; } + break; + default: + return -ENOTSUPP; + } + + return 0; +} + +static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct mtk_pinctrl *hw =3D pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param; + int cfg, err =3D 0; + u32 arg; + + for (cfg =3D 0; cfg < num_configs; cfg++) { + param =3D pinconf_to_config_param(configs[cfg]); + arg =3D pinconf_to_config_argument(configs[cfg]); + + err =3D mtk_moore_pin_config_set(hw, pin, param, arg); + if (err) + return err; } -err: - return err; + + return 0; } =20 static int mtk_pinconf_group_get(struct pinctrl_dev *pctldev, @@ -539,20 +543,21 @@ static int mtk_gpio_set_config(struct gpio_chip *chip= , unsigned int offset, { struct mtk_pinctrl *hw =3D gpiochip_get_data(chip); const struct mtk_pin_desc *desc; - u32 debounce; + enum pin_config_param param =3D pinconf_to_config_param(config); + u32 arg =3D pinconf_to_config_argument(config); =20 desc =3D (const struct mtk_pin_desc *)&hw->soc->pins[offset]; if (!desc->name) return -ENOTSUPP; =20 - if (!hw->eint || - pinconf_to_config_param(config) !=3D PIN_CONFIG_INPUT_DEBOUNCE || - desc->eint.eint_n =3D=3D (u16)EINT_NA) - return -ENOTSUPP; + if (param =3D=3D PIN_CONFIG_INPUT_DEBOUNCE) { + if (!hw->eint || desc->eint.eint_n =3D=3D (u16)EINT_NA) + return -ENOTSUPP; =20 - debounce =3D pinconf_to_config_argument(config); + return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, arg); + } =20 - return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce); + return mtk_moore_pin_config_set(hw, offset, param, arg); } =20 static int mtk_build_gpiochip(struct mtk_pinctrl *hw) --=20 2.47.0 From nobody Mon Nov 25 14:31:40 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E588F21441D; Fri, 25 Oct 2024 19:46:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729885578; cv=none; b=DnMptDIv8LXspmMwvn+YChG61E3kQOk3i2QWzgntON0dZVeR1gQJ2FxJjhrdJdDqXfOIXMX4Ln86f0Xzx1C0Y8E0ELusXtlDpL6fb7NrAt5qdDrIgjpXxLaTVsQonUFCs09a3YQO7Ky2AacOqpo55gE4QMFnY5Z07UfebOYCc1k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729885578; c=relaxed/simple; bh=IHDKkPuL6bGyn5e67txu92IjSUnnKlLm5rnqXrHDXfA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Fri, 25 Oct 2024 21:46:12 +0200 (CEST) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Fri, 25 Oct 2024 15:45:38 -0400 Subject: [PATCH RFC v2 3/5] pinctrl: mediatek: common: Expose more configurations to GPIO set_config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241025-kselftest-gpio-set-get-config-v2-3-040d748840bb@collabora.com> References: <20241025-kselftest-gpio-set-get-config-v2-0-040d748840bb@collabora.com> In-Reply-To: <20241025-kselftest-gpio-set-get-config-v2-0-040d748840bb@collabora.com> To: Sean Wang , Linus Walleij , Matthias Brugger , AngeloGioacchino Del Regno , Bamvor Jian Zhang , Shuah Khan Cc: kernel@collabora.com, linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, kernelci@lists.linux.dev, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.2 Currently the set_config callback in the gpio_chip registered by the pinctrl-mtk-common driver only supports configuring a single parameter on specific pins (the input debounce of the EINT controller, on pins that support it), even though many other configurations are already implemented and available through the pinctrl API for configuration of pins by the Devicetree and other drivers. Expose all configurations currently implemented through the GPIO API so they can also be set from userspace, which is particularly useful to allow testing them from userspace. Reviewed-by: Chen-Yu Tsai --- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 48 ++++++++++++++++-------= ---- 1 file changed, 28 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctr= l/mediatek/pinctrl-mtk-common.c index 91edb539925a49b4302866b9ac36f580cc189fb5..7f9764b474c4e7d0d4c3d6e542b= db7df0264daec 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -62,13 +62,12 @@ static unsigned int mtk_get_port(struct mtk_pinctrl *pc= tl, unsigned long pin) << pctl->devdata->port_shf; } =20 -static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, unsigned offset, - bool input) +static int mtk_common_pin_set_direction(struct mtk_pinctrl *pctl, + unsigned int offset, + bool input) { unsigned int reg_addr; unsigned int bit; - struct mtk_pinctrl *pctl =3D pinctrl_dev_get_drvdata(pctldev); =20 reg_addr =3D mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; bit =3D BIT(offset & pctl->devdata->mode_mask); @@ -86,6 +85,15 @@ static int mtk_pmx_gpio_set_direction(struct pinctrl_dev= *pctldev, return 0; } =20 +static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, unsigned int offset, + bool input) +{ + struct mtk_pinctrl *pctl =3D pinctrl_dev_get_drvdata(pctldev); + + return mtk_common_pin_set_direction(pctl, offset, input); +} + static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int valu= e) { unsigned int reg_addr; @@ -363,12 +371,11 @@ static int mtk_pconf_set_pull_select(struct mtk_pinct= rl *pctl, return 0; } =20 -static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev, +static int mtk_pconf_parse_conf(struct mtk_pinctrl *pctl, unsigned int pin, enum pin_config_param param, - enum pin_config_param arg) + u32 arg) { int ret =3D 0; - struct mtk_pinctrl *pctl =3D pinctrl_dev_get_drvdata(pctldev); =20 switch (param) { case PIN_CONFIG_BIAS_DISABLE: @@ -381,15 +388,15 @@ static int mtk_pconf_parse_conf(struct pinctrl_dev *p= ctldev, ret =3D mtk_pconf_set_pull_select(pctl, pin, true, false, arg); break; case PIN_CONFIG_INPUT_ENABLE: - mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true); + mtk_common_pin_set_direction(pctl, pin, true); ret =3D mtk_pconf_set_ies_smt(pctl, pin, arg, param); break; case PIN_CONFIG_OUTPUT: mtk_gpio_set(pctl->chip, pin, arg); - ret =3D mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false); + ret =3D mtk_common_pin_set_direction(pctl, pin, false); break; case PIN_CONFIG_INPUT_SCHMITT_ENABLE: - mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true); + mtk_common_pin_set_direction(pctl, pin, true); ret =3D mtk_pconf_set_ies_smt(pctl, pin, arg, param); break; case PIN_CONFIG_DRIVE_STRENGTH: @@ -421,7 +428,7 @@ static int mtk_pconf_group_set(struct pinctrl_dev *pctl= dev, unsigned group, int i, ret; =20 for (i =3D 0; i < num_configs; i++) { - ret =3D mtk_pconf_parse_conf(pctldev, g->pin, + ret =3D mtk_pconf_parse_conf(pctl, g->pin, pinconf_to_config_param(configs[i]), pinconf_to_config_argument(configs[i])); if (ret < 0) @@ -870,19 +877,20 @@ static int mtk_gpio_set_config(struct gpio_chip *chip= , unsigned offset, struct mtk_pinctrl *pctl =3D gpiochip_get_data(chip); const struct mtk_desc_pin *pin; unsigned long eint_n; - u32 debounce; + enum pin_config_param param =3D pinconf_to_config_param(config); + u32 arg =3D pinconf_to_config_argument(config); =20 - if (pinconf_to_config_param(config) !=3D PIN_CONFIG_INPUT_DEBOUNCE) - return -ENOTSUPP; + if (param =3D=3D PIN_CONFIG_INPUT_DEBOUNCE) { + pin =3D pctl->devdata->pins + offset; + if (pin->eint.eintnum =3D=3D NO_EINT_SUPPORT) + return -EINVAL; =20 - pin =3D pctl->devdata->pins + offset; - if (pin->eint.eintnum =3D=3D NO_EINT_SUPPORT) - return -EINVAL; + eint_n =3D pin->eint.eintnum; =20 - debounce =3D pinconf_to_config_argument(config); - eint_n =3D pin->eint.eintnum; + return mtk_eint_set_debounce(pctl->eint, eint_n, arg); + } =20 - return mtk_eint_set_debounce(pctl->eint, eint_n, debounce); + return mtk_pconf_parse_conf(pctl, offset, param, arg); } =20 static const struct gpio_chip mtk_gpio_chip =3D { --=20 2.47.0 From nobody Mon Nov 25 14:31:41 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3740120F3F0; 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Fri, 25 Oct 2024 21:46:14 +0200 (CEST) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Fri, 25 Oct 2024 15:45:39 -0400 Subject: [PATCH RFC v2 4/5] selftest: gpio: Add wait flag to gpio-mockup-cdev Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241025-kselftest-gpio-set-get-config-v2-4-040d748840bb@collabora.com> References: <20241025-kselftest-gpio-set-get-config-v2-0-040d748840bb@collabora.com> In-Reply-To: <20241025-kselftest-gpio-set-get-config-v2-0-040d748840bb@collabora.com> To: Sean Wang , Linus Walleij , Matthias Brugger , AngeloGioacchino Del Regno , Bamvor Jian Zhang , Shuah Khan Cc: kernel@collabora.com, linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, kernelci@lists.linux.dev, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.2 Add a -w flag to the gpio-mockup-cdev utility that causes the program to wait until a signal is received before exiting, even when its behavior is to retrieve the GPIO value of the line. This allows using this utility to keep a GPIO line configured even when in input mode, which will be relied on in other tests. Signed-off-by: N=C3=ADcolas F. R. A. Prado --- tools/testing/selftests/gpio/gpio-mockup-cdev.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/tools/testing/selftests/gpio/gpio-mockup-cdev.c b/tools/testin= g/selftests/gpio/gpio-mockup-cdev.c index d1640f44f8ac2a6fda7a5f75605f83fcaa165dc0..f674dcafa60a02cb1739f3cfae8= 963dc09efba74 100644 --- a/tools/testing/selftests/gpio/gpio-mockup-cdev.c +++ b/tools/testing/selftests/gpio/gpio-mockup-cdev.c @@ -15,6 +15,7 @@ #include #include #include +#include =20 #define CONSUMER "gpio-mockup-cdev" =20 @@ -95,6 +96,7 @@ static void usage(char *prog) printf(" (default is to leave bias unchanged):\n"); printf(" -l: set line active low (default is active high)\n"); printf(" -s: set line value (default is to get line value)\n"); + printf(" -w: wait even in get mode\n"); printf(" -u: uAPI version to use (default is 2)\n"); exit(-1); } @@ -120,13 +122,14 @@ int main(int argc, char *argv[]) unsigned int offset, val =3D 0, abiv; uint32_t flags_v1; uint64_t flags_v2; + bool wait =3D false; =20 abiv =3D 2; ret =3D 0; flags_v1 =3D GPIOHANDLE_REQUEST_INPUT; flags_v2 =3D GPIO_V2_LINE_FLAG_INPUT; =20 - while ((opt =3D getopt(argc, argv, "lb:s:u:")) !=3D -1) { + while ((opt =3D getopt(argc, argv, "lb:s:u:w")) !=3D -1) { switch (opt) { case 'l': flags_v1 |=3D GPIOHANDLE_REQUEST_ACTIVE_LOW; @@ -150,10 +153,14 @@ int main(int argc, char *argv[]) flags_v1 |=3D GPIOHANDLE_REQUEST_OUTPUT; flags_v2 &=3D ~GPIO_V2_LINE_FLAG_INPUT; flags_v2 |=3D GPIO_V2_LINE_FLAG_OUTPUT; + wait =3D true; break; case 'u': abiv =3D atoi(optarg); break; + case 'w': + wait =3D true; + break; default: usage(argv[0]); } @@ -183,9 +190,10 @@ int main(int argc, char *argv[]) return lfd; } =20 - if (flags_v2 & GPIO_V2_LINE_FLAG_OUTPUT) { + if (wait) wait_signal(); - } else { + + if (flags_v2 & GPIO_V2_LINE_FLAG_INPUT) { if (abiv =3D=3D 1) ret =3D get_value_v1(lfd); else --=20 2.47.0 From nobody Mon Nov 25 14:31:41 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 246A6215C67; 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Fri, 25 Oct 2024 21:46:16 +0200 (CEST) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Fri, 25 Oct 2024 15:45:40 -0400 Subject: [PATCH RFC v2 5/5] selftest: gpio: Add a new set-get config test Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241025-kselftest-gpio-set-get-config-v2-5-040d748840bb@collabora.com> References: <20241025-kselftest-gpio-set-get-config-v2-0-040d748840bb@collabora.com> In-Reply-To: <20241025-kselftest-gpio-set-get-config-v2-0-040d748840bb@collabora.com> To: Sean Wang , Linus Walleij , Matthias Brugger , AngeloGioacchino Del Regno , Bamvor Jian Zhang , Shuah Khan Cc: kernel@collabora.com, linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, kernelci@lists.linux.dev, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.2 Add a new kselftest that sets a configuration to a GPIO line and then gets it back to verify that it was correctly carried out by the driver. Setting a configuration is done through the GPIO uAPI, but retrieving it is done through the debugfs interface since that is the only place where it can be retrieved from userspace. The test reads the test plan from a YAML file, which includes the chips and pin settings to set and validate. Signed-off-by: N=C3=ADcolas F. R. A. Prado --- tools/testing/selftests/gpio/Makefile | 2 +- .../gpio-set-get-config-example-test-plan.yaml | 15 ++ .../testing/selftests/gpio/gpio-set-get-config.py | 183 +++++++++++++++++= ++++ 3 files changed, 199 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/gpio/Makefile b/tools/testing/selftest= s/gpio/Makefile index e0884390447dcfffe4ca0b4fa0f1669463bb669c..bdfeb0c9aaddc436df77ada1d5a= c0c80890960a7 100644 --- a/tools/testing/selftests/gpio/Makefile +++ b/tools/testing/selftests/gpio/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 =20 -TEST_PROGS :=3D gpio-mockup.sh gpio-sim.sh +TEST_PROGS :=3D gpio-mockup.sh gpio-sim.sh gpio-set-get-config.py TEST_FILES :=3D gpio-mockup-sysfs.sh TEST_GEN_PROGS_EXTENDED :=3D gpio-mockup-cdev gpio-chip-info gpio-line-name CFLAGS +=3D -O2 -g -Wall $(KHDR_INCLUDES) diff --git a/tools/testing/selftests/gpio/gpio-set-get-config-example-test-= plan.yaml b/tools/testing/selftests/gpio/gpio-set-get-config-example-test-p= lan.yaml new file mode 100644 index 0000000000000000000000000000000000000000..3b749be3c8dcf6822b7531424a6= b1f8fca840a65 --- /dev/null +++ b/tools/testing/selftests/gpio/gpio-set-get-config-example-test-plan.ya= ml @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0 +# Top-level contains a list of the GPIO chips that will be tested. Each on= e is +# chosen based on the GPIO chip's info label. +- label: "gpiochip_device_label" + # For each GPIO chip, multiple pin configurations can be tested, which a= re + # listed under 'tests' + tests: + # pin indicates the pin number to test + - pin: 34 + # bias can be 'pull-up', 'pull-down', 'disabled' + bias: "pull-up" + - pin: 34 + bias: "pull-down" + - pin: 34 + bias: "disabled" diff --git a/tools/testing/selftests/gpio/gpio-set-get-config.py b/tools/te= sting/selftests/gpio/gpio-set-get-config.py new file mode 100755 index 0000000000000000000000000000000000000000..6f1444c8d46bcfc226f414520b7= 4f4a59725854f --- /dev/null +++ b/tools/testing/selftests/gpio/gpio-set-get-config.py @@ -0,0 +1,183 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: GPL-2.0 +# Copyright (c) 2024 Collabora Ltd + +# +# This test validates GPIO pin configuration. It takes a test plan in YAML= (see +# gpio-set-get-config-example-test-plan.yaml) and sets and gets back each = pin +# configuration described in the plan and checks that they match in order = to +# validate that they are being applied correctly. +# +# When the file name for the test plan is not provided through --test-plan= , it +# will be guessed based on the platform ID (DT compatible or DMI). +# + +import time +import os +import sys +import argparse +import re +import subprocess +import glob +import signal + +import yaml + +# Allow ksft module to be imported from different directory +this_dir =3D os.path.dirname(os.path.realpath(__file__)) +sys.path.append(os.path.join(this_dir, "../kselftest/")) + +import ksft + + +def config_pin(chip_dev, pin_config): + flags =3D [] + if pin_config.get("bias"): + flags +=3D f"-b {pin_config['bias']}".split() + flags +=3D ["-w", chip_dev, str(pin_config["pin"])] + gpio_mockup_cdev_path =3D os.path.join(this_dir, "gpio-mockup-cdev") + return subprocess.Popen([gpio_mockup_cdev_path] + flags) + + +def get_bias_debugfs(chip_debugfs_path, pin): + with open(os.path.join(chip_debugfs_path, "pinconf-pins")) as f: + for l in f: + m =3D re.match(rf"pin {pin}.*bias (?P(pull )?\w+)", l) + if m: + return m.group("bias") + + +def check_config_pin(chip, chip_debugfs_dir, pin_config): + test_passed =3D True + + if pin_config.get("bias"): + bias =3D get_bias_debugfs(chip_debugfs_dir, pin_config["pin"]) + # Convert "pull up" / "pull down" to "pull-up" / "pull-down" + bias =3D bias.replace(" ", "-") + if bias !=3D pin_config["bias"]: + ksft.print_msg( + f"Bias doesn't match: Expected {pin_config['bias']}, read = {bias}." + ) + test_passed =3D False + + ksft.test_result( + test_passed, + f"{chip['label']}.{pin_config['pin']}.{pin_config['bias']}", + ) + + +def get_devfs_chip_file(chip_dict): + gpio_chip_info_path =3D os.path.join(this_dir, 'gpio-chip-info') + for f in glob.glob("/dev/gpiochip*"): + proc =3D subprocess.run( + f"{gpio_chip_info_path} {f} label".split(), capture_output=3DT= rue, text=3DTrue + ) + if proc.returncode: + ksft.print_msg(f"Error opening gpio device {f}: {proc.returnco= de}") + ksft.exit_fail() + + if chip_dict["label"] in proc.stdout: + return f + + +def get_debugfs_chip_dir(chip): + pinctrl_debugfs =3D "/sys/kernel/debug/pinctrl/" + + for name in os.listdir(pinctrl_debugfs): + if chip["label"] in name: + return os.path.join(pinctrl_debugfs, name) + + +def run_test(test_plan_filename): + ksft.print_msg(f"Using test plan file: {test_plan_filename}") + + with open(test_plan_filename) as f: + plan =3D yaml.safe_load(f) + + num_tests =3D 0 + for chip in plan: + num_tests +=3D len(chip["tests"]) + + ksft.set_plan(num_tests) + + for chip in plan: + chip_dev =3D get_devfs_chip_file(chip) + if not chip_dev: + ksft.print_msg("Couldn't find /dev file for GPIO chip") + ksft.exit_fail() + chip_debugfs_dir =3D get_debugfs_chip_dir(chip) + if not chip_debugfs_dir: + ksft.print_msg("Couldn't find pinctrl folder in debugfs for GP= IO chip") + ksft.exit_fail() + for pin_config in chip["tests"]: + proc =3D config_pin(chip_dev, pin_config) + time.sleep(0.1) # Give driver some time to update pin + check_config_pin(chip, chip_debugfs_dir, pin_config) + proc.send_signal(signal.SIGTERM) + proc.wait() + + +def get_possible_test_plan_filenames(): + filenames =3D [] + + dt_board_compatible_file =3D "/proc/device-tree/compatible" + if os.path.exists(dt_board_compatible_file): + with open(dt_board_compatible_file) as f: + for line in f: + compatibles =3D [compat for compat in line.split("\0") if = compat] + filenames.extend(compatibles) + else: + dmi_id_dir =3D "/sys/devices/virtual/dmi/id" + vendor_dmi_file =3D os.path.join(dmi_id_dir, "sys_vendor") + product_dmi_file =3D os.path.join(dmi_id_dir, "product_name") + + with open(vendor_dmi_file) as f: + vendor =3D f.read().replace("\n", "") + with open(product_dmi_file) as f: + product =3D f.read().replace("\n", "") + + filenames =3D [vendor + "," + product] + + return filenames + + +def get_test_plan_filename(test_plan_dir): + chosen_test_plan_filename =3D "" + full_test_plan_paths =3D [ + os.path.join(test_plan_dir, f + ".yaml") + for f in get_possible_test_plan_filenames() + ] + for path in full_test_plan_paths: + if os.path.exists(path): + chosen_test_plan_filename =3D path + break + + if not chosen_test_plan_filename: + tried_paths =3D ",".join(["'" + p + "'" for p in full_test_plan_pa= ths]) + ksft.print_msg(f"No matching test plan file found (tried {tried_pa= ths})") + ksft.print_cnts() + sys.exit(4) + + return chosen_test_plan_filename + + +parser =3D argparse.ArgumentParser() +parser.add_argument( + "--test-plan-dir", default=3D".", help=3D"Directory containing the tes= t plan files" +) +parser.add_argument("--test-plan", help=3D"Test plan file to use") +args =3D parser.parse_args() + +ksft.print_header() + +if args.test_plan: + test_plan_filename =3D os.path.join(args.test_plan_dir, args.test_plan) + if not os.path.exists(test_plan_filename): + ksft.print_msg(f"Test plan file not found: {test_plan_filename}") + ksft.exit_fail() +else: + test_plan_filename =3D get_test_plan_filename(args.test_plan_dir) + +run_test(test_plan_filename) + +ksft.finished() --=20 2.47.0