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a=ed25519; pk=p3Bh4oPpeCrTpffJvGch5WsWNikteWHJ+4LBICPbZg0= Add the compatible for Samsung Mongoose M3 CPU core to the schema. Co-developed-by: Maksym Holovach Signed-off-by: Maksym Holovach Signed-off-by: Markuss Broks --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentatio= n/devicetree/bindings/arm/cpus.yaml index c54d20dd9d7efcbbfe73e5a63fd2f61d1e010d29..2fa7d3513da839ddfb2844628b1= 249567226a025 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -207,6 +207,7 @@ properties: - qcom,oryon - qcom,scorpion - samsung,mongoose-m2 + - samsung,mongoose-m3 - samsung,mongoose-m5 =20 enable-method: --=20 2.46.2 From nobody Mon Nov 25 17:34:15 2024 Received: from mail-lf1-f51.google.com (mail-lf1-f51.google.com [209.85.167.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE619201018; Fri, 25 Oct 2024 11:25:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 25 Oct 2024 04:25:11 -0700 (PDT) Received: from [192.168.1.105] ([178.136.36.129]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53b2e1c90c0sm144028e87.189.2024.10.25.04.25.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 04:25:11 -0700 (PDT) From: Markuss Broks Date: Fri, 25 Oct 2024 14:24:49 +0300 Subject: [PATCH v2 02/12] dt-bindings: hwinfo: samsung,exynos-chipid: Add Samsung exynos9810 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241025-exynos9810-v2-2-99ca3f316e21@gmail.com> References: <20241025-exynos9810-v2-0-99ca3f316e21@gmail.com> In-Reply-To: <20241025-exynos9810-v2-0-99ca3f316e21@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , Alim Akhtar , Sylwester Nawrocki , Linus Walleij , Tomasz Figa , Will Deacon , Mark Rutland Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Ivaylo Ivanov , Markuss Broks , Maksym Holovach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729855507; l=1083; i=markuss.broks@gmail.com; s=20241024; h=from:subject:message-id; bh=e0pUeZhnaxoOJxI70AFSXGBv66qAJ/ODZ80pJS01hrw=; b=sQmGok87n+es/tJA9th7JWqP4Nbe8occLtRJWndKkoWz1YPWdc5GUzrS6sxN43GcJj7SXodIq RLrVmYnnu5HA8KY70kpPWkTvJauKR56ZvAGF4ak34wFnAgZSirOtDrN X-Developer-Key: i=markuss.broks@gmail.com; a=ed25519; pk=p3Bh4oPpeCrTpffJvGch5WsWNikteWHJ+4LBICPbZg0= Add the compatible for Samsung Exynos9810 chipid to schema. Co-developed-by: Maksym Holovach Signed-off-by: Maksym Holovach Signed-off-by: Markuss Broks --- Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid= .yaml b/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml index 47a8d98346ebb83a7ea4d11e2fc7fc87df6bc5ad..385aac7161a0db9334a92d78a57= a125f23ca1920 100644 --- a/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml +++ b/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml @@ -24,6 +24,7 @@ properties: - enum: - samsung,exynos7885-chipid - samsung,exynos8895-chipid + - samsung,exynos9810-chipid - samsung,exynos990-chipid - samsung,exynosautov9-chipid - samsung,exynosautov920-chipid --=20 2.46.2 From nobody Mon Nov 25 17:34:15 2024 Received: from mail-lf1-f50.google.com (mail-lf1-f50.google.com [209.85.167.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5C1E2022EE; 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a=ed25519-sha256; t=1729855507; l=1041; i=markuss.broks@gmail.com; s=20241024; h=from:subject:message-id; bh=J11BKakW41EeIWO3xm1R87buOc94o8CAHWbow97U0+Y=; b=8Q9xi5rnFYrKFAl6oJ5fQ+KHXAWj47BsMmvGMPCB1rygrMfgVWqg5ms3ZfQ63+gekZHuUx7a0 6+3aVw+80HHCkghT86ZdZWoLr66AZEUcf6SAOm0EOT7l+QpFFlg4UMZ X-Developer-Key: i=markuss.broks@gmail.com; a=ed25519; pk=p3Bh4oPpeCrTpffJvGch5WsWNikteWHJ+4LBICPbZg0= Add a compatible for Samsung Exynos9810 pinctrl block to the schema. Co-developed-by: Maksym Holovach Signed-off-by: Maksym Holovach Signed-off-by: Markuss Broks --- Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml= b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index 7e6ef8249de6c2eeedfaab0ad6316af135c2ec31..5296a9e4faaec691994cd567bc3= 805f870aaebf8 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -54,6 +54,7 @@ properties: - samsung,exynos7885-pinctrl - samsung,exynos850-pinctrl - samsung,exynos8895-pinctrl + - samsung,exynos9810-pinctrl - samsung,exynos990-pinctrl - samsung,exynosautov9-pinctrl - samsung,exynosautov920-pinctrl --=20 2.46.2 From nobody Mon Nov 25 17:34:15 2024 Received: from mail-lf1-f50.google.com (mail-lf1-f50.google.com [209.85.167.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22DAA2036EC; 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Fri, 25 Oct 2024 04:25:13 -0700 (PDT) Received: from [192.168.1.105] ([178.136.36.129]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53b2e1c90c0sm144028e87.189.2024.10.25.04.25.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 04:25:13 -0700 (PDT) From: Markuss Broks Date: Fri, 25 Oct 2024 14:24:51 +0300 Subject: [PATCH v2 04/12] dt-bindings: pinctrl: samsung: Add compatible for exynos9810-wakeup-eint Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241025-exynos9810-v2-4-99ca3f316e21@gmail.com> References: <20241025-exynos9810-v2-0-99ca3f316e21@gmail.com> In-Reply-To: <20241025-exynos9810-v2-0-99ca3f316e21@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , Alim Akhtar , Sylwester Nawrocki , Linus Walleij , Tomasz Figa , Will Deacon , Mark Rutland Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Ivaylo Ivanov , Markuss Broks , Maksym Holovach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729855507; l=1142; i=markuss.broks@gmail.com; s=20241024; h=from:subject:message-id; bh=anfc4pv3kBFwMUC6+boo1nr/Fl+OcGuNSaeW1M8DaGc=; b=RN0biJqpKerXFY2hT9SMKUf1B954dfTnBJCZk//sc7T/EYhl/mogqBMxMnDQf63uuf6f+l4XM Z8JM17GPDkfD3Lk8H8da8XqD/ZpvNEoUoCSKFR3Oj8zbQJTEt94iY8M X-Developer-Key: i=markuss.broks@gmail.com; a=ed25519; pk=p3Bh4oPpeCrTpffJvGch5WsWNikteWHJ+4LBICPbZg0= Add the compatible for Samsung Exynos9810 pinctrl eint block to the schema. Co-developed-by: Maksym Holovach Signed-off-by: Maksym Holovach Signed-off-by: Markuss Broks --- .../devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml |= 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wake= up-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinct= rl-wakeup-interrupt.yaml index 565cacadb6be77b1be1a7423f88564dd950c44db..68ed714eb0a178c46228bac142d= 69bbd6baa6277 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-inte= rrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-inte= rrupt.yaml @@ -47,6 +47,7 @@ properties: - items: - enum: - google,gs101-wakeup-eint + - samsung,exynos9810-wakeup-eint - samsung,exynos990-wakeup-eint - samsung,exynosautov9-wakeup-eint - const: samsung,exynos850-wakeup-eint --=20 2.46.2 From nobody Mon Nov 25 17:34:15 2024 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 512D2204088; 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a=ed25519-sha256; t=1729855507; l=1024; i=markuss.broks@gmail.com; s=20241024; h=from:subject:message-id; bh=xkm6m1i7s0SD+Mojc2S/i0Db8Qi+817SjtThULB3wpo=; b=21f+huUrG9w9oknHmtiwK3XoY/Q6yrjyTsZrvrrSb7fEVgnOXWWtlAJUmguq/tyDNYfKUO/tm /V5LCY7q/7sDSLXDv18ab3ubQ3hTZNIN0YkuNT0LNXZLwe98t7KIA66 X-Developer-Key: i=markuss.broks@gmail.com; a=ed25519; pk=p3Bh4oPpeCrTpffJvGch5WsWNikteWHJ+4LBICPbZg0= Add compatible for Samsung Exynos9810 PMU to the schema. Co-developed-by: Maksym Holovach Signed-off-by: Maksym Holovach Signed-off-by: Markuss Broks --- Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml = b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index 5c4ba6c65e6926467ff0e90142ad62fbd0b9e1e8..6cdfe7e059a3556dfb872818f1b= 2649ab6b0e8af 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -54,6 +54,7 @@ properties: - enum: - samsung,exynos7885-pmu - samsung,exynos8895-pmu + - samsung,exynos9810-pmu - samsung,exynosautov9-pmu - samsung,exynosautov920-pmu - tesla,fsd-pmu --=20 2.46.2 From nobody Mon Nov 25 17:34:15 2024 Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E29B8204945; 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Fri, 25 Oct 2024 04:25:16 -0700 (PDT) Received: from [192.168.1.105] ([178.136.36.129]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53b2e1c90c0sm144028e87.189.2024.10.25.04.25.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 04:25:15 -0700 (PDT) From: Markuss Broks Date: Fri, 25 Oct 2024 14:24:53 +0300 Subject: [PATCH v2 06/12] dt-bindings: arm: samsung: Document Exynos9810 and starlte board binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241025-exynos9810-v2-6-99ca3f316e21@gmail.com> References: <20241025-exynos9810-v2-0-99ca3f316e21@gmail.com> In-Reply-To: <20241025-exynos9810-v2-0-99ca3f316e21@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , Alim Akhtar , Sylwester Nawrocki , Linus Walleij , Tomasz Figa , Will Deacon , Mark Rutland Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Ivaylo Ivanov , Markuss Broks , Maksym Holovach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729855507; l=1237; i=markuss.broks@gmail.com; s=20241024; h=from:subject:message-id; bh=wJq9r0ywpF+U/F21JjpDFPiTiDgeAY0OfPL9TFD6z20=; b=cyhMpCuNS6CZPtIHrXY+B7GQEuyo73CRXCgppXOZkGv53V0LbIPEuKjFHjz+ZgBBe79rktv82 7o4L1mpgke0DoGvU9FyMdZkq87oQp/FS13XBJwWkEgWimCwkxhatcvS X-Developer-Key: i=markuss.broks@gmail.com; a=ed25519; pk=p3Bh4oPpeCrTpffJvGch5WsWNikteWHJ+4LBICPbZg0= Add the compatibles for Exynos9810 SoC and samsung,starlte board to the list of boards. Co-developed-by: Maksym Holovach Signed-off-by: Maksym Holovach Signed-off-by: Markuss Broks --- Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml | 6 ++++= ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.y= aml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index d25a17e697256f8d868e24bea47d21accd1184ed..b5ba5ffc36d687a6fdbc625e6d9= 5c37a8a2e2b93 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -230,6 +230,12 @@ properties: - samsung,dreamlte # Samsung Galaxy S8 (SM-G9= 50F) - const: samsung,exynos8895 =20 + - description: Exynos9810 based boards + items: + - enum: + - samsung,starlte # Samsung Galaxy S9 (SM-G9= 60F) + - const: samsung,exynos9810 + - description: Exynos990 based boards items: - enum: --=20 2.46.2 From nobody Mon Nov 25 17:34:15 2024 Received: from mail-lj1-f176.google.com (mail-lj1-f176.google.com [209.85.208.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 250F1204F73; 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Fri, 25 Oct 2024 04:25:17 -0700 (PDT) Received: from [192.168.1.105] ([178.136.36.129]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53b2e1c90c0sm144028e87.189.2024.10.25.04.25.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 04:25:17 -0700 (PDT) From: Markuss Broks Date: Fri, 25 Oct 2024 14:24:54 +0300 Subject: [PATCH v2 07/12] dt-bindings: arm: pmu: Add Samsung Mongoose core compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241025-exynos9810-v2-7-99ca3f316e21@gmail.com> References: <20241025-exynos9810-v2-0-99ca3f316e21@gmail.com> In-Reply-To: <20241025-exynos9810-v2-0-99ca3f316e21@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , Alim Akhtar , Sylwester Nawrocki , Linus Walleij , Tomasz Figa , Will Deacon , Mark Rutland Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Ivaylo Ivanov , Markuss Broks , Maksym Holovach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729855507; l=909; i=markuss.broks@gmail.com; s=20241024; h=from:subject:message-id; bh=gIFcDF3Nn6a13khPJ7KdJaPJmVQk2lFc9U58rW96C90=; b=Xzf7ozUZ1q/1szWYfZVgSzhsL4JnYbG8DEq99qnIfLpVmOvmJOCvyh0nKtj1bvGBmRExXcn9E YF7V9B58yKTATw5eyOEgWrsP9PyqRpzj2XLIpfup9Co1vU0qKMFygZp X-Developer-Key: i=markuss.broks@gmail.com; a=ed25519; pk=p3Bh4oPpeCrTpffJvGch5WsWNikteWHJ+4LBICPbZg0= Add the compatible for the Samsung Mongoose CPU PMU to the schema. Co-developed-by: Maksym Holovach Signed-off-by: Maksym Holovach Signed-off-by: Markuss Broks --- Documentation/devicetree/bindings/arm/pmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation= /devicetree/bindings/arm/pmu.yaml index 528544d0a1614c9f9bddaafa8dac4782d09ac7e9..a148ff54f2b8a92fa3fcfa78c1b= cc525dba1c6dd 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -74,6 +74,7 @@ properties: - qcom,krait-pmu - qcom,scorpion-pmu - qcom,scorpion-mp-pmu + - samsung,mongoose-pmu =20 interrupts: # Don't know how many CPUs, so no constraints to specify --=20 2.46.2 From nobody Mon Nov 25 17:34:15 2024 Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE3AF205158; Fri, 25 Oct 2024 11:25:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 25 Oct 2024 04:25:18 -0700 (PDT) Received: from [192.168.1.105] ([178.136.36.129]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53b2e1c90c0sm144028e87.189.2024.10.25.04.25.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 04:25:18 -0700 (PDT) From: Markuss Broks Date: Fri, 25 Oct 2024 14:24:55 +0300 Subject: [PATCH v2 08/12] perf: arm_pmuv3: Add support for Samsung Mongoose PMU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241025-exynos9810-v2-8-99ca3f316e21@gmail.com> References: <20241025-exynos9810-v2-0-99ca3f316e21@gmail.com> In-Reply-To: <20241025-exynos9810-v2-0-99ca3f316e21@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , Alim Akhtar , Sylwester Nawrocki , Linus Walleij , Tomasz Figa , Will Deacon , Mark Rutland Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Ivaylo Ivanov , Markuss Broks , Maksym Holovach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729855507; l=1401; i=markuss.broks@gmail.com; s=20241024; h=from:subject:message-id; bh=kyHAPTKZB5mT8XCJ0jyUMcgti7f6+k1RLiIUUCWE+Oc=; b=e18R1gAgBqNCItvEqiHWKV4mMiyFfaoPBdnl6l/utulFdQNuLswqV9JWRXelc4wgJJy11VQSs f8bgmqNff5wCYbqLk4IMUwUWHV5LEY26+RM8aVSOfPfuRr4WzerOxji X-Developer-Key: i=markuss.broks@gmail.com; a=ed25519; pk=p3Bh4oPpeCrTpffJvGch5WsWNikteWHJ+4LBICPbZg0= Add support for the Samsung Mongoose CPU core PMU. This just adds the names and links to DT compatible strings. Co-developed-by: Maksym Holovach Signed-off-by: Maksym Holovach Signed-off-by: Markuss Broks --- drivers/perf/arm_pmuv3.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index 0afe02f879b45a8600b9cea1bfd88e6a68096a67..9eb5603e1dda18c4bdd27453047= 37932a27fde8a 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -1364,6 +1364,8 @@ PMUV3_INIT_SIMPLE(armv8_neoverse_v3ae) PMUV3_INIT_SIMPLE(armv8_nvidia_carmel) PMUV3_INIT_SIMPLE(armv8_nvidia_denver) =20 +PMUV3_INIT_SIMPLE(armv8_samsung_mongoose) + PMUV3_INIT_MAP_EVENT(armv8_cortex_a35, armv8_a53_map_event) PMUV3_INIT_MAP_EVENT(armv8_cortex_a53, armv8_a53_map_event) PMUV3_INIT_MAP_EVENT(armv8_cortex_a57, armv8_a57_map_event) @@ -1409,6 +1411,7 @@ static const struct of_device_id armv8_pmu_of_device_= ids[] =3D { {.compatible =3D "brcm,vulcan-pmu", .data =3D armv8_brcm_vulcan_pmu_init}, {.compatible =3D "nvidia,carmel-pmu", .data =3D armv8_nvidia_carmel_pmu_i= nit}, {.compatible =3D "nvidia,denver-pmu", .data =3D armv8_nvidia_denver_pmu_i= nit}, + {.compatible =3D "samsung,mongoose-pmu", .data =3D armv8_samsung_mongoose= _pmu_init}, {}, }; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241025-exynos9810-v2-9-99ca3f316e21@gmail.com> References: <20241025-exynos9810-v2-0-99ca3f316e21@gmail.com> In-Reply-To: <20241025-exynos9810-v2-0-99ca3f316e21@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , Alim Akhtar , Sylwester Nawrocki , Linus Walleij , Tomasz Figa , Will Deacon , Mark Rutland Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Ivaylo Ivanov , Markuss Broks , Maksym Holovach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729855507; l=940; i=markuss.broks@gmail.com; s=20241024; h=from:subject:message-id; bh=QjtBasZbvA/8f0B/+aABkLP1VAZE3+DKqz2/AET0FRk=; b=ncmttaClZaIRfTZtg4vfNFS4I8cwBDlN9bWFjIpjluY4rymx8V7ECfUz67WUr9/Wk7q4dA/Hl wDMrvBxTz+WDmuoHj1pcX0qkbNTmPwPpgwDYR9cAQIavC8rvf6+2B4l X-Developer-Key: i=markuss.broks@gmail.com; a=ed25519; pk=p3Bh4oPpeCrTpffJvGch5WsWNikteWHJ+4LBICPbZg0= Exynos 9810 has the product ID of "0xE9810000". Add this ID to the IDs together with the name of the SoC. Co-developed-by: Maksym Holovach Signed-off-by: Maksym Holovach Signed-off-by: Markuss Broks --- drivers/soc/samsung/exynos-chipid.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exyn= os-chipid.c index 94c7cc0d11e4c6f151336dc6e25495a31cbec02d..23cc20896b85a2da02f36703225= a4f62e7538a62 100644 --- a/drivers/soc/samsung/exynos-chipid.c +++ b/drivers/soc/samsung/exynos-chipid.c @@ -59,6 +59,7 @@ static const struct exynos_soc_id { { "EXYNOS7885", 0xE7885000 }, { "EXYNOS850", 0xE3830000 }, { "EXYNOS8895", 0xE8895000 }, + { "EXYNOS9810", 0xE9810000 }, { "EXYNOS990", 0xE9830000 }, { "EXYNOSAUTOV9", 0xAAA80000 }, { "EXYNOSAUTOV920", 0x0A920000 }, --=20 2.46.2 From nobody Mon Nov 25 17:34:15 2024 Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26E9020604B; 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Fri, 25 Oct 2024 04:25:21 -0700 (PDT) Received: from [192.168.1.105] ([178.136.36.129]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53b2e1c90c0sm144028e87.189.2024.10.25.04.25.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 04:25:21 -0700 (PDT) From: Markuss Broks Date: Fri, 25 Oct 2024 14:24:57 +0300 Subject: [PATCH v2 10/12] pinctrl: samsung: Add Exynos9810 SoC specific data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241025-exynos9810-v2-10-99ca3f316e21@gmail.com> References: <20241025-exynos9810-v2-0-99ca3f316e21@gmail.com> In-Reply-To: <20241025-exynos9810-v2-0-99ca3f316e21@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , Alim Akhtar , Sylwester Nawrocki , Linus Walleij , Tomasz Figa , Will Deacon , Mark Rutland Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Ivaylo Ivanov , Markuss Broks , Maksym Holovach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729855507; l=9501; i=markuss.broks@gmail.com; s=20241024; h=from:subject:message-id; bh=zCK6xRgCZy+aKLIxLIRPz3zizHsPoXeVWBzInpPZLhg=; b=MB/JUSXZ0nO699uTxQYOiHGh8dMGUv1etUbsrO9qmWZmVT9zg47XSRO8lWIjd6JBbjyrHKr0i p9gfkq8PRDjA0O663uOYlaabWjTBHc/yMkU0bWqAdbRGeA+yBWtoUw4 X-Developer-Key: i=markuss.broks@gmail.com; a=ed25519; pk=p3Bh4oPpeCrTpffJvGch5WsWNikteWHJ+4LBICPbZg0= Add Samsung Exynos9810 SoC specific data to enable pinctrl support for platforms based on Exynos9810. Co-developed-by: Maksym Holovach Signed-off-by: Maksym Holovach Signed-off-by: Markuss Broks --- drivers/pinctrl/samsung/pinctrl-exynos-arm64.c | 154 +++++++++++++++++++++= ++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 3 files changed, 157 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinct= rl/samsung/pinctrl-exynos-arm64.c index f07c26d374425505019447161150929f7677f91d..3ea7106ce5eae3c21f11790b5a4= 0037042c1d407 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -767,6 +767,160 @@ const struct samsung_pinctrl_of_match_data exynos990_= of_data __initconst =3D { .num_ctrl =3D ARRAY_SIZE(exynos990_pin_ctrl), }; =20 +/* pin banks of exynos9810 pin-controller 0 (ALIVE) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks0[] __initco= nst =3D { + EXYNOS850_PIN_BANK_EINTN(6, 0x000, "etc1"), + EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00), + EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04), + EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08), + EXYNOS850_PIN_BANK_EINTW(8, 0x080, "gpa3", 0x0c), + EXYNOS850_PIN_BANK_EINTN(6, 0x0A0, "gpq0"), + EXYNOS850_PIN_BANK_EINTW(2, 0x0C0, "gpa4", 0x10), +}; + +/* pin banks of exynos9810 pin-controller 1 (AUD) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks1[] __initco= nst =3D { + EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpb1", 0x04), + EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpb2", 0x08), +}; + +/* pin banks of exynos9810 pin-controller 2 (CHUB) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks2[] __initco= nst =3D { + EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gph0", 0x00), + EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gph1", 0x04), +}; + +/* pin banks of exynos9810 pin-controller 3 (CMGP) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks3[] __initco= nst =3D { + EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), + EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), + EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), + EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C), + EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), + EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14), + EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18), + EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C), + EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm10", 0x20), + EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm11", 0x24), + EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm12", 0x28), + EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm13", 0x2C), + EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm14", 0x30), + EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm15", 0x34), + EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm16", 0x38), + EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm17", 0x3C), + EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm40", 0x40), + EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm41", 0x44), + EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm42", 0x48), + EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm43", 0x4C), +}; + +/* pin banks of exynos9810 pin-controller 4 (FSYS0) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks4[] __initco= nst =3D { + EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpf0", 0x00), +}; + +/* pin banks of exynos9810 pin-controller 5 (FSYS1) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks5[] __initco= nst =3D { + EXYNOS850_PIN_BANK_EINTG(7, 0x000, "gpf1", 0x00), + EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf2", 0x04), +}; + +/* pin banks of exynos9810 pin-controller 6 (PERIC0) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks6[] __initco= nst =3D { + EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04), + EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), + EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp3", 0x0C), + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), + EXYNOS850_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), + EXYNOS850_PIN_BANK_EINTG(8, 0x0C0, "gpg2", 0x18), +}; + +/* pin banks of exynos9810 pin-controller 7 (PERIC1) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks7[] __initco= nst =3D { + EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp4", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp5", 0x04), + EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp6", 0x08), + EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpc0", 0x0C), + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpc1", 0x10), + EXYNOS850_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), + EXYNOS850_PIN_BANK_EINTG(7, 0x0C0, "gpg3", 0x18), +}; + +/* pin banks of exynos9810 pin-controller 8 (VTS) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks8[] __initco= nst =3D { + EXYNOS850_PIN_BANK_EINTG(3, 0x000, "gpt0", 0x00), +}; + +static const struct samsung_pin_ctrl exynos9810_pin_ctrl[] __initconst =3D= { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks =3D exynos9810_pin_banks0, + .nr_banks =3D ARRAY_SIZE(exynos9810_pin_banks0), + .eint_wkup_init =3D exynos_eint_wkup_init, + .eint_gpio_init =3D exynos_eint_gpio_init, + .suspend =3D exynos_pinctrl_suspend, + .resume =3D exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 AUD data */ + .pin_banks =3D exynos9810_pin_banks1, + .nr_banks =3D ARRAY_SIZE(exynos9810_pin_banks1), + }, { + /* pin-controller instance 2 CHUB data */ + .pin_banks =3D exynos9810_pin_banks2, + .nr_banks =3D ARRAY_SIZE(exynos9810_pin_banks2), + .eint_gpio_init =3D exynos_eint_gpio_init, + .suspend =3D exynos_pinctrl_suspend, + .resume =3D exynos_pinctrl_resume, + }, { + /* pin-controller instance 3 CMGP data */ + .pin_banks =3D exynos9810_pin_banks3, + .nr_banks =3D ARRAY_SIZE(exynos9810_pin_banks3), + .eint_wkup_init =3D exynos_eint_wkup_init, + .eint_gpio_init =3D exynos_eint_gpio_init, + .suspend =3D exynos_pinctrl_suspend, + .resume =3D exynos_pinctrl_resume, + }, { + /* pin-controller instance 4 FSYS0 data */ + .pin_banks =3D exynos9810_pin_banks4, + .nr_banks =3D ARRAY_SIZE(exynos9810_pin_banks4), + .eint_gpio_init =3D exynos_eint_gpio_init, + .suspend =3D exynos_pinctrl_suspend, + .resume =3D exynos_pinctrl_resume, + }, { + /* pin-controller instance 5 FSYS1 data */ + .pin_banks =3D exynos9810_pin_banks5, + .nr_banks =3D ARRAY_SIZE(exynos9810_pin_banks5), + .eint_gpio_init =3D exynos_eint_gpio_init, + .suspend =3D exynos_pinctrl_suspend, + .resume =3D exynos_pinctrl_resume, + }, { + /* pin-controller instance 6 PERIC0 data */ + .pin_banks =3D exynos9810_pin_banks6, + .nr_banks =3D ARRAY_SIZE(exynos9810_pin_banks6), + .eint_gpio_init =3D exynos_eint_gpio_init, + .suspend =3D exynos_pinctrl_suspend, + .resume =3D exynos_pinctrl_resume, + }, { + /* pin-controller instance 7 PERIC1 data */ + .pin_banks =3D exynos9810_pin_banks7, + .nr_banks =3D ARRAY_SIZE(exynos9810_pin_banks7), + .eint_gpio_init =3D exynos_eint_gpio_init, + .suspend =3D exynos_pinctrl_suspend, + .resume =3D exynos_pinctrl_resume, + }, { + /* pin-controller instance 8 VTS data */ + .pin_banks =3D exynos9810_pin_banks8, + .nr_banks =3D ARRAY_SIZE(exynos9810_pin_banks8), + }, +}; + +const struct samsung_pinctrl_of_match_data exynos9810_of_data __initconst = =3D { + .ctrl =3D exynos9810_pin_ctrl, + .num_ctrl =3D ARRAY_SIZE(exynos9810_pin_ctrl), +}; + /* pin banks of exynosautov9 pin-controller 0 (ALIVE) */ static const struct samsung_pin_bank_data exynosautov9_pin_banks0[] __init= const =3D { EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/sa= msung/pinctrl-samsung.c index 42e40860841bcc94e3c11bf313df792da10ab00b..bbedd980ec67234aad847b757f4= 0af5002b11ebb 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1479,6 +1479,8 @@ static const struct of_device_id samsung_pinctrl_dt_m= atch[] =3D { .data =3D &exynos850_of_data }, { .compatible =3D "samsung,exynos8895-pinctrl", .data =3D &exynos8895_of_data }, + { .compatible =3D "samsung,exynos9810-pinctrl", + .data =3D &exynos9810_of_data }, { .compatible =3D "samsung,exynos990-pinctrl", .data =3D &exynos990_of_data }, { .compatible =3D "samsung,exynosautov9-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/sa= msung/pinctrl-samsung.h index 615048f945243d4173d40142f1e62c8aeefe5b7e..bb0689d52ea0b4392714fa9bcdc= bae8d253c73a1 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -385,6 +385,7 @@ extern const struct samsung_pinctrl_of_match_data exyno= s7_of_data; extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; extern const struct samsung_pinctrl_of_match_data exynos850_of_data; extern const struct samsung_pinctrl_of_match_data exynos8895_of_data; +extern const struct samsung_pinctrl_of_match_data exynos9810_of_data; extern const struct samsung_pinctrl_of_match_data exynos990_of_data; extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data; extern const struct samsung_pinctrl_of_match_data exynosautov920_of_data; --=20 2.46.2 From nobody Mon Nov 25 17:34:15 2024 Received: from mail-lf1-f51.google.com (mail-lf1-f51.google.com [209.85.167.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 731DC206073; Fri, 25 Oct 2024 11:25:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729855528; 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Fri, 25 Oct 2024 04:25:23 -0700 (PDT) Received: from [192.168.1.105] ([178.136.36.129]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53b2e1c90c0sm144028e87.189.2024.10.25.04.25.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 04:25:22 -0700 (PDT) From: Markuss Broks Date: Fri, 25 Oct 2024 14:24:58 +0300 Subject: [PATCH v2 11/12] arm64: dts: exynos: Add Exynos9810 SoC support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241025-exynos9810-v2-11-99ca3f316e21@gmail.com> References: <20241025-exynos9810-v2-0-99ca3f316e21@gmail.com> In-Reply-To: <20241025-exynos9810-v2-0-99ca3f316e21@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , Alim Akhtar , Sylwester Nawrocki , Linus Walleij , Tomasz Figa , Will Deacon , Mark Rutland Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Ivaylo Ivanov , Markuss Broks , Maksym Holovach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729855507; l=18125; i=markuss.broks@gmail.com; s=20241024; h=from:subject:message-id; bh=8jaXELqqI2uL/GuJBTZRyco5s9LQkHvdYgQ7ucsw0Rg=; b=Q0lyyr6dzxnfRSwvqOjMkz7Kv7kV3+Mm+KbYucHhf7zgp+ls9DdzAtjJABc2rDfIEXHog5L5o F+O/cv4mmm9DQyzKYlt2bG2ZT1n+NvKDxwF/Ba453Dm5BQwZz3cHC2I X-Developer-Key: i=markuss.broks@gmail.com; a=ed25519; pk=p3Bh4oPpeCrTpffJvGch5WsWNikteWHJ+4LBICPbZg0= Exynos 9810 is an ARMv8 mobile SoC found in various Samsung devices, such as Samsung Galaxy S9 (starlte), S9 Plus (star2lte), Note 9 (crownlte) and perhaps others. Add minimal support for this SoC, including basic stuff like: - PSCI for bringing up secondary cores - ARMv8 generic timer - GPIO and pinctrl. The firmware coming with the devices based on this SoC is buggy and doesn't configure CNTFRQ_EL0, as required by spec, so it's needed to hardcode the frequency in the timer node. Co-developed-by: Maksym Holovach Signed-off-by: Maksym Holovach Signed-off-by: Markuss Broks --- arch/arm64/boot/dts/exynos/exynos9810-pinctrl.dtsi | 503 +++++++++++++++++= ++++ arch/arm64/boot/dts/exynos/exynos9810.dtsi | 273 +++++++++++ 2 files changed, 776 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos9810-pinctrl.dtsi b/arch/arm6= 4/boot/dts/exynos/exynos9810-pinctrl.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..88091bf09e4e91b05801cafe956= 283984d564449 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos9810-pinctrl.dtsi @@ -0,0 +1,503 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Samsung's Exynos 9810 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2024 Markuss Broks + * Copyright (c) 2024 Maksym Holovach + */ + +#include "exynos-pinctrl.h" + +&pinctrl_alive { + etc1: etc1-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + , + , + , + , + ; + #interrupt-cells =3D <2>; + }; + + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + , + , + , + , + ; + #interrupt-cells =3D <2>; + }; + + gpa2: gpa2-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + , + , + , + , + ; + #interrupt-cells =3D <2>; + }; + + gpa3: gpa3-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + , + , + , + , + ; + #interrupt-cells =3D <2>; + }; + + gpa4: gpa4-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpq0: gpq0-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; +}; + +&pinctrl_aud { + gpb0: gpb0-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpb1: gpb1-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpb2: gpb2-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; +}; + +&pinctrl_chub { + gph0: gph0-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gph1: gph1-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; +}; + +&pinctrl_cmgp { + gpm0: gpm0-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + interrupts =3D ; + }; + + gpm1: gpm1-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + interrupts =3D ; + }; + + gpm2: gpm2-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + interrupts =3D ; + }; + + gpm3: gpm3-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + interrupts =3D ; + }; + + gpm4: gpm4-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + interrupts =3D ; + }; + + gpm5: gpm5-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + interrupts =3D ; + }; + + gpm6: gpm6-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + interrupts =3D ; + }; + + gpm7: gpm7-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + interrupts =3D ; + }; + + gpm10: gpm10-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + interrupts =3D ; + }; + + gpm11: gpm11-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + interrupts =3D ; + }; + + gpm12: gpm12-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + interrupts =3D ; + }; + + gpm13: gpm13-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + interrupts =3D ; + }; + + gpm14: gpm14-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + interrupts =3D ; + }; + + gpm15: gpm15-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + interrupts =3D ; + }; + + gpm16: gpm16-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + interrupts =3D ; + }; + + gpm17: gpm17-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + interrupts =3D ; + }; + + gpm40: gpm40-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + interrupts =3D ; + }; + + gpm41: gpm41-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + interrupts =3D ; + }; + + gpm42: gpm42-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + interrupts =3D ; + }; + + gpm43: gpm43-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + interrupts =3D ; + }; +}; + +&pinctrl_fsys0 { + gpf0: gpf0-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; +}; + +&pinctrl_fsys1 { + gpf1: gpf1-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpf2: gpf2-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; +}; + +&pinctrl_peric0 { + gpg0: gpg0-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpg1: gpg1-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpg2: gpg2-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpp0: gpp0-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpp1: gpp1-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpp2: gpp2-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpp3: gpp3-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; +}; + +&pinctrl_peric1 { + gpc0: gpc0-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpc1: gpc1-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpd0: gpd0-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpg3: gpg3-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpp4: gpp4-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpp5: gpp5-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpp6: gpp6-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; +}; + +&pinctrl_vts { + gpt0: gpt0-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos9810.dtsi b/arch/arm64/boot/d= ts/exynos/exynos9810.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..a65c3dea4e3384faee943479935= 4d9485a60cea6 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos9810.dtsi @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Samsung Exynos 9810 SoC device tree source + * + * Copyright (c) 2024 Markuss Broks + * Copyright (c) 2024 Maksym Holovach + */ + +#include + +/ { + compatible =3D "samsung,exynos9810"; + #address-cells =3D <2>; + #size-cells =3D <1>; + + interrupt-parent =3D <&gic>; + + aliases { + pinctrl0 =3D &pinctrl_alive; + pinctrl1 =3D &pinctrl_aud; + pinctrl2 =3D &pinctrl_chub; + pinctrl3 =3D &pinctrl_cmgp; + pinctrl4 =3D &pinctrl_fsys0; + pinctrl5 =3D &pinctrl_fsys1; + pinctrl6 =3D &pinctrl_peric0; + pinctrl7 =3D &pinctrl_peric1; + pinctrl8 =3D &pinctrl_vts; + }; + + arm-a55-pmu { + compatible =3D "arm,cortex-a55-pmu"; + interrupts =3D , + , + , + ; + interrupt-affinity =3D <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; + + mongoose-m3-pmu { + compatible =3D "samsung,mongoose-pmu"; + interrupts =3D , + , + , + ; + interrupt-affinity =3D <&cpu4>, + <&cpu5>, + <&cpu6>, + <&cpu7>; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + core1 { + cpu =3D <&cpu1>; + }; + core2 { + cpu =3D <&cpu2>; + }; + core3 { + cpu =3D <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu4>; + }; + core1 { + cpu =3D <&cpu5>; + }; + core2 { + cpu =3D <&cpu6>; + }; + core3 { + cpu =3D <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0>; + enable-method =3D "psci"; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x1>; + enable-method =3D "psci"; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x2>; + enable-method =3D "psci"; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x3>; + enable-method =3D "psci"; + }; + + cpu4: cpu@100 { + device_type =3D "cpu"; + compatible =3D "samsung,mongoose-m3"; + reg =3D <0x100>; + enable-method =3D "psci"; + }; + + cpu5: cpu@101 { + device_type =3D "cpu"; + compatible =3D "samsung,mongoose-m3"; + reg =3D <0x101>; + enable-method =3D "psci"; + }; + + cpu6: cpu@102 { + device_type =3D "cpu"; + compatible =3D "samsung,mongoose-m3"; + reg =3D <0x102>; + enable-method =3D "psci"; + }; + + cpu7: cpu@103 { + device_type =3D "cpu"; + compatible =3D "samsung,mongoose-m3"; + reg =3D <0x103>; + enable-method =3D "psci"; + }; + }; + + oscclk: osc-clock { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-output-names =3D "oscclk"; + }; + + psci { + compatible =3D "arm,psci"; + method =3D "smc"; + cpu_off =3D <0x84000002>; + cpu_on =3D <0xc4000003>; + cpu_suspend =3D <0xc4000001>; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + ranges =3D <0x0 0x0 0x0 0x20000000>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + chipid@10000000 { + compatible =3D "samsung,exynos9810-chipid", + "samsung,exynos850-chipid"; + reg =3D <0x10000000 0x100>; + }; + + gic: interrupt-controller@10101000 { + compatible =3D "arm,gic-400"; + reg =3D <0x10101000 0x1000>, + <0x10102000 0x1000>, + <0x10104000 0x2000>, + <0x10106000 0x2000>; + #interrupt-cells =3D <3>; + interrupt-controller; + interrupts =3D ; + #address-cells =3D <0>; + #size-cells =3D <1>; + }; + + pinctrl_peric0: pinctrl@10430000 { + compatible =3D "samsung,exynos9810-pinctrl"; + reg =3D <0x10430000 0x1000>; + interrupts =3D ; + }; + + pinctrl_peric1: pinctrl@10830000 { + compatible =3D "samsung,exynos9810-pinctrl"; + reg =3D <0x10830000 0x1000>; + interrupts =3D ; + }; + + pinctrl_fsys0: pinctrl@11050000 { + compatible =3D "samsung,exynos9810-pinctrl"; + reg =3D <0x11050000 0x1000>; + interrupts =3D ; + }; + + pinctrl_fsys1: pinctrl@11430000 { + compatible =3D "samsung,exynos9810-pinctrl"; + reg =3D <0x11430000 0x1000>; + interrupts =3D ; + }; + + pinctrl_vts: pinctrl@13880000 { + compatible =3D "samsung,exynos9810-pinctrl"; + reg =3D <0x13880000 0x1000>; + }; + + pinctrl_chub: pinctrl@13a80000 { + compatible =3D "samsung,exynos9810-pinctrl"; + reg =3D <0x13a80000 0x1000>; + interrupts =3D ; + }; + + pinctrl_alive: pinctrl@14050000 { + compatible =3D "samsung,exynos9810-pinctrl"; + reg =3D <0x14050000 0x1000>; + + wakeup-interrupt-controller { + compatible =3D "samsung,exynos9810-wakeup-eint", + "samsung,exynos850-wakeup-eint", + "samsung,exynos7-wakeup-eint"; + }; + }; + + pmu_system_controller: system-controller@14060000 { + compatible =3D "samsung,exynos9810-pmu", + "samsung,exynos7-pmu", "syscon"; + reg =3D <0x14060000 0x10000>; + }; + + pinctrl_cmgp: pinctrl@14220000 { + compatible =3D "samsung,exynos9810-pinctrl"; + reg =3D <0x14220000 0x1000>; + + wakeup-interrupt-controller { + compatible =3D "samsung,exynos9810-wakeup-eint", + "samsung,exynos850-wakeup-eint", + "samsung,exynos7-wakeup-eint"; + }; + }; + + pinctrl_aud: pinctrl@17c60000 { + compatible =3D "samsung,exynos9810-pinctrl"; + reg =3D <0x17c60000 0x1000>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + /* Hypervisor Virtual Timer interrupt is not wired to GIC */ + interrupts =3D , + , + , + ; + /* + * Non-updatable, broken stock Samsung bootloader does not + * configure CNTFRQ_EL0 + */ + clock-frequency =3D <26000000>; + }; +}; + +#include "exynos9810-pinctrl.dtsi" +#include "arm/samsung/exynos-syscon-restart.dtsi" --=20 2.46.2 From nobody Mon Nov 25 17:34:15 2024 Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A59F20696B; Fri, 25 Oct 2024 11:25:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729855530; 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Fri, 25 Oct 2024 04:25:24 -0700 (PDT) Received: from [192.168.1.105] ([178.136.36.129]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53b2e1c90c0sm144028e87.189.2024.10.25.04.25.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 04:25:24 -0700 (PDT) From: Markuss Broks Date: Fri, 25 Oct 2024 14:24:59 +0300 Subject: [PATCH v2 12/12] arm64: dts: exynos: Add initial support for Samsung Galaxy S9 (SM-G960F) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241025-exynos9810-v2-12-99ca3f316e21@gmail.com> References: <20241025-exynos9810-v2-0-99ca3f316e21@gmail.com> In-Reply-To: <20241025-exynos9810-v2-0-99ca3f316e21@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , Alim Akhtar , Sylwester Nawrocki , Linus Walleij , Tomasz Figa , Will Deacon , Mark Rutland Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Ivaylo Ivanov , Markuss Broks , Maksym Holovach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729855507; l=4454; i=markuss.broks@gmail.com; s=20241024; h=from:subject:message-id; bh=s5ze8wIRUmpoQbq7xRWQ3Ftw43Pf29yleNflcPuixmI=; b=zquLveixYcDZM65pnmqteghKUpfXW7iKb56bo7wzynWSET/vQ7cgnlbQAKU5YeCDAjAoxWaW4 VONlaLYWwBvD4OC0JTOVHO2yutFnIaAcArpqiW1t/Q65zwXQuylnf1j X-Developer-Key: i=markuss.broks@gmail.com; a=ed25519; pk=p3Bh4oPpeCrTpffJvGch5WsWNikteWHJ+4LBICPbZg0= Samsung Galaxy S9 (SM-G960F), codenamed starlte, is a mobile phone released in 2017. It has 4GB of RAM, 64GB of UFS storage, Exynos9810 SoC and 1440x2960 Super AMOLED display. This initial device tree enables the framebuffer pre-initialised by bootloader and physical buttons of the device, with more support to come in the future. Co-developed-by: Maksym Holovach Signed-off-by: Maksym Holovach Signed-off-by: Markuss Broks --- arch/arm64/boot/dts/exynos/Makefile | 1 + arch/arm64/boot/dts/exynos/exynos9810-starlte.dts | 120 ++++++++++++++++++= ++++ 2 files changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exyn= os/Makefile index 7a934499b235892eef38cd926905e02f0ce08278..6760b3d59e819fb52bc8cf4dc68= 77a0b9db9ce47 100644 --- a/arch/arm64/boot/dts/exynos/Makefile +++ b/arch/arm64/boot/dts/exynos/Makefile @@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) +=3D \ exynos7885-jackpotlte.dtb \ exynos850-e850-96.dtb \ exynos8895-dreamlte.dtb \ + exynos9810-starlte.dtb \ exynos990-c1s.dtb \ exynosautov9-sadk.dtb \ exynosautov920-sadk.dtb diff --git a/arch/arm64/boot/dts/exynos/exynos9810-starlte.dts b/arch/arm64= /boot/dts/exynos/exynos9810-starlte.dts new file mode 100644 index 0000000000000000000000000000000000000000..7e01118e591284267f155883c23= 6ed811d5c629a --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos9810-starlte.dts @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Samsung Galaxy S9 (starlte/SM-G960F) device tree source + * + * Copyright (c) 2024 Markuss Broks + * Copyright (c) 2024 Maksym Holovach + */ + +/dts-v1/; +#include "exynos9810.dtsi" +#include +#include + +/ { + model =3D "Samsung Galaxy S9 (SM-G960F)"; + compatible =3D "samsung,starlte", "samsung,exynos9810"; + chassis-type =3D "handset"; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <1>; + ranges; + + framebuffer@cc000000 { + compatible =3D "simple-framebuffer"; + reg =3D <0x0 0xcc000000 (1440 * 2960 * 4)>; + width =3D <1440>; + height =3D <2960>; + stride =3D <(1440 * 4)>; + format =3D "a8r8g8b8"; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&key_power &key_voldown &key_volup &key_wink>; + pinctrl-names =3D "default"; + + power-key { + label =3D "Power"; + linux,code =3D ; + gpios =3D <&gpa2 4 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + voldown-key { + label =3D "Volume Down"; + linux,code =3D ; + gpios =3D <&gpa0 4 GPIO_ACTIVE_LOW>; + }; + + volup-key { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&gpa0 3 GPIO_ACTIVE_LOW>; + }; + + /* In stock firmware used for assistant. Map it as a camera button for n= ow */ + wink-key { + label =3D "Camera"; + linux,code =3D ; + gpios =3D <&gpa0 6 GPIO_ACTIVE_LOW>; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x3c800000>, + <0x8 0x80000000 0x80000000>, + <0x0 0xc0000000 0x20000000>, + <0x0 0xe1900000 0x1e700000>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <1>; + ranges; + + framebuffer@cc000000 { + reg =3D <0x0 0xcc000000 (1440 * 2960 * 4)>; + no-map; + }; + }; +}; + +&oscclk { + clock-frequency =3D <26000000>; +}; + +&pinctrl_alive { + key_power: key-power-pins { + samsung,pins =3D "gpa2-4"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + key_voldown: key-voldown-pins { + samsung,pins =3D "gpa0-4"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + key_volup: key-volup-pins { + samsung,pins =3D "gpa0-3"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + + key_wink: key-wink-pins { + samsung,pins =3D "gpa0-6"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; +}; --=20 2.46.2