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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241025-drm-vc4-2712-support-v2-35-35efa83c8fc0@raspberrypi.com> References: <20241025-drm-vc4-2712-support-v2-0-35efa83c8fc0@raspberrypi.com> In-Reply-To: <20241025-drm-vc4-2712-support-v2-0-35efa83c8fc0@raspberrypi.com> To: Maxime Ripard , =?utf-8?q?Ma=C3=ADra_Canal?= , Raspberry Pi Kernel Maintenance , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Ray Jui , Scott Branden , Michael Turquette , Stephen Boyd , Javier Martinez Canillas , Catalin Marinas , Will Deacon Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Dave Stevenson X-Mailer: b4 0.14.1 Adds the HVS and associated hardware blocks to support the HDMI and writeback connectors on BCM2712 / Pi5. Signed-off-by: Dave Stevenson --- arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts | 14 ++ arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 188 +++++++++++++++++++= ++++ 2 files changed, 202 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/= boot/dts/broadcom/bcm2712-rpi-5-b.dts index 92a2ada037f3..fbc56309660f 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts @@ -88,5 +88,19 @@ power: power { firmware =3D <&firmware>; #power-domain-cells =3D <1>; }; +}; + +&hvs { + clocks =3D <&firmware_clocks 4>, <&firmware_clocks 16>; + clock-names =3D "core", "disp"; +}; + +&hdmi0 { + clocks =3D <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_= 27MHz>; + clock-names =3D "hdmi", "bvb", "audio", "cec"; +}; =20 +&hdmi1 { + clocks =3D <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_= 27MHz>; + clock-names =3D "hdmi", "bvb", "audio", "cec"; }; diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dt= s/broadcom/bcm2712.dtsi index 6e5a984c1d4e..39305e0869ec 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -265,6 +265,172 @@ gicv2: interrupt-controller@7fff9000 { interrupt-controller; #interrupt-cells =3D <3>; }; + + aon_intr: interrupt-controller@7d510600 { + compatible =3D "brcm,bcm2711-l2-intc", "brcm,l2-intc"; + reg =3D <0x7d510600 0x30>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + + pixelvalve0: pixelvalve@7c410000 { + compatible =3D "brcm,bcm2712-pixelvalve0"; + reg =3D <0x7c410000 0x100>; + interrupts =3D ; + }; + + pixelvalve1: pixelvalve@7c411000 { + compatible =3D "brcm,bcm2712-pixelvalve1"; + reg =3D <0x7c411000 0x100>; + interrupts =3D ; + }; + + mop: mop@7c500000 { + compatible =3D "brcm,bcm2712-mop"; + reg =3D <0x7c500000 0x28>; + interrupt-parent =3D <&disp_intr>; + interrupts =3D <1>; + }; + + moplet: moplet@7c501000 { + compatible =3D "brcm,bcm2712-moplet"; + reg =3D <0x7c501000 0x20>; + interrupt-parent =3D <&disp_intr>; + interrupts =3D <0>; + }; + + disp_intr: interrupt-controller@7c502000 { + compatible =3D "brcm,bcm2711-l2-intc", "brcm,l2-intc"; + reg =3D <0x7c502000 0x30>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + + dvp: clock@7c700000 { + compatible =3D "brcm,brcm2711-dvp"; + reg =3D <0x7c700000 0x10>; + clocks =3D <&clk_108MHz>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + ddc0: i2c@7d508200 { + compatible =3D "brcm,brcmstb-i2c"; + reg =3D <0x7d508200 0x58>; + interrupt-parent =3D <&bsc_irq>; + interrupts =3D <1>; + clock-frequency =3D <97500>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + ddc1: i2c@7d508280 { + compatible =3D "brcm,brcmstb-i2c"; + reg =3D <0x7d508280 0x58>; + interrupt-parent =3D <&bsc_irq>; + interrupts =3D <2>; + clock-frequency =3D <97500>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + bsc_irq: intc@7d508380 { + compatible =3D "brcm,bcm7271-l2-intc"; + reg =3D <0x7d508380 0x10>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + + main_irq: intc@7d508400 { + compatible =3D "brcm,bcm7271-l2-intc"; + reg =3D <0x7d508400 0x10>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + + hdmi0: hdmi@7ef00700 { + compatible =3D "brcm,bcm2712-hdmi0"; + reg =3D <0x7c701400 0x300>, + <0x7c701000 0x200>, + <0x7c701d00 0x300>, + <0x7c702000 0x80>, + <0x7c703800 0x200>, + <0x7c704000 0x800>, + <0x7c700100 0x80>, + <0x7d510800 0x100>, + <0x7c720000 0x100>; + reg-names =3D "hdmi", + "dvp", + "phy", + "rm", + "packet", + "metadata", + "csc", + "cec", + "hd"; + resets =3D <&dvp 1>; + interrupt-parent =3D <&aon_intr>; + interrupts =3D <1>, <2>, <3>, + <7>, <8>; + interrupt-names =3D "cec-tx", "cec-rx", "cec-low", + "hpd-connected", "hpd-removed"; + ddc =3D <&ddc0>; + }; + + hdmi1: hdmi@7ef05700 { + compatible =3D "brcm,bcm2712-hdmi1"; + reg =3D <0x7c706400 0x300>, + <0x7c706000 0x200>, + <0x7c706d00 0x300>, + <0x7c707000 0x80>, + <0x7c708800 0x200>, + <0x7c709000 0x800>, + <0x7c700180 0x80>, + <0x7d511000 0x100>, + <0x7c720000 0x100>; + reg-names =3D "hdmi", + "dvp", + "phy", + "rm", + "packet", + "metadata", + "csc", + "cec", + "hd"; + resets =3D <&dvp 2>; + interrupt-parent =3D <&aon_intr>; + interrupts =3D <11>, <12>, <13>, + <14>, <15>; + interrupt-names =3D "cec-tx", "cec-rx", "cec-low", + "hpd-connected", "hpd-removed"; + ddc =3D <&ddc1>; + }; + }; + + axi: axi { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + ranges =3D <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, + <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>, + <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, + <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, + <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; + + dma-ranges =3D <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, + <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>, + <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, + <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, + <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; + + vc4: gpu { + compatible =3D "brcm,bcm2712-vc6"; + }; }; =20 timer { @@ -280,4 +446,26 @@ IRQ_TYPE_LEVEL_LOW)>, ; }; + + clk_27MHz: clk-27M { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <27000000>; + clock-output-names =3D "27MHz-clock"; + }; + + clk_108MHz: clk-108M { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <108000000>; + clock-output-names =3D "108MHz-clock"; + }; + + hvs: hvs@107c580000 { + compatible =3D "brcm,bcm2712-hvs"; + reg =3D <0x10 0x7c580000 0x0 0x1a000>; + interrupt-parent =3D <&disp_intr>; + interrupts =3D <2>, <9>, <16>; + interrupt-names =3D "ch0-eof", "ch1-eof", "ch2-eof"; + }; }; --=20 2.34.1