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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241025-drm-vc4-2712-support-v2-11-35efa83c8fc0@raspberrypi.com> References: <20241025-drm-vc4-2712-support-v2-0-35efa83c8fc0@raspberrypi.com> In-Reply-To: <20241025-drm-vc4-2712-support-v2-0-35efa83c8fc0@raspberrypi.com> To: Maxime Ripard , =?utf-8?q?Ma=C3=ADra_Canal?= , Raspberry Pi Kernel Maintenance , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Ray Jui , Scott Branden , Michael Turquette , Stephen Boyd , Javier Martinez Canillas , Catalin Marinas , Will Deacon Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Dave Stevenson X-Mailer: b4 0.14.1 From: Maxime Ripard The PixelValves found on the BCM2712 are similar to the ones found in the previous generation. Compared to BCM2711: - the pixelvalves only drive one HDMI controller each - HDMI1 PixelValve has a FIFO long enough to support 4k at 60Hz - support has been added for odd horizontal timings whilst at 2pixels/clock Signed-off-by: Maxime Ripard Signed-off-by: Dave Stevenson --- drivers/gpu/drm/vc4/vc4_crtc.c | 49 ++++++++++++++++++++++++++++++++++++++= ++-- drivers/gpu/drm/vc4/vc4_drv.h | 2 ++ drivers/gpu/drm/vc4/vc4_regs.h | 6 ++++++ 3 files changed, 55 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 53bca104d0d5..bfa25efa5db2 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -240,6 +240,11 @@ static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc= 4_crtc, u32 format) const struct vc4_crtc_data *crtc_data =3D vc4_crtc_to_vc4_crtc_data(vc4_c= rtc); const struct vc4_pv_data *pv_data =3D vc4_crtc_to_vc4_pv_data(vc4_crtc); struct vc4_dev *vc4 =3D to_vc4_dev(vc4_crtc->base.dev); + + /* + * NOTE: Could we use register 0x68 (PV_HW_CFG1) to get the FIFO + * size? + */ u32 fifo_len_bytes =3D pv_data->fifo_depth; =20 /* @@ -421,6 +426,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, s= truct drm_encoder *encode */ CRTC_WRITE(PV_V_CONTROL, PV_VCONTROL_CONTINUOUS | + (vc4->gen >=3D VC4_GEN_6_C ? PV_VCONTROL_ODD_TIMING : 0) | (is_dsi ? PV_VCONTROL_DSI : 0) | PV_VCONTROL_INTERLACE | (odd_field_first @@ -432,6 +438,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, s= truct drm_encoder *encode } else { CRTC_WRITE(PV_V_CONTROL, PV_VCONTROL_CONTINUOUS | + (vc4->gen >=3D VC4_GEN_6_C ? PV_VCONTROL_ODD_TIMING : 0) | (is_dsi ? PV_VCONTROL_DSI : 0)); CRTC_WRITE(PV_VSYNCD_EVEN, 0); } @@ -446,11 +453,17 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc,= struct drm_encoder *encode if (is_dsi) CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); =20 - if (vc4->gen =3D=3D VC4_GEN_5) + if (vc4->gen >=3D VC4_GEN_5) CRTC_WRITE(PV_MUX_CFG, VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP, PV_MUX_CFG_RGB_PIXEL_MUX_MODE)); =20 + if (vc4->gen >=3D VC4_GEN_6_C) + CRTC_WRITE(PV_PIPE_INIT_CTRL, + VC4_SET_FIELD(1, PV_PIPE_INIT_CTRL_PV_INIT_WIDTH) | + VC4_SET_FIELD(1, PV_PIPE_INIT_CTRL_PV_INIT_IDLE) | + PV_PIPE_INIT_CTRL_PV_INIT_EN); + CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) | VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | @@ -549,7 +562,11 @@ int vc4_crtc_disable_at_boot(struct drm_crtc *crtc) if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node, "brcm,bcm2711-pixelvalve2") || of_device_is_compatible(vc4_crtc->pdev->dev.of_node, - "brcm,bcm2711-pixelvalve4"))) + "brcm,bcm2711-pixelvalve4") || + of_device_is_compatible(vc4_crtc->pdev->dev.of_node, + "brcm,bcm2712-pixelvalve0") || + of_device_is_compatible(vc4_crtc->pdev->dev.of_node, + "brcm,bcm2712-pixelvalve1"))) return 0; =20 if (!(CRTC_READ(PV_CONTROL) & PV_CONTROL_EN)) @@ -1292,6 +1309,32 @@ const struct vc4_pv_data bcm2711_pv4_data =3D { }, }; =20 +const struct vc4_pv_data bcm2712_pv0_data =3D { + .base =3D { + .debugfs_name =3D "crtc0_regs", + .hvs_available_channels =3D BIT(0), + .hvs_output =3D 0, + }, + .fifo_depth =3D 64, + .pixels_per_clock =3D 1, + .encoder_types =3D { + [0] =3D VC4_ENCODER_TYPE_HDMI0, + }, +}; + +const struct vc4_pv_data bcm2712_pv1_data =3D { + .base =3D { + .debugfs_name =3D "crtc1_regs", + .hvs_available_channels =3D BIT(1), + .hvs_output =3D 1, + }, + .fifo_depth =3D 64, + .pixels_per_clock =3D 1, + .encoder_types =3D { + [0] =3D VC4_ENCODER_TYPE_HDMI1, + }, +}; + static const struct of_device_id vc4_crtc_dt_match[] =3D { { .compatible =3D "brcm,bcm2835-pixelvalve0", .data =3D &bcm2835_pv0_data= }, { .compatible =3D "brcm,bcm2835-pixelvalve1", .data =3D &bcm2835_pv1_data= }, @@ -1301,6 +1344,8 @@ static const struct of_device_id vc4_crtc_dt_match[] = =3D { { .compatible =3D "brcm,bcm2711-pixelvalve2", .data =3D &bcm2711_pv2_data= }, { .compatible =3D "brcm,bcm2711-pixelvalve3", .data =3D &bcm2711_pv3_data= }, { .compatible =3D "brcm,bcm2711-pixelvalve4", .data =3D &bcm2711_pv4_data= }, + { .compatible =3D "brcm,bcm2712-pixelvalve0", .data =3D &bcm2712_pv0_data= }, + { .compatible =3D "brcm,bcm2712-pixelvalve1", .data =3D &bcm2712_pv1_data= }, {} }; =20 diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h index aea585bf83eb..a68cea921c11 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.h +++ b/drivers/gpu/drm/vc4/vc4_drv.h @@ -558,6 +558,8 @@ extern const struct vc4_pv_data bcm2711_pv1_data; extern const struct vc4_pv_data bcm2711_pv2_data; extern const struct vc4_pv_data bcm2711_pv3_data; extern const struct vc4_pv_data bcm2711_pv4_data; +extern const struct vc4_pv_data bcm2712_pv0_data; +extern const struct vc4_pv_data bcm2712_pv1_data; =20 struct vc4_crtc { struct drm_crtc base; diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h index 9226429539cf..731b13742ef5 100644 --- a/drivers/gpu/drm/vc4/vc4_regs.h +++ b/drivers/gpu/drm/vc4/vc4_regs.h @@ -155,6 +155,7 @@ # define PV_CONTROL_EN BIT(0) =20 #define PV_V_CONTROL 0x04 +# define PV_VCONTROL_ODD_TIMING BIT(29) # define PV_VCONTROL_ODD_DELAY_MASK VC4_MASK(22, 6) # define PV_VCONTROL_ODD_DELAY_SHIFT 6 # define PV_VCONTROL_ODD_FIRST BIT(5) @@ -215,6 +216,11 @@ # define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_SHIFT 2 # define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP 8 =20 +#define PV_PIPE_INIT_CTRL 0x94 +# define PV_PIPE_INIT_CTRL_PV_INIT_WIDTH_MASK VC4_MASK(11, 8) +# define PV_PIPE_INIT_CTRL_PV_INIT_IDLE_MASK VC4_MASK(7, 4) +# define PV_PIPE_INIT_CTRL_PV_INIT_EN BIT(0) + #define SCALER_CHANNELS_COUNT 3 =20 #define SCALER_DISPCTRL 0x00000000 --=20 2.34.1