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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241025-dpu-virtual-wide-v6-8-0310fd519765@linaro.org> References: <20241025-dpu-virtual-wide-v6-0-0310fd519765@linaro.org> In-Reply-To: <20241025-dpu-virtual-wide-v6-0-0310fd519765@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=10756; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=4qNpQUOhNNwVlHnVY+cep13TqyWzrHpO52v1B/hEeg8=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnGuQ7JWBdORKrPuu9KuvRBASndaP/1geNPHWah HTAHwaUCVmJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZxrkOwAKCRCLPIo+Aiko 1QNRB/4lF91qmZEYWpZkSHR8uuFgIrbwF5xpmMIVwV5ptnwhbuqg7WVio3sYqR4BEqtKh8pYUQv Tp1FtAL24INDRHdQVmsUSoc1Ef2yrg/fr2vaM2pvvUeqHU67NGiWcELV/54duV24QBdn/WTJds2 wDJh56DbH3Veqfwn2hhyriwwlk2tawiBQ0wV1GiSHxfpSr5A7+RJm9vrT3+w0S8HFlyTaFJg22G XeW6ijz9hutpTf0sa0OCjSPCcJ69W6sgoEfZ84tQt8nL63KP3emep0tN4GU9ODgAhKF22pmsiFG rB/y4fOdj3kIvYFK+vqkiYkdcR3/uEdOl2A290xAUaIhaw5m X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Virtual wide planes give high amount of flexibility, but it is not always enough: In parallel multirect case only the half of the usual width is supported for tiled formats. Thus the whole width of two tiled multirect rectangles can not be greater than max_linewidth, which is not enough for some platforms/compositors. Another example is as simple as wide YUV plane. YUV planes can not use multirect, so currently they are limited to max_linewidth too. Now that the planes are fully virtualized, add support for allocating two SSPP blocks to drive a single DRM plane. This fixes both mentioned cases and allows all planes to go up to 2*max_linewidth (at the cost of making some of the planes unavailable to the user). Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 163 ++++++++++++++++++++++----= ---- 1 file changed, 119 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 125db3803cf5..ad6cc469f475 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -20,7 +20,6 @@ #include "msm_drv.h" #include "msm_mdss.h" #include "dpu_kms.h" -#include "dpu_formats.h" #include "dpu_hw_sspp.h" #include "dpu_hw_util.h" #include "dpu_trace.h" @@ -888,6 +887,28 @@ static int dpu_plane_atomic_check_nosspp(struct drm_pl= ane *plane, return 0; } =20 +static int dpu_plane_is_multirect_parallel_capable(struct dpu_sw_pipe *pip= e, + struct dpu_sw_pipe_cfg *pipe_cfg, + const struct msm_format *fmt, + uint32_t max_linewidth) +{ + if (drm_rect_width(&pipe_cfg->src_rect) !=3D drm_rect_width(&pipe_cfg->ds= t_rect) || + drm_rect_height(&pipe_cfg->src_rect) !=3D drm_rect_height(&pipe_cfg->= dst_rect)) + return false; + + if (pipe_cfg->rotation & DRM_MODE_ROTATE_90) + return false; + + if (MSM_FORMAT_IS_YUV(fmt)) + return false; + + if (MSM_FORMAT_IS_UBWC(fmt) && + drm_rect_width(&pipe_cfg->src_rect) > max_linewidth / 2) + return false; + + return true; +} + static int dpu_plane_atomic_check_sspp(struct drm_plane *plane, struct drm_atomic_state *state, const struct drm_crtc_state *crtc_state) @@ -901,7 +922,6 @@ static int dpu_plane_atomic_check_sspp(struct drm_plane= *plane, const struct msm_format *fmt; struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; - uint32_t max_linewidth; uint32_t supported_rotations; const struct dpu_sspp_cfg *pipe_hw_caps; const struct dpu_sspp_sub_blks *sblk; @@ -923,8 +943,6 @@ static int dpu_plane_atomic_check_sspp(struct drm_plane= *plane, =20 fmt =3D msm_framebuffer_format(new_plane_state->fb); =20 - max_linewidth =3D pdpu->catalog->caps->max_linewidth; - supported_rotations =3D DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; =20 if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) @@ -940,41 +958,6 @@ static int dpu_plane_atomic_check_sspp(struct drm_plan= e *plane, return ret; =20 if (drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0) { - /* - * In parallel multirect case only the half of the usual width - * is supported for tiled formats. If we are here, we know that - * full width is more than max_linewidth, thus each rect is - * wider than allowed. - */ - if (MSM_FORMAT_IS_UBWC(fmt) && - drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) { - DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled form= at\n", - DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); - return -E2BIG; - } - - if (drm_rect_width(&pipe_cfg->src_rect) !=3D drm_rect_width(&pipe_cfg->d= st_rect) || - drm_rect_height(&pipe_cfg->src_rect) !=3D drm_rect_height(&pipe_cfg-= >dst_rect) || - (!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) && - !test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) || - pipe_cfg->rotation & DRM_MODE_ROTATE_90 || - MSM_FORMAT_IS_YUV(fmt)) { - DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use = split source\n", - DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); - return -E2BIG; - } - - /* - * Use multirect for wide plane. We do not support dynamic - * assignment of SSPPs, so we know the configuration. - */ - pipe->multirect_index =3D DPU_SSPP_RECT_0; - pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_PARALLEL; - - r_pipe->sspp =3D pipe->sspp; - r_pipe->multirect_index =3D DPU_SSPP_RECT_1; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_PARALLEL; - ret =3D dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt, &crtc_state->adjusted_mode); if (ret) @@ -995,16 +978,16 @@ static int dpu_plane_atomic_check(struct drm_plane *p= lane, struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); struct dpu_sw_pipe *pipe =3D &pstate->pipe; struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; + struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; + struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; const struct drm_crtc_state *crtc_state =3D NULL; =20 if (new_plane_state->crtc) crtc_state =3D drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); =20 - if (pdpu->pipe !=3D SSPP_NONE) { - pipe->sspp =3D dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); - r_pipe->sspp =3D NULL; - } + pipe->sspp =3D dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); + r_pipe->sspp =3D NULL; =20 if (!pipe->sspp) return -EINVAL; @@ -1021,6 +1004,49 @@ static int dpu_plane_atomic_check(struct drm_plane *= plane, r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; =20 + if (drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0) { + uint32_t max_linewidth =3D dpu_kms->catalog->caps->max_linewidth; + const struct msm_format *fmt; + + fmt =3D msm_framebuffer_format(new_plane_state->fb); + + /* + * In parallel multirect case only the half of the usual width + * is supported for tiled formats. If we are here, we know that + * full width is more than max_linewidth, thus each rect is + * wider than allowed. + */ + if (MSM_FORMAT_IS_UBWC(fmt) && + drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) { + DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled form= at\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); + return -E2BIG; + } + + if (drm_rect_width(&pipe_cfg->src_rect) !=3D drm_rect_width(&pipe_cfg->d= st_rect) || + drm_rect_height(&pipe_cfg->src_rect) !=3D drm_rect_height(&pipe_cfg-= >dst_rect) || + (!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) && + !test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) || + pipe_cfg->rotation & DRM_MODE_ROTATE_90 || + MSM_FORMAT_IS_YUV(fmt)) { + DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use = split source\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); + return -E2BIG; + } + + /* + * Use multirect for wide plane. We do not support dynamic + * assignment of SSPPs, so we know the configuration. + */ + r_pipe->sspp =3D pipe->sspp; + + pipe->multirect_index =3D DPU_SSPP_RECT_0; + pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_PARALLEL; + + r_pipe->multirect_index =3D DPU_SSPP_RECT_1; + r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_PARALLEL; + } + return dpu_plane_atomic_check_sspp(plane, state, crtc_state); } =20 @@ -1054,8 +1080,16 @@ static int dpu_plane_virtual_atomic_check(struct drm= _plane *plane, return 0; } =20 - /* force resource reallocation if the format of FB has changed */ + /* + * Force resource reallocation if the format of FB or src/dst have + * changed. We might need to allocate different SSPP or SSPPs for this + * plane than the one used previously. + */ if (!old_plane_state || !old_plane_state->fb || + old_plane_state->src_w !=3D plane_state->src_w || + old_plane_state->src_h !=3D plane_state->src_h || + old_plane_state->src_w !=3D plane_state->src_w || + old_plane_state->crtc_h !=3D plane_state->crtc_h || msm_framebuffer_format(old_plane_state->fb) !=3D msm_framebuffer_format(plane_state->fb)) crtc_state->planes_changed =3D true; @@ -1075,7 +1109,10 @@ static int dpu_plane_virtual_assign_resources(struct= drm_crtc *crtc, struct dpu_plane_state *pstate; struct dpu_sw_pipe *pipe; struct dpu_sw_pipe *r_pipe; + struct dpu_sw_pipe_cfg *pipe_cfg; + struct dpu_sw_pipe_cfg *r_pipe_cfg; const struct msm_format *fmt; + uint32_t max_linewidth; =20 if (plane_state->crtc) crtc_state =3D drm_atomic_get_new_crtc_state(state, @@ -1084,6 +1121,8 @@ static int dpu_plane_virtual_assign_resources(struct = drm_crtc *crtc, pstate =3D to_dpu_plane_state(plane_state); pipe =3D &pstate->pipe; r_pipe =3D &pstate->r_pipe; + pipe_cfg =3D &pstate->pipe_cfg; + r_pipe_cfg =3D &pstate->r_pipe_cfg; =20 pipe->sspp =3D NULL; r_pipe->sspp =3D NULL; @@ -1098,10 +1137,46 @@ static int dpu_plane_virtual_assign_resources(struc= t drm_crtc *crtc, =20 reqs.rot90 =3D drm_rotation_90_or_270(plane_state->rotation); =20 + max_linewidth =3D dpu_kms->catalog->caps->max_linewidth; + pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &req= s); if (!pipe->sspp) return -ENODEV; =20 + if (drm_rect_width(&r_pipe_cfg->src_rect) =3D=3D 0) { + pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + + r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + + r_pipe->sspp =3D NULL; + } else { + if (dpu_plane_is_multirect_parallel_capable(pipe, pipe_cfg, fmt, max_lin= ewidth) && + dpu_plane_is_multirect_parallel_capable(r_pipe, r_pipe_cfg, fmt, max= _linewidth) && + (test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) || + test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features))) { + r_pipe->sspp =3D pipe->sspp; + + pipe->multirect_index =3D DPU_SSPP_RECT_0; + pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_PARALLEL; + + r_pipe->multirect_index =3D DPU_SSPP_RECT_1; + r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_PARALLEL; + } else { + /* multirect is not possible, use two SSPP blocks */ + r_pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, = &reqs); + if (!r_pipe->sspp) + return -ENODEV; + + pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + + r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + } + } + return dpu_plane_atomic_check_sspp(plane, state, crtc_state); } =20 --=20 2.39.5