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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241025-dpu-virtual-wide-v6-2-0310fd519765@linaro.org> References: <20241025-dpu-virtual-wide-v6-0-0310fd519765@linaro.org> In-Reply-To: <20241025-dpu-virtual-wide-v6-0-0310fd519765@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2729; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=PHJ6sTq6uvNcQ3gChU8Ct2HDM9wv2LQmbjOrC4ORXdI=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnGuQ6hQho0KIgBTBFvj9q6BbQKv0Gp3wic2CJz SwNl9VOghaJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZxrkOgAKCRCLPIo+Aiko 1UgnB/4lW/gdxBKLrIy5SBKyqWzevme3eymEBo8+UbDaxqGVnggcx0aM3CP9kZvr0Ii5OvjBcvf 0fSlCwZh/tVpiyYOw+1/ZTNRm7qxPE9FSWmL5GCK0kOeYQ+sPmyHP7kB09bWO8lLVYkJ1srq1WK 0XU9iMZHCM+ZKo00OqpFD3Nw6lhKdSvqauT2HRfoYmhOkTl+DokoGE5EIOW5CwQ97/9xD3I/X6F 0ZBtfkevH5jV4TlTLyUTvnulTMNGBFWdFwZe3igUVvKuTCJt+PzzxmCe5+LmW2iZrPMq51iozPO 7HnoidCOp3JT5A2rfeMCr2jvND7ccagqEPRH7j1IHvNb2/XU X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A In preparation for virtualized planes support, move pstate->pipe initialization from dpu_plane_reset() to dpu_plane_atomic_check(). In case of virtual planes the plane's pipe will not be known up to the point of atomic_check() callback. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 37faf5b238b0..725c9a5826fd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -797,13 +797,22 @@ static int dpu_plane_atomic_check(struct drm_plane *p= lane, uint32_t max_linewidth; unsigned int rotation; uint32_t supported_rotations; - const struct dpu_sspp_cfg *pipe_hw_caps =3D pstate->pipe.sspp->cap; - const struct dpu_sspp_sub_blks *sblk =3D pstate->pipe.sspp->cap->sblk; + const struct dpu_sspp_cfg *pipe_hw_caps; + const struct dpu_sspp_sub_blks *sblk; =20 if (new_plane_state->crtc) crtc_state =3D drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); =20 + pipe->sspp =3D dpu_rm_get_sspp(&kms->rm, pdpu->pipe); + r_pipe->sspp =3D NULL; + + if (!pipe->sspp) + return -EINVAL; + + pipe_hw_caps =3D pipe->sspp->cap; + sblk =3D pipe->sspp->cap->sblk; + min_scale =3D FRAC_16_16(1, sblk->maxupscale); ret =3D drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, min_scale, @@ -820,7 +829,6 @@ static int dpu_plane_atomic_check(struct drm_plane *pla= ne, pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; - r_pipe->sspp =3D NULL; =20 pstate->stage =3D DPU_STAGE_0 + pstate->base.normalized_zpos; if (pstate->stage >=3D pdpu->catalog->caps->max_mixer_blendstages) { @@ -1286,7 +1294,6 @@ static void dpu_plane_reset(struct drm_plane *plane) { struct dpu_plane *pdpu; struct dpu_plane_state *pstate; - struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); =20 if (!plane) { DPU_ERROR("invalid plane\n"); @@ -1308,16 +1315,6 @@ static void dpu_plane_reset(struct drm_plane *plane) return; } =20 - /* - * Set the SSPP here until we have proper virtualized DPU planes. - * This is the place where the state is allocated, so fill it fully. - */ - pstate->pipe.sspp =3D dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); - pstate->pipe.multirect_index =3D DPU_SSPP_RECT_SOLO; - pstate->pipe.multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; - - pstate->r_pipe.sspp =3D NULL; - __drm_atomic_helper_plane_reset(plane, &pstate->base); } =20 --=20 2.39.5