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([2403:c300:5606:d914:fec1:9dc9:d21d:9b02]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e7f0bd376sm69782065ad.132.2024.10.24.03.17.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2024 03:17:42 -0700 (PDT) From: Tony Chung To: gregkh@linuxfoundation.org Cc: johan@kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Tony Chung Subject: [PATCH 3/3] driver: usb: serial: mos7840: add more baudrate options Date: Thu, 24 Oct 2024 18:09:05 +0800 Message-Id: <20241024100901.69883-4-tony467913@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241024100901.69883-1-tony467913@gmail.com> References: <20241024100901.69883-1-tony467913@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adds more baud rate options using 96M/30M/External clock sources. To use these clock sources, set through Clk_Select_Reg1 and Clk_Select_Reg2. Signed-off-by: Tony Chung --- drivers/usb/serial/mos7840.c | 156 ++++++++++++++++++++++++++++++++++- 1 file changed, 155 insertions(+), 1 deletion(-) diff --git a/drivers/usb/serial/mos7840.c b/drivers/usb/serial/mos7840.c index acc16737b..70ee4a638 100644 --- a/drivers/usb/serial/mos7840.c +++ b/drivers/usb/serial/mos7840.c @@ -1169,6 +1169,37 @@ static int mos7840_calc_baud_rate_divisor(struct usb= _serial_port *port, *divisor =3D 0x01; // DLM=3D0, DLL=3D0x01 *clk_sel_val =3D 0x60; // clock source=3D24M =20 + /* below are using 96M or 30M clock source + * will determine the clock source later + * in function mos7840_send_cmd_write_baud_rate + */ + } else if (baudRate =3D=3D 6000000) { + *divisor =3D 0x01; // DLM=3D0, DLL=3D0x01 + *clk_sel_val =3D 0x80; // DUMMY val, clock source =3D 96M + } else if (baudRate =3D=3D 2000000) { + *divisor =3D 0x03; // DLM=3D0, DLL=3D0x03 + *clk_sel_val =3D 0x80; // DUMMY val, clock source =3D 96M + } else if (baudRate =3D=3D 403200) { + *divisor =3D 0x0f; // DLM=3D0, DLL=3D0x0f + *clk_sel_val =3D 0x80; // DUMMY val, clock source =3D 96M + } else if (baudRate =3D=3D 225000) { + *divisor =3D 0x1b; // DLM=3D0, DLL=3D0x1b + *clk_sel_val =3D 0x80; // DUMMY val, clock source =3D 96M + } else if (baudRate =3D=3D 153600) { + *divisor =3D 0x27; // DLM=3D0, DLL=3D0x27 + *clk_sel_val =3D 0x80; // DUMMY val, clock source =3D 96M + + } else if (baudRate =3D=3D 10000) { + *divisor =3D 0xbb; // DLM=3D0, DLL=3D0xbb + *clk_sel_val =3D 0x80; // DUMMY val, clock source =3D 30M + } else if (baudRate =3D=3D 125000) { + *divisor =3D 0x0f; // DLM=3D0, DLL=3D0x0f + *clk_sel_val =3D 0x80; // DUMMY val, clock source =3D 30M + } else if (baudRate =3D=3D 625000) { + *divisor =3D 0x03; // DLM=3D0, DLL=3D0x03 + *clk_sel_val =3D 0x80; // DUMMY val, clock source =3D 30M + + } else if (baudRate <=3D 115200) { *divisor =3D 115200 / baudRate; *clk_sel_val =3D 0x0; @@ -1246,11 +1277,134 @@ static int mos7840_send_cmd_write_baud_rate(struct= moschip_port *mos7840_port, =20 } =20 - if (1) { /* baudRate <=3D 115200) */ + if (1) { clk_sel_val =3D 0x0; Data =3D 0x0; status =3D mos7840_calc_baud_rate_divisor(port, baudRate, &divisor, &clk_sel_val); + if (status < 0) { + dev_dbg(&port->dev, "%s failed in set_serial_baud\n", __func__); + return -1; + } + + /* Write clk_sel_val to SP_Reg or Clk_Select_Reg*/ + // check clk_sel_val before setting the clk_sel_val + if (clk_sel_val =3D=3D 0x80) { + // clk_sel_val is DUMMY value -> Write the corresponding value to Clk_Se= lect_Reg + // 0x01:30M, 0x02:96M, 0x05:External Clock + if (baudRate =3D=3D 125000 || baudRate =3D=3D 625000 || baudRate =3D=3D= 10000) { + clk_sel_val =3D 0x01; + } else if (baudRate =3D=3D 153600 || baudRate =3D=3D 225000 || baudRate= =3D=3D 403200 || + baudRate =3D=3D 2000000 || baudRate =3D=3D 6000000) { + clk_sel_val =3D 0x02; + } else { + clk_sel_val =3D 0x05; // externel clk for custom case. + } + + // needs to set clock source through + // Clk_Select_Reg1(offset 0x13) & Clk_Select_Reg2(offset 0x14) + // Clk_Select_Reg1 for port1,2 Clk_Select_Reg2 for port3,4 + if (mos7840_port->port_num <=3D 2) { + status =3D mos7840_get_reg_sync(port, CLOCK_SELECT_REG1, &Data); + if (status < 0) { + dev_dbg(&port->dev, "reading Clk_Select_Reg failed in set_serial_baud= \n"); + return -1; + } + if (mos7840_port->port_num =3D=3D 1) { + Data =3D (Data & 0xf8) | clk_sel_val; + status =3D + mos7840_set_reg_sync(port, CLOCK_SELECT_REG1, Data); + } else if (mos7840_port->port_num =3D=3D 2) { + Data =3D (Data & 0xc7) | (clk_sel_val<<3); + status =3D + mos7840_set_reg_sync(port, CLOCK_SELECT_REG1, Data); + } + if (status < 0) { + dev_dbg(&port->dev, "setting Clk_Select_Reg failed\n"); + return -1; + } + } else if (mos7840_port->port_num <=3D 4) { + status =3D mos7840_get_reg_sync(port, CLOCK_SELECT_REG2, &Data); + if (status < 0) { + dev_dbg(&port->dev, "reading Clk_Select_Reg failed in set_serial_baud= \n"); + return -1; + } + if (mos7840_port->port_num =3D=3D 3) { + Data =3D (Data & 0xf8) | clk_sel_val; + status =3D + mos7840_set_reg_sync(port, CLOCK_SELECT_REG2, Data); + } else if (mos7840_port->port_num =3D=3D 4) { + Data =3D (Data & 0xc7) | (clk_sel_val<<3); + status =3D + mos7840_set_reg_sync(port, CLOCK_SELECT_REG2, Data); + } + if (status < 0) { + dev_dbg(&port->dev, "setting Clk_Select_Reg failed\n"); + return -1; + } + } + } else { + // clk_sel_val is not DUMMY value -> Write the corresponding value to SP= _Reg + + /* First, needs to write default value to + * Clk_Select_Reg1(offset 0x13) & Clk_Select_Reg2(offset 0x14) + * Clk_Select_Reg1 for port1,2 Clk_Select_Reg2 for port3,4 + */ + if (mos7840_port->port_num <=3D 2) { + status =3D mos7840_get_reg_sync(port, CLOCK_SELECT_REG1, &Data); + if (status < 0) { + dev_dbg(&port->dev, "reading Clk_Select_Reg failed in set_serial_baud= \n"); + return -1; + } + if (mos7840_port->port_num =3D=3D 1) { + Data =3D (Data & 0xf8) | 0x00; + status =3D + mos7840_set_reg_sync(port, CLOCK_SELECT_REG1, Data); + } else if (mos7840_port->port_num =3D=3D 2) { + Data =3D (Data & 0xc7) | (0x00<<3); + status =3D + mos7840_set_reg_sync(port, CLOCK_SELECT_REG1, Data); + } + if (status < 0) { + dev_dbg(&port->dev, "setting Clk_Select_Reg failed\n"); + return -1; + } + } else if (mos7840_port->port_num <=3D 4) { + status =3D mos7840_get_reg_sync(port, CLOCK_SELECT_REG2, &Data); + if (status < 0) { + dev_dbg(&port->dev, "reading Clk_Select_Reg failed in set_serial_baud= \n"); + return -1; + } + if (mos7840_port->port_num =3D=3D 3) { + Data =3D (Data & 0xf8) | 0x00; + status =3D + mos7840_set_reg_sync(port, CLOCK_SELECT_REG2, Data); + } else if (mos7840_port->port_num =3D=3D 4) { + Data =3D (Data & 0xc7) | (0x00<<3); + status =3D + mos7840_set_reg_sync(port, CLOCK_SELECT_REG2, Data); + } + if (status < 0) { + dev_dbg(&port->dev, "setting Clk_Select_Reg failed\n"); + return -1; + } + } + // select clock source by writing clk_sel_val to SPx_Reg + status =3D mos7840_get_reg_sync(port, mos7840_port->SpRegOffset, + &Data); + if (status < 0) { + dev_dbg(&port->dev, "reading spreg failed in set_serial_baud\n"); + return -1; + } + Data =3D (Data & 0x8f) | clk_sel_val; + status =3D mos7840_set_reg_sync(port, mos7840_port->SpRegOffset, + Data); + if (status < 0) { + dev_dbg(&port->dev, "Writing spreg failed in set_serial_baud\n"); + return -1; + } + } + status =3D mos7840_get_reg_sync(port, mos7840_port->SpRegOffset, &Data); if (status < 0) { --=20 2.34.1