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([2403:c300:5606:d914:fec1:9dc9:d21d:9b02]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e7f0bd376sm69782065ad.132.2024.10.24.03.16.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2024 03:16:30 -0700 (PDT) From: Tony Chung To: gregkh@linuxfoundation.org Cc: johan@kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Tony Chung Subject: [PATCH 1/3] drivers: usb: serial: mos7840: Add defines for clock select register offset Date: Thu, 24 Oct 2024 18:09:01 +0800 Message-Id: <20241024100901.69883-2-tony467913@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241024100901.69883-1-tony467913@gmail.com> References: <20241024100901.69883-1-tony467913@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch adds define for CLOCK_SELECT_REG1 & CLOCK_SELECT_REG2 offsets. These two registers can select clock source between 30M/96M/External. Signed-off-by: Tony Chung --- drivers/usb/serial/mos7840.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/serial/mos7840.c b/drivers/usb/serial/mos7840.c index ca3da79af..362875a53 100644 --- a/drivers/usb/serial/mos7840.c +++ b/drivers/usb/serial/mos7840.c @@ -144,6 +144,9 @@ =20 #define SERIAL_LCR_DLAB ((__u16)(0x0080)) =20 +#define CLOCK_SELECT_REG1 ((__u16)(0x13)) +#define CLOCK_SELECT_REG2 ((__u16)(0x14)) + /* * URB POOL related defines */ --=20 2.34.1 From nobody Mon Nov 25 21:40:33 2024 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB00E1B0F2B; Thu, 24 Oct 2024 10:16:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729765018; cv=none; b=jJd+4sYm91QI9s5cba22XX2DkjOGWZHjeSaW1qUoqOln38Ji3RSbin7quXa2zcBGmN0bbU0xqfMIt1MbzXS0O4SoCXELUubUDTj0lwNo3qoWV56Umik5Lz7b8PMPsRXRD/vDhEkhej5iGjBXfRo0mbzJpE+N/zfSTZoHzt7zqmk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729765018; c=relaxed/simple; bh=qmPDOcWi4GZ2WL2qnJgzDrV08NLOO3YnKWxWoOl+R9w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EjajhMZAOit2eP89nSU94x4vwyG2gpUFt5lDCfA7qymkoOqbbKZgeWjPtZacEiBxvZjs+3BaUTgPSEM8GAkmJ9JdYrqn1ZtQrt/9XakIgwX41bDKpJpGO+rlmbropNGGAxyqkRHp+vFX0N86LD7z2wpeEq1vgIF9DhPgRGdIKYo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=h+UySiUl; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="h+UySiUl" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-20c7ee8fe6bso5192945ad.2; Thu, 24 Oct 2024 03:16:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729765016; x=1730369816; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pvZ1ZhPe43+xA+24X/t0+zXdfah6Ns/POWttndJQ8qQ=; b=h+UySiUlyGPGbUci6A18FH9skJBdR6NFSBV4cnpc0KIbVYCbx75B7ZDN4cMzRPbyo+ 6YDPBTl7+7iU8pzmzTwGbN4Jp4JrrQWCN3qn9TSYEsc/+8XmwCEm/SIIbr+l6B3L54Am 1V+hp9o4ZmZEdOKqma2C1eIbFe/X8wLS86F/aVYoLr28XN8/M9eKxYFaEXfuhx3b+QCq MNLaPCfPd3cifsDjqwRIQyGBzqR8eulKR5jwkJHP6hvJfOQE41Ne/qpNlxeBISRm693v ek2d/IhOjhMw6CO26rzY/odgNw4azJl6wqcuXxfbwmuFO4nLUHKImmcnaUCdJWMA7IhY brig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729765016; x=1730369816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pvZ1ZhPe43+xA+24X/t0+zXdfah6Ns/POWttndJQ8qQ=; b=L5D7QTWsqafR5HXlfa7+ueVOHo4oZBNpNDBmEh74y+BLaulsrj6pe/GzP7i+Q2+Axl yZH73Y+06ZJWSKFBXf/rnoQt9b73BYSd559TPdCLZOq1eC46WSlOcQF6IOKQZSZhW5OF NCbu0CzF1uolPv2c3Q3RoYJfBvLECOu93dTR2+5t789WNWnHhH+MPpUhAlHlHctj5PfD V7SXKsJXTS2P30yXziykNYCtzWA1IQJOZrPlYbJnY899+7Zkq+bHvAMmS1jUpo3p5VWT eoEfAwBtLO/0bJj5velo75g7jiXYcLaM+LpIK/q+CJk1L1nPQTw2xx/+I4rVWtpj6ScG YBVw== X-Forwarded-Encrypted: i=1; AJvYcCUbVFqtc2sx62V0xJqpLGd7U+nuTk8rbm0UVF9+TKyGn8RXrLV7M4eEVpHDUKOZaVVMC9NzhBEvE1Ir@vger.kernel.org, AJvYcCXn3MH5hlandLPZeIJYIUjoznPRCOoricsndtjW3JiLfuOeoPY+SFjtFutYrYS3xIlDbPfJ5lRrhwIXKng=@vger.kernel.org X-Gm-Message-State: AOJu0YxZQavFZ4dWVChcy35Ncp6AQnvmbx6EPHblF9U81vawQHw/5D9x 80uRt7p2x9TyTO0q+a4rSzAalgQDmW654lUk29dishiLs8JsoV7K940NrP1iucc= X-Google-Smtp-Source: AGHT+IFDHMJxcGzxyDj6XM0QRJdQj9V+xj/hmPYE0tIDSciLcrYoMRr4/vtKEHT6Z4MU+Y+MWNWu9w== X-Received: by 2002:a17:903:22c1:b0:20c:a04f:927d with SMTP id d9443c01a7336-20fb99d3784mr15869935ad.33.1729765015805; Thu, 24 Oct 2024 03:16:55 -0700 (PDT) Received: from asix-MS-7816.. ([2403:c300:5606:d914:fec1:9dc9:d21d:9b02]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e7f0bd376sm69782065ad.132.2024.10.24.03.16.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2024 03:16:55 -0700 (PDT) From: Tony Chung To: gregkh@linuxfoundation.org Cc: johan@kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Tony Chung Subject: [PATCH 2/3] drivers: usb: serial: mos7840: added optimized register setups for common baudrates. Date: Thu, 24 Oct 2024 18:09:03 +0800 Message-Id: <20241024100901.69883-3-tony467913@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241024100901.69883-1-tony467913@gmail.com> References: <20241024100901.69883-1-tony467913@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" added optimized register setups for common baudrates. Signed-off-by: Tony Chung --- drivers/usb/serial/mos7840.c | 114 ++++++++++++++++++++++++++++++++++- 1 file changed, 111 insertions(+), 3 deletions(-) diff --git a/drivers/usb/serial/mos7840.c b/drivers/usb/serial/mos7840.c index 362875a53..acc16737b 100644 --- a/drivers/usb/serial/mos7840.c +++ b/drivers/usb/serial/mos7840.c @@ -1063,11 +1063,116 @@ static int mos7840_calc_baud_rate_divisor(struct u= sb_serial_port *port, { dev_dbg(&port->dev, "%s - %d\n", __func__, baudRate); =20 - if (baudRate <=3D 115200) { + // divisor =3D (256*DLM)+DLL + // baudrate =3D InputCLK/(16*Divisor) + if (baudRate =3D=3D 50) { + *divisor =3D (256*0x09)+0x04; // DLM=3D0x09, DLL=3D0x04 + *clk_sel_val =3D 0x0; // clock source =3D 1.846153846M + } else if (baudRate =3D=3D 75) { + *divisor =3D (256*0x06)+0x02; // DLM=3D0x06, DLL=3D0x02 + *clk_sel_val =3D 0x0; // clock source =3D 1.846153846M + } else if (baudRate =3D=3D 110) { + *divisor =3D (256*0x04)+0x19; // DLM=3D0x04, DLL=3D0x19 + *clk_sel_val =3D 0x0; // clock source =3D 1.846153846M + } else if (baudRate =3D=3D 134) { + *divisor =3D (256*0x03)+0x5d; // DLM=3D0x03, DLL=3D0x5d + *clk_sel_val =3D 0x0; // clock source =3D 1.846153846M + } else if (baudRate =3D=3D 150) { + *divisor =3D (256*0x03)+0x01; // DLM=3D0x03, DLL=3D0x01 + *clk_sel_val =3D 0x0; // clock source =3D 1.846153846M + } else if (baudRate =3D=3D 300) { + *divisor =3D (256*0x01)+0x81; // DLM=3D0x01, DLL=3D0x81 + *clk_sel_val =3D 0x0; // clock source =3D 1.846153846M + } else if (baudRate =3D=3D 600) { + *divisor =3D 0xc0; // DLM=3D0, DLL=3D0xc0 + *clk_sel_val =3D 0x0; // clock source =3D 1.846153846M + } else if (baudRate =3D=3D 1200) { + *divisor =3D 0x60; // DLM=3D0, DLL=3D0x60 + *clk_sel_val =3D 0x0; // clock source =3D 1.846153846M + } else if (baudRate =3D=3D 1800) { + *divisor =3D 0x40; // DLM=3D0, DLL=3D0x40 + *clk_sel_val =3D 0x0; // clock source =3D 1.846153846M + } else if (baudRate =3D=3D 2400) { + *divisor =3D 0x30; // DLM=3D0, DLL=3D0x30 + *clk_sel_val =3D 0x0; // clock source =3D 1.846153846M + } else if (baudRate =3D=3D 4800) { + *divisor =3D 0x18; // DLM=3D0, DLL=3D0x18 + *clk_sel_val =3D 0x0; // clock source =3D 1.846153846M + } else if (baudRate =3D=3D 7200) { + *divisor =3D 0x10; // DLM=3D0, DLL=3D0x10 + *clk_sel_val =3D 0x0; // clock source =3D 1.846153846M + } else if (baudRate =3D=3D 9600) { + *divisor =3D 0x0c; // DLM=3D0, DLL=3D0x0c + *clk_sel_val =3D 0x0; // clock source =3D 1.846153846M + } else if (baudRate =3D=3D 14400) { + *divisor =3D 0x08; // DLM=3D0, DLL=3D0x08 + *clk_sel_val =3D 0x0; // clock source =3D 1.846153846M + } else if (baudRate =3D=3D 19200) { + *divisor =3D 0x06; // DLM=3D0, DLL=3D0x06 + *clk_sel_val =3D 0x0; // clock source =3D 1.846153846M + } else if (baudRate =3D=3D 28800) { + *divisor =3D 0x04; // DLM=3D0, DLL=3D0x04 + *clk_sel_val =3D 0x0; // clock source =3D 1.846153846M + } else if (baudRate =3D=3D 38400) { + *divisor =3D 0x03; // DLM=3D0, DLL=3D0x03 + *clk_sel_val =3D 0x0; // clock source =3D 1.846153846M + } else if (baudRate =3D=3D 57600) { + *divisor =3D 0x02; // DLM=3D0, DLL=3D0x02 + *clk_sel_val =3D 0x0; // clock source =3D 1.846153846M + } else if (baudRate =3D=3D 115200) { + *divisor =3D 0x01; // DLM=3D0, DLL=3D0x01 + *clk_sel_val =3D 0x0; // clock source =3D 1.846153846M + } else if (baudRate =3D=3D 230400) { + *divisor =3D 0x01; // DLM=3D0, DLL=3D0x01 + *clk_sel_val =3D 0x10; // clock source =3D 3.692307692M + } else if (baudRate =3D=3D 460800) { + *divisor =3D 0x01; // DLM=3D0, DLL=3D0x01 + *clk_sel_val =3D 0x30; // clock source =3D 7.384615384M + } else if (baudRate =3D=3D 806400) { + *divisor =3D 0x01; // DLM=3D0, DLL=3D0x01 + *clk_sel_val =3D 0x40; // clock source =3D 12.923076922M + } else if (baudRate =3D=3D 921600) { + *divisor =3D 0x01; // DLM=3D0, DLL=3D0x01 + *clk_sel_val =3D 0x50; // clock source =3D 14.769230768M + } else if (baudRate =3D=3D 25000) { + *divisor =3D 0x78; // DLM=3D0, DLL=3D0x78 + *clk_sel_val =3D 0x70; // clock source=3D48M + } else if (baudRate =3D=3D 50000) { + *divisor =3D 0x3c; // DLM=3D0, DLL=3D0x3c + *clk_sel_val =3D 0x70; // clock source=3D48M + } else if (baudRate =3D=3D 75000) { + *divisor =3D 0x28; // DLM=3D0, DLL=3D0x28 + *clk_sel_val =3D 0x70; // clock source=3D48M + } else if (baudRate =3D=3D 100000) { + *divisor =3D 0x1e; // DLM=3D0, DLL=3D0x1e + *clk_sel_val =3D 0x70; // clock source=3D48M + } else if (baudRate =3D=3D 250000) { + *divisor =3D 0x0c; // DLM=3D0, DLL=3D0x0c + *clk_sel_val =3D 0x70; // clock source=3D48M + } else if (baudRate =3D=3D 300000) { + *divisor =3D 0x0a; // DLM=3D0, DLL=3D0x0a + *clk_sel_val =3D 0x70; // clock source=3D48M + } else if (baudRate =3D=3D 500000) { + *divisor =3D 0x06; // DLM=3D0, DLL=3D0x06 + *clk_sel_val =3D 0x70; // clock source=3D48M + } else if (baudRate =3D=3D 600000) { + *divisor =3D 0x05; // DLM=3D0, DLL=3D0x05 + *clk_sel_val =3D 0x70; // clock source=3D48M + } else if (baudRate =3D=3D 1000000) { + *divisor =3D 0x03; // DLM=3D0, DLL=3D0x03 + *clk_sel_val =3D 0x70; // clock source=3D48M + } else if (baudRate =3D=3D 3000000) { + *divisor =3D 0x01; // DLM=3D0, DLL=3D0x01 + *clk_sel_val =3D 0x70; // clock source=3D48M + + } else if (baudRate =3D=3D 1500000) { + *divisor =3D 0x01; // DLM=3D0, DLL=3D0x01 + *clk_sel_val =3D 0x60; // clock source=3D24M + + } else if (baudRate <=3D 115200) { *divisor =3D 115200 / baudRate; *clk_sel_val =3D 0x0; - } - if ((baudRate > 115200) && (baudRate <=3D 230400)) { + } else if ((baudRate > 115200) && (baudRate <=3D 230400)) { *divisor =3D 230400 / baudRate; *clk_sel_val =3D 0x10; } else if ((baudRate > 230400) && (baudRate <=3D 403200)) { @@ -1088,6 +1193,9 @@ static int mos7840_calc_baud_rate_divisor(struct usb_= serial_port *port, } else if ((baudRate > 1572864) && (baudRate <=3D 3145728)) { *divisor =3D 3145728 / baudRate; *clk_sel_val =3D 0x70; + } else { + dev_dbg(&port->dev, "func: %s -baudrate %d not supported.\n", __func__, = baudRate); + return -1; } return 0; } --=20 2.34.1 From nobody Mon Nov 25 21:40:33 2024 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A75541BD028; Thu, 24 Oct 2024 10:17:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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([2403:c300:5606:d914:fec1:9dc9:d21d:9b02]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e7f0bd376sm69782065ad.132.2024.10.24.03.17.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2024 03:17:42 -0700 (PDT) From: Tony Chung To: gregkh@linuxfoundation.org Cc: johan@kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Tony Chung Subject: [PATCH 3/3] driver: usb: serial: mos7840: add more baudrate options Date: Thu, 24 Oct 2024 18:09:05 +0800 Message-Id: <20241024100901.69883-4-tony467913@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241024100901.69883-1-tony467913@gmail.com> References: <20241024100901.69883-1-tony467913@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adds more baud rate options using 96M/30M/External clock sources. To use these clock sources, set through Clk_Select_Reg1 and Clk_Select_Reg2. Signed-off-by: Tony Chung --- drivers/usb/serial/mos7840.c | 156 ++++++++++++++++++++++++++++++++++- 1 file changed, 155 insertions(+), 1 deletion(-) diff --git a/drivers/usb/serial/mos7840.c b/drivers/usb/serial/mos7840.c index acc16737b..70ee4a638 100644 --- a/drivers/usb/serial/mos7840.c +++ b/drivers/usb/serial/mos7840.c @@ -1169,6 +1169,37 @@ static int mos7840_calc_baud_rate_divisor(struct usb= _serial_port *port, *divisor =3D 0x01; // DLM=3D0, DLL=3D0x01 *clk_sel_val =3D 0x60; // clock source=3D24M =20 + /* below are using 96M or 30M clock source + * will determine the clock source later + * in function mos7840_send_cmd_write_baud_rate + */ + } else if (baudRate =3D=3D 6000000) { + *divisor =3D 0x01; // DLM=3D0, DLL=3D0x01 + *clk_sel_val =3D 0x80; // DUMMY val, clock source =3D 96M + } else if (baudRate =3D=3D 2000000) { + *divisor =3D 0x03; // DLM=3D0, DLL=3D0x03 + *clk_sel_val =3D 0x80; // DUMMY val, clock source =3D 96M + } else if (baudRate =3D=3D 403200) { + *divisor =3D 0x0f; // DLM=3D0, DLL=3D0x0f + *clk_sel_val =3D 0x80; // DUMMY val, clock source =3D 96M + } else if (baudRate =3D=3D 225000) { + *divisor =3D 0x1b; // DLM=3D0, DLL=3D0x1b + *clk_sel_val =3D 0x80; // DUMMY val, clock source =3D 96M + } else if (baudRate =3D=3D 153600) { + *divisor =3D 0x27; // DLM=3D0, DLL=3D0x27 + *clk_sel_val =3D 0x80; // DUMMY val, clock source =3D 96M + + } else if (baudRate =3D=3D 10000) { + *divisor =3D 0xbb; // DLM=3D0, DLL=3D0xbb + *clk_sel_val =3D 0x80; // DUMMY val, clock source =3D 30M + } else if (baudRate =3D=3D 125000) { + *divisor =3D 0x0f; // DLM=3D0, DLL=3D0x0f + *clk_sel_val =3D 0x80; // DUMMY val, clock source =3D 30M + } else if (baudRate =3D=3D 625000) { + *divisor =3D 0x03; // DLM=3D0, DLL=3D0x03 + *clk_sel_val =3D 0x80; // DUMMY val, clock source =3D 30M + + } else if (baudRate <=3D 115200) { *divisor =3D 115200 / baudRate; *clk_sel_val =3D 0x0; @@ -1246,11 +1277,134 @@ static int mos7840_send_cmd_write_baud_rate(struct= moschip_port *mos7840_port, =20 } =20 - if (1) { /* baudRate <=3D 115200) */ + if (1) { clk_sel_val =3D 0x0; Data =3D 0x0; status =3D mos7840_calc_baud_rate_divisor(port, baudRate, &divisor, &clk_sel_val); + if (status < 0) { + dev_dbg(&port->dev, "%s failed in set_serial_baud\n", __func__); + return -1; + } + + /* Write clk_sel_val to SP_Reg or Clk_Select_Reg*/ + // check clk_sel_val before setting the clk_sel_val + if (clk_sel_val =3D=3D 0x80) { + // clk_sel_val is DUMMY value -> Write the corresponding value to Clk_Se= lect_Reg + // 0x01:30M, 0x02:96M, 0x05:External Clock + if (baudRate =3D=3D 125000 || baudRate =3D=3D 625000 || baudRate =3D=3D= 10000) { + clk_sel_val =3D 0x01; + } else if (baudRate =3D=3D 153600 || baudRate =3D=3D 225000 || baudRate= =3D=3D 403200 || + baudRate =3D=3D 2000000 || baudRate =3D=3D 6000000) { + clk_sel_val =3D 0x02; + } else { + clk_sel_val =3D 0x05; // externel clk for custom case. + } + + // needs to set clock source through + // Clk_Select_Reg1(offset 0x13) & Clk_Select_Reg2(offset 0x14) + // Clk_Select_Reg1 for port1,2 Clk_Select_Reg2 for port3,4 + if (mos7840_port->port_num <=3D 2) { + status =3D mos7840_get_reg_sync(port, CLOCK_SELECT_REG1, &Data); + if (status < 0) { + dev_dbg(&port->dev, "reading Clk_Select_Reg failed in set_serial_baud= \n"); + return -1; + } + if (mos7840_port->port_num =3D=3D 1) { + Data =3D (Data & 0xf8) | clk_sel_val; + status =3D + mos7840_set_reg_sync(port, CLOCK_SELECT_REG1, Data); + } else if (mos7840_port->port_num =3D=3D 2) { + Data =3D (Data & 0xc7) | (clk_sel_val<<3); + status =3D + mos7840_set_reg_sync(port, CLOCK_SELECT_REG1, Data); + } + if (status < 0) { + dev_dbg(&port->dev, "setting Clk_Select_Reg failed\n"); + return -1; + } + } else if (mos7840_port->port_num <=3D 4) { + status =3D mos7840_get_reg_sync(port, CLOCK_SELECT_REG2, &Data); + if (status < 0) { + dev_dbg(&port->dev, "reading Clk_Select_Reg failed in set_serial_baud= \n"); + return -1; + } + if (mos7840_port->port_num =3D=3D 3) { + Data =3D (Data & 0xf8) | clk_sel_val; + status =3D + mos7840_set_reg_sync(port, CLOCK_SELECT_REG2, Data); + } else if (mos7840_port->port_num =3D=3D 4) { + Data =3D (Data & 0xc7) | (clk_sel_val<<3); + status =3D + mos7840_set_reg_sync(port, CLOCK_SELECT_REG2, Data); + } + if (status < 0) { + dev_dbg(&port->dev, "setting Clk_Select_Reg failed\n"); + return -1; + } + } + } else { + // clk_sel_val is not DUMMY value -> Write the corresponding value to SP= _Reg + + /* First, needs to write default value to + * Clk_Select_Reg1(offset 0x13) & Clk_Select_Reg2(offset 0x14) + * Clk_Select_Reg1 for port1,2 Clk_Select_Reg2 for port3,4 + */ + if (mos7840_port->port_num <=3D 2) { + status =3D mos7840_get_reg_sync(port, CLOCK_SELECT_REG1, &Data); + if (status < 0) { + dev_dbg(&port->dev, "reading Clk_Select_Reg failed in set_serial_baud= \n"); + return -1; + } + if (mos7840_port->port_num =3D=3D 1) { + Data =3D (Data & 0xf8) | 0x00; + status =3D + mos7840_set_reg_sync(port, CLOCK_SELECT_REG1, Data); + } else if (mos7840_port->port_num =3D=3D 2) { + Data =3D (Data & 0xc7) | (0x00<<3); + status =3D + mos7840_set_reg_sync(port, CLOCK_SELECT_REG1, Data); + } + if (status < 0) { + dev_dbg(&port->dev, "setting Clk_Select_Reg failed\n"); + return -1; + } + } else if (mos7840_port->port_num <=3D 4) { + status =3D mos7840_get_reg_sync(port, CLOCK_SELECT_REG2, &Data); + if (status < 0) { + dev_dbg(&port->dev, "reading Clk_Select_Reg failed in set_serial_baud= \n"); + return -1; + } + if (mos7840_port->port_num =3D=3D 3) { + Data =3D (Data & 0xf8) | 0x00; + status =3D + mos7840_set_reg_sync(port, CLOCK_SELECT_REG2, Data); + } else if (mos7840_port->port_num =3D=3D 4) { + Data =3D (Data & 0xc7) | (0x00<<3); + status =3D + mos7840_set_reg_sync(port, CLOCK_SELECT_REG2, Data); + } + if (status < 0) { + dev_dbg(&port->dev, "setting Clk_Select_Reg failed\n"); + return -1; + } + } + // select clock source by writing clk_sel_val to SPx_Reg + status =3D mos7840_get_reg_sync(port, mos7840_port->SpRegOffset, + &Data); + if (status < 0) { + dev_dbg(&port->dev, "reading spreg failed in set_serial_baud\n"); + return -1; + } + Data =3D (Data & 0x8f) | clk_sel_val; + status =3D mos7840_set_reg_sync(port, mos7840_port->SpRegOffset, + Data); + if (status < 0) { + dev_dbg(&port->dev, "Writing spreg failed in set_serial_baud\n"); + return -1; + } + } + status =3D mos7840_get_reg_sync(port, mos7840_port->SpRegOffset, &Data); if (status < 0) { --=20 2.34.1