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charset="utf-8" The UART of SG2044 is modified version of the standard Synopsys DesignWare UART. The UART on SG2044 relys on the internal divisor and can not set right clock rate for the common bitrates. Add compatibles string for the Sophgo SG2044 uarts. Signed-off-by: Inochi Amaoto Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml= b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index c104bd8446cf..fc263e652280 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -54,6 +54,7 @@ properties: - rockchip,rk3588-uart - rockchip,rv1108-uart - rockchip,rv1126-uart + - sophgo,sg2044-uart - starfive,jh7100-hsuart - starfive,jh7100-uart - starfive,jh7110-uart --=20 2.47.0