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Date: Thu, 24 Oct 2024 14:21:01 +0800 Message-ID: <20241024062105.782330-2-inochiama@gmail.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241024062105.782330-1-inochiama@gmail.com> References: <20241024062105.782330-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Each vendor have an items entry of its own compatible, It is needless and can be merged as it share the same base "snps,dw-apb-uart" compatible. Merge the duplicate compatible entry into one item entry. Signed-off-by: Inochi Amaoto Suggested-by: Conor Dooley Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/serial/snps-dw-apb-uart.yaml | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml= b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index 4cdb0dcaccf3..c104bd8446cf 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -37,6 +37,8 @@ properties: - const: renesas,rzn1-uart - items: - enum: + - brcm,bcm11351-dw-apb-uart + - brcm,bcm21664-dw-apb-uart - rockchip,px30-uart - rockchip,rk1808-uart - rockchip,rk3036-uart @@ -52,14 +54,6 @@ properties: - rockchip,rk3588-uart - rockchip,rv1108-uart - rockchip,rv1126-uart - - const: snps,dw-apb-uart - - items: - - enum: - - brcm,bcm11351-dw-apb-uart - - brcm,bcm21664-dw-apb-uart - - const: snps,dw-apb-uart - - items: - - enum: - starfive,jh7100-hsuart - starfive,jh7100-uart - starfive,jh7110-uart --=20 2.47.0 From nobody Mon Nov 25 21:46:22 2024 Received: from mail-pg1-f169.google.com (mail-pg1-f169.google.com [209.85.215.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B9D9189BA3; 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Wed, 23 Oct 2024 23:21:34 -0700 (PDT) Received: from localhost ([121.250.214.124]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7eaeabb9009sm7980110a12.59.2024.10.23.23.21.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2024 23:21:33 -0700 (PDT) From: Inochi Amaoto To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Andy Shevchenko , Chen Wang , Inochi Amaoto Cc: Inochi Amaoto , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 2/3] dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2044 uarts Date: Thu, 24 Oct 2024 14:21:02 +0800 Message-ID: <20241024062105.782330-3-inochiama@gmail.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241024062105.782330-1-inochiama@gmail.com> References: <20241024062105.782330-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The UART of SG2044 is modified version of the standard Synopsys DesignWare UART. The UART on SG2044 relys on the internal divisor and can not set right clock rate for the common bitrates. Add compatibles string for the Sophgo SG2044 uarts. Signed-off-by: Inochi Amaoto Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml= b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index c104bd8446cf..fc263e652280 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -54,6 +54,7 @@ properties: - rockchip,rk3588-uart - rockchip,rv1108-uart - rockchip,rv1126-uart + - sophgo,sg2044-uart - starfive,jh7100-hsuart - starfive,jh7100-uart - starfive,jh7110-uart --=20 2.47.0 From nobody Mon Nov 25 21:46:22 2024 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61F62189F37; Thu, 24 Oct 2024 06:21:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 23 Oct 2024 23:21:36 -0700 (PDT) Received: from localhost ([121.250.214.124]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e7f0bd480sm66219025ad.130.2024.10.23.23.21.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2024 23:21:36 -0700 (PDT) From: Inochi Amaoto To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Andy Shevchenko , Chen Wang , Inochi Amaoto Cc: Inochi Amaoto , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 3/3] serial: 8250_dw: Add Sophgo SG2044 quirk Date: Thu, 24 Oct 2024 14:21:03 +0800 Message-ID: <20241024062105.782330-4-inochiama@gmail.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241024062105.782330-1-inochiama@gmail.com> References: <20241024062105.782330-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable SG2044 relys on an internal divisor when calculating bitrate, which means a wrong clock for the most common bitrates. So add a quirk for this uart device to skip the set rate call and only relys on the internal UART divisor. Reviewed-by: Andy Shevchenko Reviewed-by: Ilpo J=C3=A4rvinen Signed-off-by: Inochi Amaoto --- drivers/tty/serial/8250/8250_dw.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/82= 50_dw.c index ab9e7f204260..51894c93c8a3 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -750,7 +750,7 @@ static const struct dw8250_platform_data dw8250_renesas= _rzn1_data =3D { .quirks =3D DW_UART_QUIRK_CPR_VALUE | DW_UART_QUIRK_IS_DMA_FC, }; =20 -static const struct dw8250_platform_data dw8250_starfive_jh7100_data =3D { +static const struct dw8250_platform_data dw8250_skip_set_rate_data =3D { .usr_reg =3D DW_UART_USR, .quirks =3D DW_UART_QUIRK_SKIP_SET_RATE, }; @@ -760,7 +760,8 @@ static const struct of_device_id dw8250_of_match[] =3D { { .compatible =3D "cavium,octeon-3860-uart", .data =3D &dw8250_octeon_386= 0_data }, { .compatible =3D "marvell,armada-38x-uart", .data =3D &dw8250_armada_38x= _data }, { .compatible =3D "renesas,rzn1-uart", .data =3D &dw8250_renesas_rzn1_dat= a }, - { .compatible =3D "starfive,jh7100-uart", .data =3D &dw8250_starfive_jh71= 00_data }, + { .compatible =3D "sophgo,sg2044-uart", .data =3D &dw8250_skip_set_rate_d= ata }, + { .compatible =3D "starfive,jh7100-uart", .data =3D &dw8250_skip_set_rate= _data }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, dw8250_of_match); --=20 2.47.0