From nobody Fri Dec 19 17:36:11 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F04801FBC80; Wed, 23 Oct 2024 22:02:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729720960; cv=none; b=rpr2XPE/+2d+KChq88TWXKr6mA0XixYD9+Uv15+pZBdTkgHJJ7N2kEg5RbCivCUrdpOueIXhiIf9WCwJvhbVlEEpdFaNwJf32Dd6N4X5oJKzwokN05J/LZPXI9lncc+0N104NpGqQ7DdgY+1NEkQWCNob9s8RkAkK+f3zhygNVw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729720960; c=relaxed/simple; bh=J8qCXnNG/OAP9j8DsIe5XLMigohB45RpGMYrjnzBjeQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=IZWp8NuMF4jo82McKhRyBq3S1ZJI8cRhJaYieRTliLl5jHQF6HJByadqGweE+uRAwRSqSMgrYCDnjolbjPQLjvGdMN5/G4ZKLpMO3ajNYOIhqIArs2L52IjItUiKYPIRiCXk5zIeSioRL/KO4ViMJbHbZN08D65pUuPxwFhv4kQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=C9ACEB1i; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="C9ACEB1i" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1729720957; x=1761256957; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=J8qCXnNG/OAP9j8DsIe5XLMigohB45RpGMYrjnzBjeQ=; b=C9ACEB1iXMnayAXvOnjJu/wDgZlpH9AMLSdgVKuMqZIMBz8ulb7ygbo2 yihLRG+CGZyIuuFnbcUVQ1F7uTWBIgQFP6VZSNUbDM4LyRBSTf3UuUFNk mvYgmo3oUCP4hqpZ8VcQmnG6AGG+CrKhPIrDJQo25Hpm9+l/6MaV0xiAk 428ZBzopKNFcNEnZNKp/Wd23iyevy9qt0Sb5maDXHprZpizLQF+/DFIpx aOQSt18yG8/5r2XY+xCq04Z5O0nbPjIMx/EHwSIUNwUbAk81mamNUIVb0 WyoQIC5usl/db61zMsk+A7rth0ZfyfpFpKwA4qRPKQRZ7enGiyNQRjbvk w==; X-CSE-ConnectionGUID: wd8IJW4NTJ64cR86gqDN2Q== X-CSE-MsgGUID: pOvqRvkuSWyNcGFxl+BJxQ== X-IronPort-AV: E=Sophos;i="6.11,227,1725346800"; d="scan'208";a="200831268" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Oct 2024 15:02:36 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 23 Oct 2024 15:02:08 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 23 Oct 2024 15:02:04 -0700 From: Daniel Machon Date: Thu, 24 Oct 2024 00:01:26 +0200 Subject: [PATCH net-next v2 07/15] net: lan969x: add register diffs to match data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241024-sparx5-lan969x-switch-driver-2-v2-7-a0b5fae88a0f@microchip.com> References: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> In-Reply-To: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Lars Povlsen , Steen Hegelund , , , , , , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: , , , Steen Hegelund , X-Mailer: b4 0.14-dev Add new file lan969x_regs.c that defines all the register differences for lan969x, and add it to the lan969x match data. GW_DEV2G5_PHASE_DETECTOR_CTRL, FP_DEV2G5_PHAD_CTRL_PHAD_ENA and FP_DEV2G5_PHAD_CTRL_PHAD_FAILED are required by the new register macros which was introduced earlier. Add these for Sparx5 also. Reviewed-by: Steen Hegelund Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/lan969x/Makefile | 2 +- drivers/net/ethernet/microchip/lan969x/lan969x.c | 12 ++ drivers/net/ethernet/microchip/lan969x/lan969x.h | 11 + .../net/ethernet/microchip/lan969x/lan969x_regs.c | 222 +++++++++++++++++= ++++ .../net/ethernet/microchip/sparx5/sparx5_regs.c | 5 +- .../net/ethernet/microchip/sparx5/sparx5_regs.h | 5 +- 6 files changed, 254 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan969x/Makefile b/drivers/net/= ethernet/microchip/lan969x/Makefile index f3d9dfcd8c30..ff40e7e5d420 100644 --- a/drivers/net/ethernet/microchip/lan969x/Makefile +++ b/drivers/net/ethernet/microchip/lan969x/Makefile @@ -5,7 +5,7 @@ =20 obj-$(CONFIG_LAN969X_SWITCH) +=3D lan969x-switch.o =20 -lan969x-switch-y :=3D lan969x.o +lan969x-switch-y :=3D lan969x_regs.o lan969x.o =20 # Provide include files ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/microchip/fdma diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x.c b/drivers/net= /ethernet/microchip/lan969x/lan969x.c index 488af2a8ee3c..0b47e4e66058 100644 --- a/drivers/net/ethernet/microchip/lan969x/lan969x.c +++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c @@ -92,10 +92,22 @@ static const struct sparx5_main_io_resource lan969x_mai= n_iomap[] =3D { { TARGET_ASM, 0x3200000, 1 }, /* 0xe3200000 */ }; =20 +static const struct sparx5_regs lan969x_regs =3D { + .tsize =3D lan969x_tsize, + .gaddr =3D lan969x_gaddr, + .gcnt =3D lan969x_gcnt, + .gsize =3D lan969x_gsize, + .raddr =3D lan969x_raddr, + .rcnt =3D lan969x_rcnt, + .fpos =3D lan969x_fpos, + .fsize =3D lan969x_fsize, +}; + const struct sparx5_match_data lan969x_desc =3D { .iomap =3D lan969x_main_iomap, .iomap_size =3D ARRAY_SIZE(lan969x_main_iomap), .ioranges =3D 2, + .regs =3D &lan969x_regs, }; EXPORT_SYMBOL_GPL(lan969x_desc); =20 diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x.h b/drivers/net= /ethernet/microchip/lan969x/lan969x.h index 0507046ab9af..3b4c9ea30071 100644 --- a/drivers/net/ethernet/microchip/lan969x/lan969x.h +++ b/drivers/net/ethernet/microchip/lan969x/lan969x.h @@ -8,8 +8,19 @@ #define __LAN969X_H__ =20 #include "../sparx5/sparx5_main.h" +#include "../sparx5/sparx5_regs.h" =20 /* lan969x.c */ extern const struct sparx5_match_data lan969x_desc; =20 +/* lan969x_regs.c */ +extern const unsigned int lan969x_tsize[TSIZE_LAST]; +extern const unsigned int lan969x_raddr[RADDR_LAST]; +extern const unsigned int lan969x_rcnt[RCNT_LAST]; +extern const unsigned int lan969x_gaddr[GADDR_LAST]; +extern const unsigned int lan969x_gcnt[GCNT_LAST]; +extern const unsigned int lan969x_gsize[GSIZE_LAST]; +extern const unsigned int lan969x_fpos[FPOS_LAST]; +extern const unsigned int lan969x_fsize[FSIZE_LAST]; + #endif diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x_regs.c b/driver= s/net/ethernet/microchip/lan969x/lan969x_regs.c new file mode 100644 index 000000000000..ace4ba21eec4 --- /dev/null +++ b/drivers/net/ethernet/microchip/lan969x/lan969x_regs.c @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Microchip lan969x Switch driver + * + * Copyright (c) 2024 Microchip Technology Inc. + */ + +/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200. + * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b + */ + +#include "lan969x.h" + +const unsigned int lan969x_tsize[TSIZE_LAST] =3D { + [TC_DEV10G] =3D 10, + [TC_DEV2G5] =3D 28, + [TC_DEV5G] =3D 4, + [TC_PCS10G_BR] =3D 10, + [TC_PCS5G_BR] =3D 4, +}; + +const unsigned int lan969x_raddr[RADDR_LAST] =3D { + [RA_CPU_PROC_CTRL] =3D 160, + [RA_GCB_SOFT_RST] =3D 12, + [RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] =3D 20, +}; + +const unsigned int lan969x_rcnt[RCNT_LAST] =3D { + [RC_ANA_AC_OWN_UPSID] =3D 1, + [RC_ANA_ACL_VCAP_S2_CFG] =3D 35, + [RC_ANA_ACL_OWN_UPSID] =3D 1, + [RC_ANA_CL_OWN_UPSID] =3D 1, + [RC_ANA_L2_OWN_UPSID] =3D 1, + [RC_ASM_PORT_CFG] =3D 32, + [RC_DSM_BUF_CFG] =3D 32, + [RC_DSM_DEV_TX_STOP_WM_CFG] =3D 32, + [RC_DSM_RX_PAUSE_CFG] =3D 32, + [RC_DSM_MAC_CFG] =3D 32, + [RC_DSM_MAC_ADDR_BASE_HIGH_CFG] =3D 30, + [RC_DSM_MAC_ADDR_BASE_LOW_CFG] =3D 30, + [RC_DSM_TAXI_CAL_CFG] =3D 6, + [RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] =3D 30, + [RC_HSCH_PORT_MODE] =3D 35, + [RC_QFWD_SWITCH_PORT_MODE] =3D 35, + [RC_QSYS_PAUSE_CFG] =3D 35, + [RC_QSYS_ATOP] =3D 35, + [RC_QSYS_FWD_PRESSURE] =3D 35, + [RC_QSYS_CAL_AUTO] =3D 4, + [RC_REW_OWN_UPSID] =3D 1, + [RC_REW_RTAG_ETAG_CTRL] =3D 35, +}; + +const unsigned int lan969x_gaddr[GADDR_LAST] =3D { + [GA_ANA_AC_RAM_CTRL] =3D 202000, + [GA_ANA_AC_PS_COMMON] =3D 202880, + [GA_ANA_AC_MIRROR_PROBE] =3D 203232, + [GA_ANA_AC_SRC] =3D 201728, + [GA_ANA_AC_PGID] =3D 131072, + [GA_ANA_AC_TSN_SF] =3D 202028, + [GA_ANA_AC_TSN_SF_CFG] =3D 148480, + [GA_ANA_AC_TSN_SF_STATUS] =3D 147936, + [GA_ANA_AC_SG_ACCESS] =3D 202032, + [GA_ANA_AC_SG_CONFIG] =3D 202752, + [GA_ANA_AC_SG_STATUS] =3D 147952, + [GA_ANA_AC_SG_STATUS_STICKY] =3D 202044, + [GA_ANA_AC_STAT_GLOBAL_CFG_PORT] =3D 202048, + [GA_ANA_AC_STAT_CNT_CFG_PORT] =3D 204800, + [GA_ANA_AC_STAT_GLOBAL_CFG_ACL] =3D 202068, + [GA_ANA_ACL_COMMON] =3D 8192, + [GA_ANA_ACL_KEY_SEL] =3D 9204, + [GA_ANA_ACL_CNT_B] =3D 4096, + [GA_ANA_ACL_STICKY] =3D 10852, + [GA_ANA_AC_POL_POL_ALL_CFG] =3D 17504, + [GA_ANA_AC_POL_COMMON_BDLB] =3D 19464, + [GA_ANA_AC_POL_COMMON_BUM_SLB] =3D 19472, + [GA_ANA_AC_SDLB_LBGRP_TBL] =3D 31788, + [GA_ANA_CL_PORT] =3D 65536, + [GA_ANA_CL_COMMON] =3D 87040, + [GA_ANA_L2_COMMON] =3D 561928, + [GA_ANA_L3_COMMON] =3D 370752, + [GA_ANA_L3_VLAN_ARP_L3MC_STICKY] =3D 368580, + [GA_ASM_CFG] =3D 18304, + [GA_ASM_PFC_TIMER_CFG] =3D 15568, + [GA_ASM_LBK_WM_CFG] =3D 15596, + [GA_ASM_LBK_MISC_CFG] =3D 15608, + [GA_ASM_RAM_CTRL] =3D 15684, + [GA_EACL_ES2_KEY_SELECT_PROFILE] =3D 36864, + [GA_EACL_CNT_TBL] =3D 30720, + [GA_EACL_POL_CFG] =3D 38400, + [GA_EACL_ES2_STICKY] =3D 29072, + [GA_EACL_RAM_CTRL] =3D 29112, + [GA_GCB_SIO_CTRL] =3D 560, + [GA_HSCH_HSCH_DWRR] =3D 36480, + [GA_HSCH_HSCH_MISC] =3D 36608, + [GA_HSCH_HSCH_LEAK_LISTS] =3D 37256, + [GA_HSCH_SYSTEM] =3D 37384, + [GA_HSCH_MMGT] =3D 36260, + [GA_HSCH_TAS_CONFIG] =3D 37696, + [GA_PTP_PTP_CFG] =3D 512, + [GA_PTP_PTP_TOD_DOMAINS] =3D 528, + [GA_PTP_PHASE_DETECTOR_CTRL] =3D 628, + [GA_QSYS_CALCFG] =3D 2164, + [GA_QSYS_RAM_CTRL] =3D 2204, + [GA_REW_COMMON] =3D 98304, + [GA_REW_PORT] =3D 49152, + [GA_REW_VOE_PORT_LM_CNT] =3D 90112, + [GA_REW_RAM_CTRL] =3D 93992, + [GA_VOP_RAM_CTRL] =3D 16368, + [GA_XQS_SYSTEM] =3D 5744, + [GA_XQS_QLIMIT_SHR] =3D 6912, +}; + +const unsigned int lan969x_gcnt[GCNT_LAST] =3D { + [GC_ANA_AC_SRC] =3D 67, + [GC_ANA_AC_PGID] =3D 1054, + [GC_ANA_AC_TSN_SF_CFG] =3D 256, + [GC_ANA_AC_STAT_CNT_CFG_PORT] =3D 35, + [GC_ANA_ACL_KEY_SEL] =3D 99, + [GC_ANA_ACL_CNT_A] =3D 1024, + [GC_ANA_ACL_CNT_B] =3D 1024, + [GC_ANA_AC_SDLB_LBGRP_TBL] =3D 5, + [GC_ANA_AC_SDLB_LBSET_TBL] =3D 496, + [GC_ANA_CL_PORT] =3D 35, + [GC_ANA_L2_ISDX_LIMIT] =3D 256, + [GC_ANA_L2_ISDX] =3D 1024, + [GC_ANA_L3_VLAN] =3D 4608, + [GC_ASM_DEV_STATISTICS] =3D 30, + [GC_EACL_ES2_KEY_SELECT_PROFILE] =3D 68, + [GC_EACL_CNT_TBL] =3D 512, + [GC_GCB_SIO_CTRL] =3D 1, + [GC_HSCH_HSCH_CFG] =3D 1120, + [GC_HSCH_HSCH_DWRR] =3D 32, + [GC_PTP_PTP_PINS] =3D 8, + [GC_PTP_PHASE_DETECTOR_CTRL] =3D 8, + [GC_REW_PORT] =3D 35, + [GC_REW_VOE_PORT_LM_CNT] =3D 240, +}; + +const unsigned int lan969x_gsize[GSIZE_LAST] =3D { + [GW_ANA_AC_SRC] =3D 4, + [GW_ANA_L2_COMMON] =3D 712, + [GW_ASM_CFG] =3D 1092, + [GW_CPU_CPU_REGS] =3D 180, + [GW_DEV2G5_PHASE_DETECTOR_CTRL] =3D 12, + [GW_FDMA_FDMA] =3D 448, + [GW_GCB_CHIP_REGS] =3D 180, + [GW_HSCH_TAS_CONFIG] =3D 16, + [GW_PTP_PHASE_DETECTOR_CTRL] =3D 12, + [GW_QSYS_PAUSE_CFG] =3D 988, +}; + +const unsigned int lan969x_fpos[FPOS_LAST] =3D { + [FP_CPU_PROC_CTRL_AARCH64_MODE_ENA] =3D 7, + [FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS] =3D 6, + [FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS] =3D 5, + [FP_CPU_PROC_CTRL_BE_EXCEP_MODE] =3D 4, + [FP_CPU_PROC_CTRL_VINITHI] =3D 3, + [FP_CPU_PROC_CTRL_CFGTE] =3D 2, + [FP_CPU_PROC_CTRL_CP15S_DISABLE] =3D 1, + [FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] =3D 0, + [FP_CPU_PROC_CTRL_L2_FLUSH_REQ] =3D 8, + [FP_DEV2G5_PHAD_CTRL_PHAD_ENA] =3D 5, + [FP_DEV2G5_PHAD_CTRL_PHAD_FAILED] =3D 3, + [FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] =3D 5, + [FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] =3D 4, + [FP_FDMA_CH_CFG_CH_INJ_PORT] =3D 3, + [FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] =3D 27, + [FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] =3D 25, + [FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL] =3D 24, + [FP_PTP_PHAD_CTRL_PHAD_ENA] =3D 5, + [FP_PTP_PHAD_CTRL_PHAD_FAILED] =3D 3, +}; + +const unsigned int lan969x_fsize[FSIZE_LAST] =3D { + [FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK] =3D 30, + [FW_ANA_AC_SRC_CFG_PORT_MASK] =3D 30, + [FW_ANA_AC_PGID_CFG_PORT_MASK] =3D 30, + [FW_ANA_AC_TSN_SF_PORT_NUM] =3D 7, + [FW_ANA_AC_TSN_SF_CFG_TSN_SGID] =3D 8, + [FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] =3D 8, + [FW_ANA_AC_SG_ACCESS_CTRL_SGID] =3D 8, + [FW_ANA_AC_PORT_SGE_CFG_MASK] =3D 17, + [FW_ANA_AC_SDLB_XLB_START_LBSET_START] =3D 9, + [FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] =3D 3, + [FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] =3D 9, + [FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] =3D 9, + [FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] =3D 3, + [FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] =3D 9, + [FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA] =3D 30, + [FW_ANA_L2_DLB_CFG_DLB_IDX] =3D 9, + [FW_ANA_L2_TSN_CFG_TSN_SFID] =3D 8, + [FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK] =3D 30, + [FW_FDMA_CH_CFG_CH_DCB_DB_CNT] =3D 2, + [FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] =3D 7, + [FW_HSCH_SE_CFG_SE_DWRR_CNT] =3D 5, + [FW_HSCH_SE_CONNECT_SE_LEAK_LINK] =3D 14, + [FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] =3D 6, + [FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] =3D 11, + [FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] =3D 14, + [FW_HSCH_FLUSH_CTRL_FLUSH_PORT] =3D 6, + [FW_HSCH_FLUSH_CTRL_FLUSH_HIER] =3D 14, + [FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] =3D 13, + [FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] =3D 8, + [FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] =3D 13, + [FW_PTP_PTP_PIN_INTR_INTR_PTP] =3D 8, + [FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] =3D 8, + [FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] =3D 8, + [FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] =3D 3, + [FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] =3D 6, + [FW_QRES_RES_CFG_WM_HIGH] =3D 11, + [FW_QRES_RES_STAT_MAXUSE] =3D 19, + [FW_QRES_RES_STAT_CUR_INUSE] =3D 19, + [FW_QSYS_PAUSE_CFG_PAUSE_START] =3D 11, + [FW_QSYS_PAUSE_CFG_PAUSE_STOP] =3D 11, + [FW_QSYS_ATOP_ATOP] =3D 11, + [FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] =3D 11, + [FW_REW_RTAG_ETAG_CTRL_IPE_TBL] =3D 6, + [FW_XQS_STAT_CFG_STAT_VIEW] =3D 10, + [FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] =3D 14, + [FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] =3D 14, + [FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] =3D 14, + [FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] =3D 14, +}; diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_regs.c b/drivers/= net/ethernet/microchip/sparx5/sparx5_regs.c index 1db212ce3df7..220e81b714d4 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_regs.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_regs.c @@ -4,7 +4,7 @@ * Copyright (c) 2024 Microchip Technology Inc. */ =20 -/* This file is autogenerated by cml-utils 2024-09-24 14:02:24 +0200. +/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200. * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b */ =20 @@ -140,6 +140,7 @@ const unsigned int sparx5_gsize[GSIZE_LAST] =3D { [GW_ANA_L2_COMMON] =3D 700, [GW_ASM_CFG] =3D 1088, [GW_CPU_CPU_REGS] =3D 204, + [GW_DEV2G5_PHASE_DETECTOR_CTRL] =3D 8, [GW_FDMA_FDMA] =3D 428, [GW_GCB_CHIP_REGS] =3D 424, [GW_HSCH_TAS_CONFIG] =3D 12, @@ -157,6 +158,8 @@ const unsigned int sparx5_fpos[FPOS_LAST] =3D { [FP_CPU_PROC_CTRL_CP15S_DISABLE] =3D 6, [FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] =3D 5, [FP_CPU_PROC_CTRL_L2_FLUSH_REQ] =3D 1, + [FP_DEV2G5_PHAD_CTRL_PHAD_ENA] =3D 7, + [FP_DEV2G5_PHAD_CTRL_PHAD_FAILED] =3D 6, [FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] =3D 7, [FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] =3D 6, [FP_FDMA_CH_CFG_CH_INJ_PORT] =3D 5, diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_regs.h b/drivers/= net/ethernet/microchip/sparx5/sparx5_regs.h index c4e8b581c1f3..ea28130c2341 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_regs.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_regs.h @@ -4,7 +4,7 @@ * Copyright (c) 2024 Microchip Technology Inc. */ =20 -/* This file is autogenerated by cml-utils 2024-09-24 14:02:24 +0200. +/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200. * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b */ =20 @@ -151,6 +151,7 @@ enum sparx5_gsize_enum { GW_ANA_L2_COMMON, GW_ASM_CFG, GW_CPU_CPU_REGS, + GW_DEV2G5_PHASE_DETECTOR_CTRL, GW_FDMA_FDMA, GW_GCB_CHIP_REGS, GW_HSCH_TAS_CONFIG, @@ -169,6 +170,8 @@ enum sparx5_fpos_enum { FP_CPU_PROC_CTRL_CP15S_DISABLE, FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, FP_CPU_PROC_CTRL_L2_FLUSH_REQ, + FP_DEV2G5_PHAD_CTRL_PHAD_ENA, + FP_DEV2G5_PHAD_CTRL_PHAD_FAILED, FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE, FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, FP_FDMA_CH_CFG_CH_INJ_PORT, --=20 2.34.1