From nobody Tue Nov 26 00:43:08 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 953BB1FEFBA; Wed, 23 Oct 2024 22:02:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729720980; cv=none; b=cT5rl+AAajRfvrHoznynwzDXrMgsg788mrVSjIPZTcG/qxh8r8lOD9seULvKSYFxdzKIbQ93Q3U/4wGeQcqesrd3YIHVQMFqWi4TfLtkLAHgPbf2uSmmwrC0Xdcjnnb/uQInaZNMFTzZttgzaRjrKOFqN9q1tcdQRwNncdErjYU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729720980; c=relaxed/simple; bh=ALt5Jin6lko80fvAdgpJ8NqUlAgTrlAgzFK9GMWMi4s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=nnn/eakOnExHZ2yz9AAxbDEK0z0SpFKbqfdk2q4uDpr3SGjP7vLAM4B7wvFtOLF4vQBUeWsLO2/nOdEGk5sFy+0OcOZoCFTSlfvPLaq8T//S/x8Hbkao+TaP0mqJRUY39nWlSLrMVLuuOKk4fivK7UskFeT82C7jZa/YBJz7XZE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=lH3Dm8J0; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="lH3Dm8J0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1729720977; x=1761256977; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=ALt5Jin6lko80fvAdgpJ8NqUlAgTrlAgzFK9GMWMi4s=; b=lH3Dm8J0iCxQEn89bU0Oax9ovyhO2CS0oavu2KmY6tR2BiQvHv+4Z2os IfoFlU00kuHxSe+rxHRPiOXSa46AbOKGhV3ATP7/Cl+LbIJb3hml0+rvR b69lb5fXDib+mfPBRkQG4oMiXGal7T65m7GXJZjTTuBHJ+IcY3S3l7uyC RWj6726MmzSeqPBX7GvBVbaOaTampWQJFRXOx10dB95RItxzWgxew8zde YE1b1Kod2t0GvE4AiHTFimdQUZUSlOHMKESoUxjirY/qVbzpRqvZuSz6h lptb34MYBz0WefnnO+JyMqui/k44Kv/B5+NMSoObDTP1uOsfa2j0T+B63 Q==; X-CSE-ConnectionGUID: oMPErp9qRFmiMc0P9W4Bgw== X-CSE-MsgGUID: JoEFOq/hRbaehMbIrrjw7A== X-IronPort-AV: E=Sophos;i="6.11,227,1725346800"; d="scan'208";a="264507058" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Oct 2024 15:02:56 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 23 Oct 2024 15:02:29 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 23 Oct 2024 15:02:25 -0700 From: Daniel Machon Date: Thu, 24 Oct 2024 00:01:31 +0200 Subject: [PATCH net-next v2 12/15] net: sparx5: use is_sparx5() macro throughout Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241024-sparx5-lan969x-switch-driver-2-v2-12-a0b5fae88a0f@microchip.com> References: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> In-Reply-To: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Lars Povlsen , Steen Hegelund , , , , , , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: , , , Steen Hegelund , X-Mailer: b4 0.14-dev Use the is_sparx5() macro (introduced in earlier series [1]), in places where we need to handle things a bit differently on lan969x. These places are: - in sparx5_dsm_calendar_update() we need to switch the calendar from a to b on lan969x. - in sparx5_start() we need to make sure the HSCH_SYS_CLK_PER register is only touched on Sparx5. - in sparx5_start() we need to disable VCAP and FDMA for lan969x (will come in later series). - in sparx5_mirror_port_get() we must make sure the ANA_AC_PROBE_PORT_CFG1 register is only read on Sparx5. - sparx5_netdev.c and sparx5_packet.c we need to use different IFH (Internal Frame Header) offsets for lan969x. - in sparx5_port_fifo_sz() we must bail out on lan969x. - in sparx5_port_config_low_set() we must configure the phase detection registers. - in sparx5_port_config() and sparx5_port_init() we must do some additional configuration of the port devices. - in sparx5_dwrr_conf_set() we must derive the scheduling layer [1] https://lore.kernel.org/netdev/20241004-b4-sparx5-lan969x-switch-driver= -v2-8-d3290f581663@microchip.com/ Reviewed-by: Steen Hegelund Signed-off-by: Daniel Machon --- .../ethernet/microchip/sparx5/sparx5_calendar.c | 21 +++++++++- .../net/ethernet/microchip/sparx5/sparx5_main.c | 21 +++++----- .../net/ethernet/microchip/sparx5/sparx5_mirror.c | 10 ++++- .../net/ethernet/microchip/sparx5/sparx5_netdev.c | 17 ++++---- .../net/ethernet/microchip/sparx5/sparx5_packet.c | 3 +- .../net/ethernet/microchip/sparx5/sparx5_port.c | 46 ++++++++++++++++++= ++++ drivers/net/ethernet/microchip/sparx5/sparx5_qos.c | 3 +- 7 files changed, 99 insertions(+), 22 deletions(-) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c b/driv= ers/net/ethernet/microchip/sparx5/sparx5_calendar.c index 64c5ed70cc6b..5fe941c66c17 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c @@ -531,8 +531,18 @@ static int sparx5_dsm_calendar_check(struct sparx5 *sp= arx5, static int sparx5_dsm_calendar_update(struct sparx5 *sparx5, u32 taxi, struct sparx5_calendar_data *data) { - u32 idx; - u32 cal_len =3D sparx5_dsm_cal_len(data->schedule), len; + u32 cal_len =3D sparx5_dsm_cal_len(data->schedule), len, idx; + + if (!is_sparx5(sparx5)) { + u32 val, act; + + val =3D spx5_rd(sparx5, DSM_TAXI_CAL_CFG(taxi)); + act =3D DSM_TAXI_CAL_CFG_CAL_SEL_STAT_GET(val); + + spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_SEL_SET(!act), + DSM_TAXI_CAL_CFG_CAL_PGM_SEL, + sparx5, DSM_TAXI_CAL_CFG(taxi)); + } =20 spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(1), DSM_TAXI_CAL_CFG_CAL_PGM_ENA, @@ -556,6 +566,13 @@ static int sparx5_dsm_calendar_update(struct sparx5 *s= parx5, u32 taxi, DSM_TAXI_CAL_CFG(taxi))); if (len !=3D cal_len - 1) goto update_err; + + if (!is_sparx5(sparx5)) { + spx5_rmw(DSM_TAXI_CAL_CFG_CAL_SWITCH_SET(1), + DSM_TAXI_CAL_CFG_CAL_SWITCH, + sparx5, DSM_TAXI_CAL_CFG(taxi)); + } + return 0; update_err: dev_err(sparx5->dev, "Incorrect calendar length: %u\n", len); diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c b/drivers/= net/ethernet/microchip/sparx5/sparx5_main.c index 9da755c8b894..741404ccd8f5 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c @@ -538,10 +538,11 @@ static int sparx5_init_coreclock(struct sparx5 *sparx= 5) sparx5->coreclock =3D freq; clk_period =3D sparx5_clk_period(freq); =20 - spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100), - HSCH_SYS_CLK_PER_100PS, - sparx5, - HSCH_SYS_CLK_PER); + if (is_sparx5(sparx5)) + spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100), + HSCH_SYS_CLK_PER_100PS, + sparx5, + HSCH_SYS_CLK_PER); =20 spx5_rmw(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, @@ -731,15 +732,17 @@ static int sparx5_start(struct sparx5 *sparx5) if (err) return err; =20 - err =3D sparx5_vcap_init(sparx5); - if (err) { - sparx5_unregister_notifier_blocks(sparx5); - return err; + if (is_sparx5(sparx5)) { + err =3D sparx5_vcap_init(sparx5); + if (err) { + sparx5_unregister_notifier_blocks(sparx5); + return err; + } } =20 /* Start Frame DMA with fallback to register based INJ/XTR */ err =3D -ENXIO; - if (sparx5->fdma_irq >=3D 0) { + if (sparx5->fdma_irq >=3D 0 && is_sparx5(sparx5)) { if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0) err =3D devm_request_threaded_irq(sparx5->dev, sparx5->fdma_irq, diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c b/driver= s/net/ethernet/microchip/sparx5/sparx5_mirror.c index 459a53676ae9..9806729e9c62 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c @@ -24,8 +24,14 @@ static u32 sparx5_mirror_to_dir(bool ingress) /* Get ports belonging to this mirror */ static u64 sparx5_mirror_port_get(struct sparx5 *sparx5, u32 idx) { - return (u64)spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG1(idx)) << 32 | - spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG(idx)); + u64 val; + + val =3D spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG(idx)); + + if (is_sparx5(sparx5)) + val |=3D (u64)spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG1(idx)) << 32; + + return val; } =20 /* Add port to mirror (only front ports) */ diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c b/driver= s/net/ethernet/microchip/sparx5/sparx5_netdev.c index a94d9a540bd3..1d34af78166a 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c @@ -64,16 +64,16 @@ void sparx5_set_port_ifh(struct sparx5 *sparx5, void *i= fh_hdr, u16 portno) /* MISC.CPU_MASK/DPORT =3D Destination port */ ifh_encode_bitfield(ifh_hdr, portno, 29, 8); /* MISC.PIPELINE_PT */ - ifh_encode_bitfield(ifh_hdr, 16, 37, 5); + ifh_encode_bitfield(ifh_hdr, is_sparx5(sparx5) ? 16 : 17, 37, 5); /* MISC.PIPELINE_ACT */ ifh_encode_bitfield(ifh_hdr, 1, 42, 3); /* FWD.SRC_PORT =3D CPU */ ifh_encode_bitfield(ifh_hdr, sparx5_get_pgid(sparx5, SPX5_PORT_CPU_0), - 46, 7); + 46, is_sparx5(sparx5) ? 7 : 6); /* FWD.SFLOW_ID (disable SFlow sampling) */ - ifh_encode_bitfield(ifh_hdr, 124, 57, 7); + ifh_encode_bitfield(ifh_hdr, 124, is_sparx5(sparx5) ? 57 : 56, 7); /* FWD.UPDATE_FCS =3D Enable. Enforce update of FCS. */ - ifh_encode_bitfield(ifh_hdr, 1, 67, 1); + ifh_encode_bitfield(ifh_hdr, 1, is_sparx5(sparx5) ? 67 : 66, 1); } =20 void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op) @@ -84,19 +84,22 @@ void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_= op) void sparx5_set_port_ifh_pdu_type(struct sparx5 *sparx5, void *ifh_hdr, u32 pdu_type) { - ifh_encode_bitfield(ifh_hdr, pdu_type, 191, 4); + ifh_encode_bitfield(ifh_hdr, pdu_type, is_sparx5(sparx5) ? 191 : 190, + 4); } =20 void sparx5_set_port_ifh_pdu_w16_offset(struct sparx5 *sparx5, void *ifh_h= dr, u32 pdu_w16_offset) { - ifh_encode_bitfield(ifh_hdr, pdu_w16_offset, 195, 6); + ifh_encode_bitfield(ifh_hdr, pdu_w16_offset, + is_sparx5(sparx5) ? 195 : 194, 6); } =20 void sparx5_set_port_ifh_timestamp(struct sparx5 *sparx5, void *ifh_hdr, u64 timestamp) { - ifh_encode_bitfield(ifh_hdr, timestamp, 232, 40); + ifh_encode_bitfield(ifh_hdr, timestamp, 232, + is_sparx5(sparx5) ? 40 : 38); } =20 static int sparx5_port_open(struct net_device *ndev) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c b/driver= s/net/ethernet/microchip/sparx5/sparx5_packet.c index 57fa9ff9dfce..b6f635d85820 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c @@ -43,7 +43,8 @@ void sparx5_ifh_parse(struct sparx5 *sparx5, u32 *ifh, st= ruct frame_info *info) ((u32)xtr_hdr[29] << 8) | ((u32)xtr_hdr[30] << 0); fwd =3D (fwd >> 5); - info->src_port =3D FIELD_GET(GENMASK(7, 1), fwd); + info->src_port =3D spx5_field_get(GENMASK(is_sparx5(sparx5) ? 7 : 6, 1), + fwd); =20 /* * Bit 270-271 are occasionally unexpectedly set by the hardware, diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c b/drivers/= net/ethernet/microchip/sparx5/sparx5_port.c index 0b38b4cb0929..1401761c6251 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c @@ -476,6 +476,9 @@ static int sparx5_port_fifo_sz(struct sparx5 *sparx5, u32 mac_width =3D 8; u32 addition =3D 0; =20 + if (!is_sparx5(sparx5)) + return 0; + switch (speed) { case SPEED_25000: return 0; @@ -921,6 +924,20 @@ static int sparx5_port_config_low_set(struct sparx5 *s= parx5, sparx5, DEV2G5_DEV_RST_CTRL(port->portno)); =20 + /* Enable PHAD_CTRL for better timestamping */ + if (!is_sparx5(sparx5)) { + for (int i =3D 0; i < 2; ++i) { + /* Divide the port clock by three for the two + * phase detection registers. + */ + spx5_rmw(DEV2G5_PHAD_CTRL_DIV_CFG_SET(3) | + DEV2G5_PHAD_CTRL_PHAD_ENA_SET(1), + DEV2G5_PHAD_CTRL_DIV_CFG | + DEV2G5_PHAD_CTRL_PHAD_ENA, + sparx5, DEV2G5_PHAD_CTRL(port->portno, i)); + } + } + return 0; } =20 @@ -978,6 +995,7 @@ int sparx5_port_config(struct sparx5 *sparx5, struct sparx5_port_config *conf) { bool high_speed_dev =3D sparx5_is_baser(conf->portmode); + const struct sparx5_ops *ops =3D sparx5->data->ops; int err, urgency, stop_wm; =20 err =3D sparx5_port_verify_speed(sparx5, port, conf); @@ -993,6 +1011,13 @@ int sparx5_port_config(struct sparx5 *sparx5, if (err) return err; =20 + if (!is_sparx5(sparx5) && ops->is_port_10g(port->portno) && + conf->speed < SPEED_10000) + spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(1), + DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, + sparx5, + DSM_DEV_TX_STOP_WM_CFG(port->portno)); + /* Set the DSM stop watermark */ stop_wm =3D sparx5_port_fifo_sz(sparx5, port->portno, conf->speed); spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(stop_wm), @@ -1144,6 +1169,27 @@ int sparx5_port_init(struct sparx5 *sparx5, DEV25G_PCS25G_SD_CFG(pix)); } =20 + if (!is_sparx5(sparx5)) { + void __iomem *inst; + u32 dev, tinst; + + if (ops->is_port_10g(port->portno)) { + dev =3D sparx5_to_high_dev(sparx5, port->portno); + tinst =3D sparx5_port_dev_index(sparx5, port->portno); + inst =3D spx5_inst_get(sparx5, dev, tinst); + + spx5_inst_wr(5, inst, + DEV10G_PTP_STAMPER_CFG(port->portno)); + } else if (ops->is_port_5g(port->portno)) { + dev =3D sparx5_to_high_dev(sparx5, port->portno); + tinst =3D sparx5_port_dev_index(sparx5, port->portno); + inst =3D spx5_inst_get(sparx5, dev, tinst); + + spx5_inst_wr(5, inst, + DEV5G_PTP_STAMPER_CFG(port->portno)); + } + } + return 0; } =20 diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_qos.c b/drivers/n= et/ethernet/microchip/sparx5/sparx5_qos.c index d065f8c40d37..e580670f3992 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_qos.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_qos.c @@ -367,9 +367,10 @@ static u32 sparx5_weight_to_hw_cost(u32 weight_min, u3= 2 weight) static int sparx5_dwrr_conf_set(struct sparx5_port *port, struct sparx5_dwrr *dwrr) { + u32 layer =3D is_sparx5(port->sparx5) ? 2 : 1; int i; =20 - spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(2) | + spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(layer) | HSCH_HSCH_CFG_CFG_CFG_SE_IDX_SET(port->portno), HSCH_HSCH_CFG_CFG_HSCH_LAYER | HSCH_HSCH_CFG_CFG_CFG_SE_IDX, port->sparx5, HSCH_HSCH_CFG_CFG); --=20 2.34.1