From nobody Mon Nov 25 22:51:56 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 429FE1E00A2; Wed, 23 Oct 2024 22:02:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729720926; cv=none; b=icixI+Q6k1SMVSx/5Zroov0IX+9p+OYFdaPUY3OMeuJum3bCikFs3k7C2nRNc9Bcg3jqaMU8Umr9ABPXAgymXDJB2tV6kz+tyAfh9k1RAvY2ZoJzbM3ojhFSLyZPHP/WVQkoMhId0HQ+8/OBR9EppTu7nupmFJmQy7Sy9ClDrzg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729720926; c=relaxed/simple; bh=MuJJ4LlvyejvlG7OuIrz3VoNCIapqHE4HSNFdd4Yb14=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=gSJiGewb7Vd2w/lg7N9ooJIAq36MNb86aA56jRED3DKY/IHghVbdnoVzS0gtBp8nCtRhjcfRRd0OYsMXhN7D1/+xmjqlk0o+v4pfy0IsnlSfjF1d0z/SADB2LV4PnDDd9hIl3ctmvSTVMktAgP3mt+bLAxFYDzsn0FJI3QCeNKA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=t8OWidNw; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="t8OWidNw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1729720924; x=1761256924; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=MuJJ4LlvyejvlG7OuIrz3VoNCIapqHE4HSNFdd4Yb14=; b=t8OWidNwdyZCgq6t7H5iczqOMha0jmovI1q1kZzlMDqG8Es2IAFpMEiP qc8DjXlSveEYIWaLjqqTmHJJ9xMuGyjmSuzA1S9O4QWRbRHJ+WllyFGBh VE1934GlVWN8kpaTZ3A9IUMe3P0KiVJET44M/kucv0Kr+IhP/U5AEeBBc NlBGSVi5PZrmvkMFH4KSOiTz30M+Hfn92Js52CKOMI+1qlxkSwZB0ATJT K2pnPeR/Zf/LpZWhBuhxI+VJ9jUjkR7AvwY36nPtH03R/NmctINYSGZDI 7WKM7OTm+qPCBp0f2L0pLJ0KRsSgxQ5BsPzbdGtXv7m0wR0ZtI85c+pOn Q==; X-CSE-ConnectionGUID: 1Xapdzk8QAqz3uJYdYtrIg== X-CSE-MsgGUID: lG8inuBvTbidbLV9WE2aLQ== X-IronPort-AV: E=Sophos;i="6.11,227,1725346800"; d="scan'208";a="33409628" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Oct 2024 15:02:03 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 23 Oct 2024 15:01:42 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 23 Oct 2024 15:01:38 -0700 From: Daniel Machon Date: Thu, 24 Oct 2024 00:01:20 +0200 Subject: [PATCH net-next v2 01/15] net: sparx5: add support for lan969x targets and core clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241024-sparx5-lan969x-switch-driver-2-v2-1-a0b5fae88a0f@microchip.com> References: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> In-Reply-To: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Lars Povlsen , Steen Hegelund , , , , , , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: , , , Steen Hegelund , X-Mailer: b4 0.14-dev In preparation for lan969x, add lan969x targets to sparx5_target_chiptype and set the core clock frequency for these throughout. Lan969x only supports a core clock frequency of 328MHz. Also, set the policer update internal (pol_upd_int) matching the 328 MHz frequency of the lan969x targets. Reviewed-by: Steen Hegelund Signed-off-by: Daniel Machon --- .../ethernet/microchip/sparx5/sparx5_calendar.c | 17 +++++++++++ .../net/ethernet/microchip/sparx5/sparx5_main.c | 16 ++++++++++ .../net/ethernet/microchip/sparx5/sparx5_main.h | 35 +++++++++++++++---= ---- drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c | 6 ++++ 4 files changed, 64 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c b/driv= ers/net/ethernet/microchip/sparx5/sparx5_calendar.c index b2a8d04ab509..1ae56194637f 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c @@ -53,6 +53,22 @@ static u32 sparx5_target_bandwidth(struct sparx5 *sparx5) case SPX5_TARGET_CT_7558: case SPX5_TARGET_CT_7558TSN: return 201000; + case SPX5_TARGET_CT_LAN9691VAO: + return 46000; + case SPX5_TARGET_CT_LAN9694RED: + case SPX5_TARGET_CT_LAN9694TSN: + case SPX5_TARGET_CT_LAN9694: + return 68000; + case SPX5_TARGET_CT_LAN9696RED: + case SPX5_TARGET_CT_LAN9696TSN: + case SPX5_TARGET_CT_LAN9692VAO: + case SPX5_TARGET_CT_LAN9696: + return 88000; + case SPX5_TARGET_CT_LAN9698RED: + case SPX5_TARGET_CT_LAN9698TSN: + case SPX5_TARGET_CT_LAN9693VAO: + case SPX5_TARGET_CT_LAN9698: + return 101000; default: return 0; } @@ -74,6 +90,7 @@ static u32 sparx5_clk_to_bandwidth(enum sparx5_core_clock= freq cclock) { switch (cclock) { case SPX5_CORE_CLOCK_250MHZ: return 83000; /* 250000 / 3 */ + case SPX5_CORE_CLOCK_328MHZ: return 109375; /* 328000 / 3 */ case SPX5_CORE_CLOCK_500MHZ: return 166000; /* 500000 / 3 */ case SPX5_CORE_CLOCK_625MHZ: return 208000; /* 625000 / 3 */ default: return 0; diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c b/drivers/= net/ethernet/microchip/sparx5/sparx5_main.c index d1e9bc030c80..9da755c8b894 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c @@ -475,6 +475,20 @@ static int sparx5_init_coreclock(struct sparx5 *sparx5) else if (sparx5->coreclock =3D=3D SPX5_CORE_CLOCK_250MHZ) freq =3D 0; /* Not supported */ break; + case SPX5_TARGET_CT_LAN9694: + case SPX5_TARGET_CT_LAN9691VAO: + case SPX5_TARGET_CT_LAN9694TSN: + case SPX5_TARGET_CT_LAN9694RED: + case SPX5_TARGET_CT_LAN9696: + case SPX5_TARGET_CT_LAN9692VAO: + case SPX5_TARGET_CT_LAN9696TSN: + case SPX5_TARGET_CT_LAN9696RED: + case SPX5_TARGET_CT_LAN9698: + case SPX5_TARGET_CT_LAN9693VAO: + case SPX5_TARGET_CT_LAN9698TSN: + case SPX5_TARGET_CT_LAN9698RED: + freq =3D SPX5_CORE_CLOCK_328MHZ; + break; default: dev_err(sparx5->dev, "Target (%#04x) not supported\n", sparx5->target_ct); @@ -516,6 +530,8 @@ static int sparx5_init_coreclock(struct sparx5 *sparx5) CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA | CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, sparx5, CLKGEN_LCPLL1_CORE_CLK_CFG); + } else { + pol_upd_int =3D 820; // SPX5_CORE_CLOCK_328MHZ } =20 /* Update state with chosen frequency */ diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h b/drivers/= net/ethernet/microchip/sparx5/sparx5_main.h index 364ae92969bc..f117cf65cf8c 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h @@ -26,16 +26,28 @@ =20 /* Target chip type */ enum spx5_target_chiptype { - SPX5_TARGET_CT_7546 =3D 0x7546, /* SparX-5-64 Enterprise */ - SPX5_TARGET_CT_7549 =3D 0x7549, /* SparX-5-90 Enterprise */ - SPX5_TARGET_CT_7552 =3D 0x7552, /* SparX-5-128 Enterprise */ - SPX5_TARGET_CT_7556 =3D 0x7556, /* SparX-5-160 Enterprise */ - SPX5_TARGET_CT_7558 =3D 0x7558, /* SparX-5-200 Enterprise */ - SPX5_TARGET_CT_7546TSN =3D 0x47546, /* SparX-5-64i Industrial */ - SPX5_TARGET_CT_7549TSN =3D 0x47549, /* SparX-5-90i Industrial */ - SPX5_TARGET_CT_7552TSN =3D 0x47552, /* SparX-5-128i Industrial */ - SPX5_TARGET_CT_7556TSN =3D 0x47556, /* SparX-5-160i Industrial */ - SPX5_TARGET_CT_7558TSN =3D 0x47558, /* SparX-5-200i Industrial */ + SPX5_TARGET_CT_7546 =3D 0x7546, /* SparX-5-64 Enterprise */ + SPX5_TARGET_CT_7549 =3D 0x7549, /* SparX-5-90 Enterprise */ + SPX5_TARGET_CT_7552 =3D 0x7552, /* SparX-5-128 Enterprise */ + SPX5_TARGET_CT_7556 =3D 0x7556, /* SparX-5-160 Enterprise */ + SPX5_TARGET_CT_7558 =3D 0x7558, /* SparX-5-200 Enterprise */ + SPX5_TARGET_CT_7546TSN =3D 0x47546, /* SparX-5-64i Industrial */ + SPX5_TARGET_CT_7549TSN =3D 0x47549, /* SparX-5-90i Industrial */ + SPX5_TARGET_CT_7552TSN =3D 0x47552, /* SparX-5-128i Industrial */ + SPX5_TARGET_CT_7556TSN =3D 0x47556, /* SparX-5-160i Industrial */ + SPX5_TARGET_CT_7558TSN =3D 0x47558, /* SparX-5-200i Industrial */ + SPX5_TARGET_CT_LAN9694 =3D 0x9694, /* lan969x-40 */ + SPX5_TARGET_CT_LAN9691VAO =3D 0x9691, /* lan969x-40-VAO */ + SPX5_TARGET_CT_LAN9694TSN =3D 0x9695, /* lan969x-40-TSN */ + SPX5_TARGET_CT_LAN9694RED =3D 0x969A, /* lan969x-40-RED */ + SPX5_TARGET_CT_LAN9696 =3D 0x9696, /* lan969x-60 */ + SPX5_TARGET_CT_LAN9692VAO =3D 0x9692, /* lan969x-65-VAO */ + SPX5_TARGET_CT_LAN9696TSN =3D 0x9697, /* lan969x-60-TSN */ + SPX5_TARGET_CT_LAN9696RED =3D 0x969B, /* lan969x-60-RED */ + SPX5_TARGET_CT_LAN9698 =3D 0x9698, /* lan969x-100 */ + SPX5_TARGET_CT_LAN9693VAO =3D 0x9693, /* lan969x-100-VAO */ + SPX5_TARGET_CT_LAN9698TSN =3D 0x9699, /* lan969x-100-TSN */ + SPX5_TARGET_CT_LAN9698RED =3D 0x969C, /* lan969x-100-RED */ }; =20 enum sparx5_port_max_tags { @@ -192,6 +204,7 @@ struct sparx5_port { enum sparx5_core_clockfreq { SPX5_CORE_CLOCK_DEFAULT, /* Defaults to the highest supported frequency = */ SPX5_CORE_CLOCK_250MHZ, /* 250MHZ core clock frequency */ + SPX5_CORE_CLOCK_328MHZ, /* 328MHZ core clock frequency */ SPX5_CORE_CLOCK_500MHZ, /* 500MHZ core clock frequency */ SPX5_CORE_CLOCK_625MHZ, /* 625MHZ core clock frequency */ }; @@ -641,6 +654,8 @@ static inline u32 sparx5_clk_period(enum sparx5_core_cl= ockfreq cclock) switch (cclock) { case SPX5_CORE_CLOCK_250MHZ: return 4000; + case SPX5_CORE_CLOCK_328MHZ: + return 3048; case SPX5_CORE_CLOCK_500MHZ: return 2000; case SPX5_CORE_CLOCK_625MHZ: diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c b/drivers/n= et/ethernet/microchip/sparx5/sparx5_ptp.c index 9b15e44f9e64..a511f14312f1 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c @@ -38,6 +38,9 @@ static u64 sparx5_ptp_get_1ppm(struct sparx5 *sparx5) case SPX5_CORE_CLOCK_250MHZ: res =3D 2301339409586; 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Wed, 23 Oct 2024 15:01:47 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 23 Oct 2024 15:01:43 -0700 From: Daniel Machon Date: Thu, 24 Oct 2024 00:01:21 +0200 Subject: [PATCH net-next v2 02/15] net: sparx5: change spx5_wr to spx5_rmw in cal update() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241024-sparx5-lan969x-switch-driver-2-v2-2-a0b5fae88a0f@microchip.com> References: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> In-Reply-To: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Lars Povlsen , Steen Hegelund , , , , , , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: , , , Steen Hegelund , X-Mailer: b4 0.14-dev In preparation for lan969x, use spx5_rmw() for enabling the update of the calendar. This is required to not overwrite the DSM_TAXI_CAL_CFG register, as an additional write will be added before this one, in a subsequent patch. Reviewed-by: Steen Hegelund Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c b/driv= ers/net/ethernet/microchip/sparx5/sparx5_calendar.c index 1ae56194637f..edc03b6ebf34 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c @@ -546,9 +546,10 @@ static int sparx5_dsm_calendar_update(struct sparx5 *s= parx5, u32 taxi, u32 idx; u32 cal_len =3D sparx5_dsm_cal_len(data->schedule), len; =20 - spx5_wr(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(1), - sparx5, - DSM_TAXI_CAL_CFG(taxi)); + spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(1), + DSM_TAXI_CAL_CFG_CAL_PGM_ENA, + sparx5, + DSM_TAXI_CAL_CFG(taxi)); for (idx =3D 0; idx < cal_len; idx++) { spx5_rmw(DSM_TAXI_CAL_CFG_CAL_IDX_SET(idx), DSM_TAXI_CAL_CFG_CAL_IDX, @@ -559,9 +560,10 @@ static int sparx5_dsm_calendar_update(struct sparx5 *s= parx5, u32 taxi, sparx5, DSM_TAXI_CAL_CFG(taxi)); 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Wed, 23 Oct 2024 15:01:51 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 23 Oct 2024 15:01:47 -0700 From: Daniel Machon Date: Thu, 24 Oct 2024 00:01:22 +0200 Subject: [PATCH net-next v2 03/15] net: sparx5: change frequency calculation for SDLB's Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241024-sparx5-lan969x-switch-driver-2-v2-3-a0b5fae88a0f@microchip.com> References: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> In-Reply-To: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Lars Povlsen , Steen Hegelund , , , , , , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: , , , Steen Hegelund , X-Mailer: b4 0.14-dev In preparation for lan969x, rework the function that calculates the SDLB (Service Dual Leacky Bucket) clock. This is required, as the HSCH_SYS_CLK_PER register is Sparx5-exclusive. Instead derive the clock from the core clock, using the sparx5_clk_period() function. The clock stays the same before and after this patch, only now, sparx5_sdlb_clk_hz_get() can be used for lan969x too. Reviewed-by: Steen Hegelund Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 2 +- drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c | 10 +++------- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h b/drivers/= net/ethernet/microchip/sparx5/sparx5_main.h index f117cf65cf8c..2a3b4e855590 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h @@ -552,7 +552,7 @@ struct sparx5_sdlb_group *sparx5_get_sdlb_group(int idx= ); int sparx5_sdlb_pup_token_get(struct sparx5 *sparx5, u32 pup_interval, u64 rate); =20 -int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5); +u64 sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5); int sparx5_sdlb_group_get_by_rate(struct sparx5 *sparx5, u32 rate, u32 bur= st); int sparx5_sdlb_group_get_by_index(struct sparx5 *sparx5, u32 idx, u32 *gr= oup); =20 diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c b/drivers/= net/ethernet/microchip/sparx5/sparx5_sdlb.c index df1d15600aad..98a3f44c569c 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c @@ -25,17 +25,13 @@ struct sparx5_sdlb_group *sparx5_get_sdlb_group(int idx) return &sdlb_groups[idx]; } =20 -int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5) +u64 sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5) { - u32 clk_per_100ps; u64 clk_hz; =20 - clk_per_100ps =3D HSCH_SYS_CLK_PER_100PS_GET(spx5_rd(sparx5, - HSCH_SYS_CLK_PER)); - if (!clk_per_100ps) - clk_per_100ps =3D SPX5_CLK_PER_100PS_DEFAULT; + clk_hz =3D (10 * 1000 * 1000) / + (sparx5_clk_period(sparx5->coreclock) / 100); =20 - clk_hz =3D (10 * 1000 * 1000) / clk_per_100ps; return clk_hz *=3D 1000; } =20 --=20 2.34.1 From nobody Mon Nov 25 22:51:56 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F009261FE9; Wed, 23 Oct 2024 22:02:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729720959; cv=none; b=VmOHseRVanVUiAEY0s5DBx8F+WE6yXAcBTfKol5umgK4+qzKJdrFbohW7pgJRxG4VLmY9gBtiTkdlP1fvGQg6EqgXeYJc1Bbx3AlAK9n2vSfo2AANFcfKcGFLnFaMyQUbelYu+r7EkKDzVfjw7iIavHwLZgQbtyE2jRGooE4ACU= ARC-Message-Signature: i=1; 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Wed, 23 Oct 2024 15:01:55 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 23 Oct 2024 15:01:51 -0700 From: Daniel Machon Date: Thu, 24 Oct 2024 00:01:23 +0200 Subject: [PATCH net-next v2 04/15] net: sparx5: add sparx5 context pointer to a few functions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241024-sparx5-lan969x-switch-driver-2-v2-4-a0b5fae88a0f@microchip.com> References: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> In-Reply-To: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Lars Povlsen , Steen Hegelund , , , , , , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: , , , Steen Hegelund , X-Mailer: b4 0.14-dev In preparation for lan969x, add the sparx5 context pointer to certain IFH (Internal Frame Header) functions. This is required, as the is_sparx5() function will be used here in a subsequent patch. Reviewed-by: Steen Hegelund Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c | 2 +- drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 11 +++++++---- drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c | 9 ++++++--- drivers/net/ethernet/microchip/sparx5/sparx5_packet.c | 13 ++++++++----- 4 files changed, 22 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c b/drivers/= net/ethernet/microchip/sparx5/sparx5_fdma.c index 88f7509f0980..0027144a2af2 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c @@ -154,7 +154,7 @@ static bool sparx5_fdma_rx_get_frame(struct sparx5 *spa= rx5, struct sparx5_rx *rx skb =3D rx->skb[fdma->dcb_index][fdma->db_index]; skb_put(skb, fdma_db_len_get(db_hw)); /* Now do the normal processing of the skb */ - sparx5_ifh_parse((u32 *)skb->data, &fi); + sparx5_ifh_parse(sparx5, (u32 *)skb->data, &fi); /* Map to port netdev */ port =3D fi.src_port < sparx5->data->consts->n_ports ? sparx5->ports[fi.src_port] : diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h b/drivers/= net/ethernet/microchip/sparx5/sparx5_main.h index 2a3b4e855590..15f5d38776c4 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h @@ -401,7 +401,7 @@ struct frame_info { }; =20 void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp); -void sparx5_ifh_parse(u32 *ifh, struct frame_info *info); +void sparx5_ifh_parse(struct sparx5 *sparx5, u32 *ifh, struct frame_info *= info); irqreturn_t sparx5_xtr_handler(int irq, void *_priv); netdev_tx_t sparx5_port_xmit_impl(struct sk_buff *skb, struct net_device *= dev); int sparx5_manual_injection_mode(struct sparx5 *sparx5); @@ -469,10 +469,13 @@ static inline int sparx5_dcb_init(struct sparx5 *spar= x5) #endif =20 /* sparx5_netdev.c */ -void sparx5_set_port_ifh_timestamp(void *ifh_hdr, u64 timestamp); +void sparx5_set_port_ifh_timestamp(struct sparx5 *sparx5, void *ifh_hdr, + u64 timestamp); void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op); -void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type); -void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset); +void sparx5_set_port_ifh_pdu_type(struct sparx5 *sparx5, void *ifh_hdr, + u32 pdu_type); +void sparx5_set_port_ifh_pdu_w16_offset(struct sparx5 *sparx5, void *ifh_h= dr, + u32 pdu_w16_offset); void sparx5_set_port_ifh(struct sparx5 *sparx5, void *ifh_hdr, u16 portno); bool sparx5_netdevice_check(const struct net_device *dev); struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno); diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c b/driver= s/net/ethernet/microchip/sparx5/sparx5_netdev.c index d4e9986ef16a..a94d9a540bd3 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c @@ -81,17 +81,20 @@ void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_= op) ifh_encode_bitfield(ifh_hdr, rew_op, VSTAX + 32, 10); } =20 -void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type) +void sparx5_set_port_ifh_pdu_type(struct sparx5 *sparx5, void *ifh_hdr, + u32 pdu_type) { ifh_encode_bitfield(ifh_hdr, pdu_type, 191, 4); } =20 -void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset) +void sparx5_set_port_ifh_pdu_w16_offset(struct sparx5 *sparx5, void *ifh_h= dr, + u32 pdu_w16_offset) { ifh_encode_bitfield(ifh_hdr, pdu_w16_offset, 195, 6); } =20 -void sparx5_set_port_ifh_timestamp(void *ifh_hdr, u64 timestamp) +void sparx5_set_port_ifh_timestamp(struct sparx5 *sparx5, void *ifh_hdr, + u64 timestamp) { ifh_encode_bitfield(ifh_hdr, timestamp, 232, 40); } diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c b/driver= s/net/ethernet/microchip/sparx5/sparx5_packet.c index 5bfa86a71ac8..57fa9ff9dfce 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c @@ -32,7 +32,7 @@ void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp) spx5_wr(0, sparx5, QS_XTR_FLUSH); } =20 -void sparx5_ifh_parse(u32 *ifh, struct frame_info *info) +void sparx5_ifh_parse(struct sparx5 *sparx5, u32 *ifh, struct frame_info *= info) { u8 *xtr_hdr =3D (u8 *)ifh; =20 @@ -72,7 +72,7 @@ static void sparx5_xtr_grp(struct sparx5 *sparx5, u8 grp,= bool byte_swap) ifh[i] =3D spx5_rd(sparx5, QS_XTR_RD(grp)); =20 /* Decode IFH (what's needed) */ - sparx5_ifh_parse(ifh, &fi); + sparx5_ifh_parse(sparx5, ifh, &fi); =20 /* Map to port netdev */ port =3D fi.src_port < sparx5->data->consts->n_ports ? @@ -242,9 +242,12 @@ netdev_tx_t sparx5_port_xmit_impl(struct sk_buff *skb,= struct net_device *dev) return NETDEV_TX_BUSY; =20 sparx5_set_port_ifh_rew_op(ifh, SPARX5_SKB_CB(skb)->rew_op); - sparx5_set_port_ifh_pdu_type(ifh, SPARX5_SKB_CB(skb)->pdu_type); - sparx5_set_port_ifh_pdu_w16_offset(ifh, SPARX5_SKB_CB(skb)->pdu_w16_offs= et); - sparx5_set_port_ifh_timestamp(ifh, SPARX5_SKB_CB(skb)->ts_id); + sparx5_set_port_ifh_pdu_type(sparx5, ifh, + SPARX5_SKB_CB(skb)->pdu_type); + sparx5_set_port_ifh_pdu_w16_offset(sparx5, ifh, + SPARX5_SKB_CB(skb)->pdu_w16_offset); + sparx5_set_port_ifh_timestamp(sparx5, ifh, + SPARX5_SKB_CB(skb)->ts_id); } =20 skb_tx_timestamp(skb); --=20 2.34.1 From nobody Mon Nov 25 22:51:56 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC2291FAC36; Wed, 23 Oct 2024 22:02:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729720929; cv=none; b=UEjPThJHg/KKTTzY1vTRRtoFLVY9Q46lMNp+JHemwochrJuLmNh5DwvoCRe5xnYoAiEXBexArdKqPyPfS5pg2K+vHOFsOYkEoVVU4aSEP6rW9qKONPKAmgzkWQc/HcYo3DSQbx0Oxx79dExTBS2H7AjcAvJ6rrdO3pxuuwSbwrs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729720929; c=relaxed/simple; bh=tYIsnlYu8tQgs3FFqbphhsO7GFXXscQdLLBW4Ok9TdI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=dqlitAfulRJsiQ5JfQpam0G/FXQVbXrNi+TWcjAd4/R3L4xvBvw0pA3BsJta4etsADC+OFLWplbcnG1Qn6fyN0OVg1G1+6+kvC57tsx81r9iaQv/2Vznhnt6xIy9tZkhKa/gNw0UViVwdHuB91TDK/n3XnBr7/+yk3IomBWyNdM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=as8iU2aX; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="as8iU2aX" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1729720927; x=1761256927; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=tYIsnlYu8tQgs3FFqbphhsO7GFXXscQdLLBW4Ok9TdI=; b=as8iU2aXsR2oF1TgozM/qP24TcCTiHikSMu1xlTY2UGVw/on5AgfxUJv Qa6EAqxIIkGzZOm2tdDCfubG1rnRkeaKdji/rB1j5utBnfFpaiCdQ5Ks/ FIByCvbfJG+bRaGyyzpobmGRq10VSubycKkPi+81BSV8qQtHTaz/9KBUz pDGsWOq5LwjwXRX4F1Wo8Pdy6PAwDzq8yZA+K31tGZRatPl0M0/Y5oTdL EdZKV+VPkl2MEksp5AQYNrt3Rih5HFt3xcrpPrBLrvJZ0lg/UotO6XPmS cSG9FlvMvzIy34Vsz/0HvogZ+ey6r6r0NoSY6xpN1TyZ+yK97AzzAY0il g==; X-CSE-ConnectionGUID: 1Xapdzk8QAqz3uJYdYtrIg== X-CSE-MsgGUID: BGTP6e2oRi2jYdjqN96SDQ== X-IronPort-AV: E=Sophos;i="6.11,227,1725346800"; d="scan'208";a="33409631" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Oct 2024 15:02:04 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 23 Oct 2024 15:01:59 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 23 Oct 2024 15:01:55 -0700 From: Daniel Machon Date: Thu, 24 Oct 2024 00:01:24 +0200 Subject: [PATCH net-next v2 05/15] net: sparx5: add registers required by lan969x Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241024-sparx5-lan969x-switch-driver-2-v2-5-a0b5fae88a0f@microchip.com> References: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> In-Reply-To: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Lars Povlsen , Steen Hegelund , , , , , , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: , , , Steen Hegelund , X-Mailer: b4 0.14-dev Lan969x will require a few additional registers for certain operations. Some are shared, some are not. Add these. Reviewed-by: Steen Hegelund Signed-off-by: Daniel Machon --- .../ethernet/microchip/sparx5/sparx5_main_regs.h | 132 +++++++++++++++++= ++++ 1 file changed, 132 insertions(+) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h b/dri= vers/net/ethernet/microchip/sparx5/sparx5_main_regs.h index 0e8b18bcf179..561344f19062 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h @@ -2666,6 +2666,44 @@ extern const struct sparx5_regs *regs; #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\ FIELD_GET(CPU_PROC_CTRL_ACP_DISABLE, x) =20 +/* DEV1G:PHASE_DETECTOR_CTRL:PHAD_CTRL */ +#define DEV2G5_PHAD_CTRL(t, g) = \ + __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 200, g, 2, \ + regs->gsize[GW_DEV2G5_PHASE_DETECTOR_CTRL], 0, 0, 1, 4) + +#define DEV2G5_PHAD_CTRL_PHAD_ENA\ + BIT(regs->fpos[FP_DEV2G5_PHAD_CTRL_PHAD_ENA]) +#define DEV2G5_PHAD_CTRL_PHAD_ENA_SET(x)\ + spx5_field_prep(DEV2G5_PHAD_CTRL_PHAD_ENA, x) +#define DEV2G5_PHAD_CTRL_PHAD_ENA_GET(x)\ + spx5_field_get(DEV2G5_PHAD_CTRL_PHAD_ENA, x) + +/* LAN969X ONLY */ +#define DEV2G5_PHAD_CTRL_DIV_CFG GENMASK(11, 9) +#define DEV2G5_PHAD_CTRL_DIV_CFG_SET(x)\ + FIELD_PREP(DEV2G5_PHAD_CTRL_DIV_CFG, x) +#define DEV2G5_PHAD_CTRL_DIV_CFG_GET(x)\ + FIELD_GET(DEV2G5_PHAD_CTRL_DIV_CFG, x) + +/* DEV1G:PHASE_DETECTOR_CTRL:PHAD_CTRL */ +#define DEV2G5_PHAD_CTRL(t, g) = \ + __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 200, g, 2, \ + regs->gsize[GW_DEV2G5_PHASE_DETECTOR_CTRL], 0, 0, 1, 4) + +#define DEV2G5_PHAD_CTRL_PHAD_ENA\ + BIT(regs->fpos[FP_DEV2G5_PHAD_CTRL_PHAD_ENA]) +#define DEV2G5_PHAD_CTRL_PHAD_ENA_SET(x)\ + spx5_field_prep(DEV2G5_PHAD_CTRL_PHAD_ENA, x) +#define DEV2G5_PHAD_CTRL_PHAD_ENA_GET(x)\ + spx5_field_get(DEV2G5_PHAD_CTRL_PHAD_ENA, x) + +/* LAN969X ONLY */ +#define DEV2G5_PHAD_CTRL_DIV_CFG GENMASK(11, 9) +#define DEV2G5_PHAD_CTRL_DIV_CFG_SET(x)\ + FIELD_PREP(DEV2G5_PHAD_CTRL_DIV_CFG, x) +#define DEV2G5_PHAD_CTRL_DIV_CFG_GET(x)\ + FIELD_GET(DEV2G5_PHAD_CTRL_DIV_CFG, x) + /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ #define DEV10G_MAC_ENA_CFG(t) = \ __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 0, 0, 1, \ @@ -2869,6 +2907,11 @@ extern const struct sparx5_regs *regs; #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x) =20 +/* DEV10G:DEV_CFG_STATUS:PTP_STAMPER_CFG */ +#define DEV10G_PTP_STAMPER_CFG(t) = \ + __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 436, 0, 1, 52, 20, 0, \ + 1, 4) + /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ #define DEV10G_PCS25G_CFG(t) = \ __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 488, 0, 1, 32, 0, 0, 1,\ @@ -4267,6 +4310,11 @@ extern const struct sparx5_regs *regs; #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x) =20 +/* DEV10G:DEV_CFG_STATUS:PTP_STAMPER_CFG */ +#define DEV5G_PTP_STAMPER_CFG(t) = \ + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 436, 0, 1, 52, 20, 0, 1, \ + 4) + /* DSM:RAM_CTRL:RAM_INIT */ #define DSM_RAM_INIT = \ __REG(TARGET_DSM, 0, 1, 0, 0, 1, 4, 0, 0, 1, 4) @@ -4444,6 +4492,27 @@ extern const struct sparx5_regs *regs; #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\ FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x) =20 +/* LAN969X ONLY */ +#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT BIT(23) +#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_SET(x)\ + FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_SEL_STAT, x) +#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_GET(x)\ + FIELD_GET(DSM_TAXI_CAL_CFG_CAL_SEL_STAT, x) + +/* LAN969X ONLY */ +#define DSM_TAXI_CAL_CFG_CAL_SWITCH BIT(22) +#define DSM_TAXI_CAL_CFG_CAL_SWITCH_SET(x)\ + FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_SWITCH, x) +#define DSM_TAXI_CAL_CFG_CAL_SWITCH_GET(x)\ + FIELD_GET(DSM_TAXI_CAL_CFG_CAL_SWITCH, x) + +/* LAN969X ONLY */ +#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL BIT(21) +#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_SET(x)\ + FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_SEL, x) +#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_GET(x)\ + FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_SEL, x) + /* EACL:ES2_KEY_SELECT_PROFILE:VCAP_ES2_KEY_SEL */ #define EACL_VCAP_ES2_KEY_SEL(g, r) = \ __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_ES2_KEY_SELECT_PROFILE], \ @@ -6720,6 +6789,69 @@ extern const struct sparx5_regs *regs; regs->gcnt[GC_PTP_PHASE_DETECTOR_CTRL], \ regs->gsize[GW_PTP_PHASE_DETECTOR_CTRL], 4, 0, 1, 4) =20 +/* LAN969X ONLY */ +/* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_CTRL */ +#define PTP_TWOSTEP_CTRL = \ + __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 0, 0, 1, 4) + +#define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA BIT(12) +#define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\ + FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x) +#define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\ + FIELD_GET(PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x) + +#define PTP_TWOSTEP_CTRL_PTP_NXT BIT(11) +#define PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\ + FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_NXT, x) +#define PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\ + FIELD_GET(PTP_TWOSTEP_CTRL_PTP_NXT, x) + +#define PTP_TWOSTEP_CTRL_PTP_VLD BIT(10) +#define PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\ + FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_VLD, x) +#define PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\ + FIELD_GET(PTP_TWOSTEP_CTRL_PTP_VLD, x) + +#define PTP_TWOSTEP_CTRL_STAMP_TX BIT(9) +#define PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\ + FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_TX, x) +#define PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\ + FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_TX, x) + +#define PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1) +#define PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\ + FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_PORT, x) +#define PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\ + FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_PORT, x) + +#define PTP_TWOSTEP_CTRL_PTP_OVFL BIT(0) +#define PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\ + FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_OVFL, x) +#define PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\ + FIELD_GET(PTP_TWOSTEP_CTRL_PTP_OVFL, x) + +/* LAN969X ONLY */ +/* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP_NSEC */ +#define PTP_TWOSTEP_STAMP_NSEC = \ + __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 4, 0, 1, 4) + +#define PTP_TWOSTEP_STAMP_NSEC_NS GENMASK(29, 0) +#define PTP_TWOSTEP_STAMP_NSEC_NS_SET(x)\ + FIELD_PREP(PTP_TWOSTEP_STAMP_NSEC_NS, x) +#define PTP_TWOSTEP_STAMP_NSEC_NS_GET(x)\ + FIELD_GET(PTP_TWOSTEP_STAMP_NSEC_NS, x) + +/* LAN969X ONLY */ +/* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP_SUBNS */ +#define PTP_TWOSTEP_STAMP_SUBNS = \ + __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 8, 0, 1, 4) + +#define PTP_TWOSTEP_STAMP_SUBNS_NS GENMASK(7, 0) +#define PTP_TWOSTEP_STAMP_SUBNS_NS_SET(x)\ + FIELD_PREP(PTP_TWOSTEP_STAMP_SUBNS_NS, x) +#define PTP_TWOSTEP_STAMP_SUBNS_NS_GET(x)\ + FIELD_GET(PTP_TWOSTEP_STAMP_SUBNS_NS, x) + /* QFWD:SYSTEM:SWITCH_PORT_MODE */ #define QFWD_SWITCH_PORT_MODE(r) = \ __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 0, r, \ --=20 2.34.1 From nobody Mon Nov 25 22:51:56 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A1711E1311; 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X-CSE-ConnectionGUID: 1Xapdzk8QAqz3uJYdYtrIg== X-CSE-MsgGUID: sopeB3rDT5m4tF48pmQKWw== X-IronPort-AV: E=Sophos;i="6.11,227,1725346800"; d="scan'208";a="33409632" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Oct 2024 15:02:05 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 23 Oct 2024 15:02:04 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 23 Oct 2024 15:02:00 -0700 From: Daniel Machon Date: Thu, 24 Oct 2024 00:01:25 +0200 Subject: [PATCH net-next v2 06/15] net: lan969x: add match data for lan969x Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241024-sparx5-lan969x-switch-driver-2-v2-6-a0b5fae88a0f@microchip.com> References: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> In-Reply-To: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Lars Povlsen , Steen Hegelund , , , , , , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: , , , Steen Hegelund , X-Mailer: b4 0.14-dev Add match data for lan969x, with initial fields for iomap, iomap_size and ioranges. Add new Kconfig symbol CONFIG_LAN969X_CONFIG for compiling the lan969x driver. It has been decided to give lan969x its own Kconfig symbol, as a considerable amount of code is needed, beside the Sparx5 code, to add full chip support (and more will be added in future series). Also this makes it possible to compile Sparx5 without lan969x. Reviewed-by: Steen Hegelund Signed-off-by: Daniel Machon --- MAINTAINERS | 7 ++ drivers/net/ethernet/microchip/Kconfig | 1 + drivers/net/ethernet/microchip/Makefile | 1 + drivers/net/ethernet/microchip/lan969x/Kconfig | 5 ++ drivers/net/ethernet/microchip/lan969x/Makefile | 12 +++ drivers/net/ethernet/microchip/lan969x/lan969x.c | 104 +++++++++++++++++++= ++++ drivers/net/ethernet/microchip/lan969x/lan969x.h | 15 ++++ 7 files changed, 145 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index aed1fa42cfd2..c6bc8f111cf0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15188,6 +15188,13 @@ S: Maintained F: Documentation/devicetree/bindings/interrupt-controller/microchip,lan966= x-oic.yaml F: drivers/irqchip/irq-lan966x-oic.c =20 +MICROCHIP LAN969X ETHERNET DRIVER +M: Daniel Machon +M: UNGLinuxDriver@microchip.com +L: netdev@vger.kernel.org +S: Maintained +F: drivers/net/ethernet/microchip/lan969x/* + MICROCHIP LCDFB DRIVER M: Nicolas Ferre L: linux-fbdev@vger.kernel.org diff --git a/drivers/net/ethernet/microchip/Kconfig b/drivers/net/ethernet/= microchip/Kconfig index ee046468652c..73832fb2bc32 100644 --- a/drivers/net/ethernet/microchip/Kconfig +++ b/drivers/net/ethernet/microchip/Kconfig @@ -59,6 +59,7 @@ config LAN743X =20 source "drivers/net/ethernet/microchip/lan865x/Kconfig" source "drivers/net/ethernet/microchip/lan966x/Kconfig" +source "drivers/net/ethernet/microchip/lan969x/Kconfig" source "drivers/net/ethernet/microchip/sparx5/Kconfig" source "drivers/net/ethernet/microchip/vcap/Kconfig" source "drivers/net/ethernet/microchip/fdma/Kconfig" diff --git a/drivers/net/ethernet/microchip/Makefile b/drivers/net/ethernet= /microchip/Makefile index 3c65baed9fd8..7770df82200f 100644 --- a/drivers/net/ethernet/microchip/Makefile +++ b/drivers/net/ethernet/microchip/Makefile @@ -11,6 +11,7 @@ lan743x-objs :=3D lan743x_main.o lan743x_ethtool.o lan743= x_ptp.o =20 obj-$(CONFIG_LAN865X) +=3D lan865x/ obj-$(CONFIG_LAN966X_SWITCH) +=3D lan966x/ +obj-$(CONFIG_LAN969X_SWITCH) +=3D lan969x/ obj-$(CONFIG_SPARX5_SWITCH) +=3D sparx5/ obj-$(CONFIG_VCAP) +=3D vcap/ obj-$(CONFIG_FDMA) +=3D fdma/ diff --git a/drivers/net/ethernet/microchip/lan969x/Kconfig b/drivers/net/e= thernet/microchip/lan969x/Kconfig new file mode 100644 index 000000000000..728180d3fa33 --- /dev/null +++ b/drivers/net/ethernet/microchip/lan969x/Kconfig @@ -0,0 +1,5 @@ +config LAN969X_SWITCH + tristate "Lan969x switch driver" + depends on SPARX5_SWITCH + help + This driver supports the lan969x family of network switch devices. diff --git a/drivers/net/ethernet/microchip/lan969x/Makefile b/drivers/net/= ethernet/microchip/lan969x/Makefile new file mode 100644 index 000000000000..f3d9dfcd8c30 --- /dev/null +++ b/drivers/net/ethernet/microchip/lan969x/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Makefile for the Microchip lan969x network device drivers. +# + +obj-$(CONFIG_LAN969X_SWITCH) +=3D lan969x-switch.o + +lan969x-switch-y :=3D lan969x.o + +# Provide include files +ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/microchip/fdma +ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/microchip/vcap diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x.c b/drivers/net= /ethernet/microchip/lan969x/lan969x.c new file mode 100644 index 000000000000..488af2a8ee3c --- /dev/null +++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Microchip lan969x Switch driver + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + */ + +#include "lan969x.h" + +static const struct sparx5_main_io_resource lan969x_main_iomap[] =3D { + { TARGET_CPU, 0xc0000, 0 }, /* 0xe00c0000 */ + { TARGET_FDMA, 0xc0400, 0 }, /* 0xe00c0400 */ + { TARGET_GCB, 0x2010000, 1 }, /* 0xe2010000 */ + { TARGET_QS, 0x2030000, 1 }, /* 0xe2030000 */ + { TARGET_PTP, 0x2040000, 1 }, /* 0xe2040000 */ + { TARGET_ANA_ACL, 0x2050000, 1 }, /* 0xe2050000 */ + { TARGET_LRN, 0x2060000, 1 }, /* 0xe2060000 */ + { TARGET_VCAP_SUPER, 0x2080000, 1 }, /* 0xe2080000 */ + { TARGET_QSYS, 0x20a0000, 1 }, /* 0xe20a0000 */ + { TARGET_QFWD, 0x20b0000, 1 }, /* 0xe20b0000 */ + { TARGET_XQS, 0x20c0000, 1 }, /* 0xe20c0000 */ + { TARGET_VCAP_ES2, 0x20d0000, 1 }, /* 0xe20d0000 */ + { TARGET_VCAP_ES0, 0x20e0000, 1 }, /* 0xe20e0000 */ + { TARGET_ANA_AC_POL, 0x2200000, 1 }, /* 0xe2200000 */ + { TARGET_QRES, 0x2280000, 1 }, /* 0xe2280000 */ + { TARGET_EACL, 0x22c0000, 1 }, /* 0xe22c0000 */ + { TARGET_ANA_CL, 0x2400000, 1 }, /* 0xe2400000 */ + { TARGET_ANA_L3, 0x2480000, 1 }, /* 0xe2480000 */ + { TARGET_ANA_AC_SDLB, 0x2500000, 1 }, /* 0xe2500000 */ + { TARGET_HSCH, 0x2580000, 1 }, /* 0xe2580000 */ + { TARGET_REW, 0x2600000, 1 }, /* 0xe2600000 */ + { TARGET_ANA_L2, 0x2800000, 1 }, /* 0xe2800000 */ + { TARGET_ANA_AC, 0x2900000, 1 }, /* 0xe2900000 */ + { TARGET_VOP, 0x2a00000, 1 }, /* 0xe2a00000 */ + { TARGET_DEV2G5, 0x3004000, 1 }, /* 0xe3004000 */ + { TARGET_DEV10G, 0x3008000, 1 }, /* 0xe3008000 */ + { TARGET_PCS10G_BR, 0x300c000, 1 }, /* 0xe300c000 */ + { TARGET_DEV2G5 + 1, 0x3010000, 1 }, /* 0xe3010000 */ + { TARGET_DEV2G5 + 2, 0x3014000, 1 }, /* 0xe3014000 */ + { TARGET_DEV2G5 + 3, 0x3018000, 1 }, /* 0xe3018000 */ + { TARGET_DEV2G5 + 4, 0x301c000, 1 }, /* 0xe301c000 */ + { TARGET_DEV10G + 1, 0x3020000, 1 }, /* 0xe3020000 */ + { TARGET_PCS10G_BR + 1, 0x3024000, 1 }, /* 0xe3024000 */ + { TARGET_DEV2G5 + 5, 0x3028000, 1 }, /* 0xe3028000 */ + { TARGET_DEV2G5 + 6, 0x302c000, 1 }, /* 0xe302c000 */ + { TARGET_DEV2G5 + 7, 0x3030000, 1 }, /* 0xe3030000 */ + { TARGET_DEV2G5 + 8, 0x3034000, 1 }, /* 0xe3034000 */ + { TARGET_DEV10G + 2, 0x3038000, 1 }, /* 0xe3038000 */ + { TARGET_PCS10G_BR + 2, 0x303c000, 1 }, /* 0xe303c000 */ + { TARGET_DEV2G5 + 9, 0x3040000, 1 }, /* 0xe3040000 */ + { TARGET_DEV5G, 0x3044000, 1 }, /* 0xe3044000 */ + { TARGET_PCS5G_BR, 0x3048000, 1 }, /* 0xe3048000 */ + { TARGET_DEV2G5 + 10, 0x304c000, 1 }, /* 0xe304c000 */ + { TARGET_DEV2G5 + 11, 0x3050000, 1 }, /* 0xe3050000 */ + { TARGET_DEV2G5 + 12, 0x3054000, 1 }, /* 0xe3054000 */ + { TARGET_DEV10G + 3, 0x3058000, 1 }, /* 0xe3058000 */ + { TARGET_PCS10G_BR + 3, 0x305c000, 1 }, /* 0xe305c000 */ + { TARGET_DEV2G5 + 13, 0x3060000, 1 }, /* 0xe3060000 */ + { TARGET_DEV5G + 1, 0x3064000, 1 }, /* 0xe3064000 */ + { TARGET_PCS5G_BR + 1, 0x3068000, 1 }, /* 0xe3068000 */ + { TARGET_DEV2G5 + 14, 0x306c000, 1 }, /* 0xe306c000 */ + { TARGET_DEV2G5 + 15, 0x3070000, 1 }, /* 0xe3070000 */ + { TARGET_DEV2G5 + 16, 0x3074000, 1 }, /* 0xe3074000 */ + { TARGET_DEV10G + 4, 0x3078000, 1 }, /* 0xe3078000 */ + { TARGET_PCS10G_BR + 4, 0x307c000, 1 }, /* 0xe307c000 */ + { TARGET_DEV2G5 + 17, 0x3080000, 1 }, /* 0xe3080000 */ + { TARGET_DEV5G + 2, 0x3084000, 1 }, /* 0xe3084000 */ + { TARGET_PCS5G_BR + 2, 0x3088000, 1 }, /* 0xe3088000 */ + { TARGET_DEV2G5 + 18, 0x308c000, 1 }, /* 0xe308c000 */ + { TARGET_DEV2G5 + 19, 0x3090000, 1 }, /* 0xe3090000 */ + { TARGET_DEV2G5 + 20, 0x3094000, 1 }, /* 0xe3094000 */ + { TARGET_DEV10G + 5, 0x3098000, 1 }, /* 0xe3098000 */ + { TARGET_PCS10G_BR + 5, 0x309c000, 1 }, /* 0xe309c000 */ + { TARGET_DEV2G5 + 21, 0x30a0000, 1 }, /* 0xe30a0000 */ + { TARGET_DEV5G + 3, 0x30a4000, 1 }, /* 0xe30a4000 */ + { TARGET_PCS5G_BR + 3, 0x30a8000, 1 }, /* 0xe30a8000 */ + { TARGET_DEV2G5 + 22, 0x30ac000, 1 }, /* 0xe30ac000 */ + { TARGET_DEV2G5 + 23, 0x30b0000, 1 }, /* 0xe30b0000 */ + { TARGET_DEV2G5 + 24, 0x30b4000, 1 }, /* 0xe30b4000 */ + { TARGET_DEV10G + 6, 0x30b8000, 1 }, /* 0xe30b8000 */ + { TARGET_PCS10G_BR + 6, 0x30bc000, 1 }, /* 0xe30bc000 */ + { TARGET_DEV2G5 + 25, 0x30c0000, 1 }, /* 0xe30c0000 */ + { TARGET_DEV10G + 7, 0x30c4000, 1 }, /* 0xe30c4000 */ + { TARGET_PCS10G_BR + 7, 0x30c8000, 1 }, /* 0xe30c8000 */ + { TARGET_DEV2G5 + 26, 0x30cc000, 1 }, /* 0xe30cc000 */ + { TARGET_DEV10G + 8, 0x30d0000, 1 }, /* 0xe30d0000 */ + { TARGET_PCS10G_BR + 8, 0x30d4000, 1 }, /* 0xe30d4000 */ + { TARGET_DEV2G5 + 27, 0x30d8000, 1 }, /* 0xe30d8000 */ + { TARGET_DEV10G + 9, 0x30dc000, 1 }, /* 0xe30dc000 */ + { TARGET_PCS10G_BR + 9, 0x30e0000, 1 }, /* 0xe30e0000 */ + { TARGET_DSM, 0x30ec000, 1 }, /* 0xe30ec000 */ + { TARGET_PORT_CONF, 0x30f0000, 1 }, /* 0xe30f0000 */ + { TARGET_ASM, 0x3200000, 1 }, /* 0xe3200000 */ +}; + +const struct sparx5_match_data lan969x_desc =3D { + .iomap =3D lan969x_main_iomap, + .iomap_size =3D ARRAY_SIZE(lan969x_main_iomap), + .ioranges =3D 2, +}; +EXPORT_SYMBOL_GPL(lan969x_desc); + +MODULE_DESCRIPTION("Microchip lan969x switch driver"); +MODULE_AUTHOR("Daniel Machon "); +MODULE_LICENSE("Dual MIT/GPL"); diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x.h b/drivers/net= /ethernet/microchip/lan969x/lan969x.h new file mode 100644 index 000000000000..0507046ab9af --- /dev/null +++ b/drivers/net/ethernet/microchip/lan969x/lan969x.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Microchip lan969x Switch driver + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + */ + +#ifndef __LAN969X_H__ +#define __LAN969X_H__ + +#include "../sparx5/sparx5_main.h" + +/* lan969x.c */ +extern const struct sparx5_match_data lan969x_desc; + +#endif --=20 2.34.1 From nobody Mon Nov 25 22:51:56 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F04801FBC80; Wed, 23 Oct 2024 22:02:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729720960; cv=none; b=rpr2XPE/+2d+KChq88TWXKr6mA0XixYD9+Uv15+pZBdTkgHJJ7N2kEg5RbCivCUrdpOueIXhiIf9WCwJvhbVlEEpdFaNwJf32Dd6N4X5oJKzwokN05J/LZPXI9lncc+0N104NpGqQ7DdgY+1NEkQWCNob9s8RkAkK+f3zhygNVw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729720960; c=relaxed/simple; bh=J8qCXnNG/OAP9j8DsIe5XLMigohB45RpGMYrjnzBjeQ=; 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(10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 23 Oct 2024 15:02:08 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 23 Oct 2024 15:02:04 -0700 From: Daniel Machon Date: Thu, 24 Oct 2024 00:01:26 +0200 Subject: [PATCH net-next v2 07/15] net: lan969x: add register diffs to match data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241024-sparx5-lan969x-switch-driver-2-v2-7-a0b5fae88a0f@microchip.com> References: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> In-Reply-To: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Lars Povlsen , Steen Hegelund , , , , , , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: , , , Steen Hegelund , X-Mailer: b4 0.14-dev Add new file lan969x_regs.c that defines all the register differences for lan969x, and add it to the lan969x match data. GW_DEV2G5_PHASE_DETECTOR_CTRL, FP_DEV2G5_PHAD_CTRL_PHAD_ENA and FP_DEV2G5_PHAD_CTRL_PHAD_FAILED are required by the new register macros which was introduced earlier. Add these for Sparx5 also. Reviewed-by: Steen Hegelund Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/lan969x/Makefile | 2 +- drivers/net/ethernet/microchip/lan969x/lan969x.c | 12 ++ drivers/net/ethernet/microchip/lan969x/lan969x.h | 11 + .../net/ethernet/microchip/lan969x/lan969x_regs.c | 222 +++++++++++++++++= ++++ .../net/ethernet/microchip/sparx5/sparx5_regs.c | 5 +- .../net/ethernet/microchip/sparx5/sparx5_regs.h | 5 +- 6 files changed, 254 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan969x/Makefile b/drivers/net/= ethernet/microchip/lan969x/Makefile index f3d9dfcd8c30..ff40e7e5d420 100644 --- a/drivers/net/ethernet/microchip/lan969x/Makefile +++ b/drivers/net/ethernet/microchip/lan969x/Makefile @@ -5,7 +5,7 @@ =20 obj-$(CONFIG_LAN969X_SWITCH) +=3D lan969x-switch.o =20 -lan969x-switch-y :=3D lan969x.o +lan969x-switch-y :=3D lan969x_regs.o lan969x.o =20 # Provide include files ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/microchip/fdma diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x.c b/drivers/net= /ethernet/microchip/lan969x/lan969x.c index 488af2a8ee3c..0b47e4e66058 100644 --- a/drivers/net/ethernet/microchip/lan969x/lan969x.c +++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c @@ -92,10 +92,22 @@ static const struct sparx5_main_io_resource lan969x_mai= n_iomap[] =3D { { TARGET_ASM, 0x3200000, 1 }, /* 0xe3200000 */ }; =20 +static const struct sparx5_regs lan969x_regs =3D { + .tsize =3D lan969x_tsize, + .gaddr =3D lan969x_gaddr, + .gcnt =3D lan969x_gcnt, + .gsize =3D lan969x_gsize, + .raddr =3D lan969x_raddr, + .rcnt =3D lan969x_rcnt, + .fpos =3D lan969x_fpos, + .fsize =3D lan969x_fsize, +}; + const struct sparx5_match_data lan969x_desc =3D { .iomap =3D lan969x_main_iomap, .iomap_size =3D ARRAY_SIZE(lan969x_main_iomap), .ioranges =3D 2, + .regs =3D &lan969x_regs, }; EXPORT_SYMBOL_GPL(lan969x_desc); =20 diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x.h b/drivers/net= /ethernet/microchip/lan969x/lan969x.h index 0507046ab9af..3b4c9ea30071 100644 --- a/drivers/net/ethernet/microchip/lan969x/lan969x.h +++ b/drivers/net/ethernet/microchip/lan969x/lan969x.h @@ -8,8 +8,19 @@ #define __LAN969X_H__ =20 #include "../sparx5/sparx5_main.h" +#include "../sparx5/sparx5_regs.h" =20 /* lan969x.c */ extern const struct sparx5_match_data lan969x_desc; =20 +/* lan969x_regs.c */ +extern const unsigned int lan969x_tsize[TSIZE_LAST]; +extern const unsigned int lan969x_raddr[RADDR_LAST]; +extern const unsigned int lan969x_rcnt[RCNT_LAST]; +extern const unsigned int lan969x_gaddr[GADDR_LAST]; +extern const unsigned int lan969x_gcnt[GCNT_LAST]; +extern const unsigned int lan969x_gsize[GSIZE_LAST]; +extern const unsigned int lan969x_fpos[FPOS_LAST]; +extern const unsigned int lan969x_fsize[FSIZE_LAST]; + #endif diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x_regs.c b/driver= s/net/ethernet/microchip/lan969x/lan969x_regs.c new file mode 100644 index 000000000000..ace4ba21eec4 --- /dev/null +++ b/drivers/net/ethernet/microchip/lan969x/lan969x_regs.c @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Microchip lan969x Switch driver + * + * Copyright (c) 2024 Microchip Technology Inc. + */ + +/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200. + * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b + */ + +#include "lan969x.h" + +const unsigned int lan969x_tsize[TSIZE_LAST] =3D { + [TC_DEV10G] =3D 10, + [TC_DEV2G5] =3D 28, + [TC_DEV5G] =3D 4, + [TC_PCS10G_BR] =3D 10, + [TC_PCS5G_BR] =3D 4, +}; + +const unsigned int lan969x_raddr[RADDR_LAST] =3D { + [RA_CPU_PROC_CTRL] =3D 160, + [RA_GCB_SOFT_RST] =3D 12, + [RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] =3D 20, +}; + +const unsigned int lan969x_rcnt[RCNT_LAST] =3D { + [RC_ANA_AC_OWN_UPSID] =3D 1, + [RC_ANA_ACL_VCAP_S2_CFG] =3D 35, + [RC_ANA_ACL_OWN_UPSID] =3D 1, + [RC_ANA_CL_OWN_UPSID] =3D 1, + [RC_ANA_L2_OWN_UPSID] =3D 1, + [RC_ASM_PORT_CFG] =3D 32, + [RC_DSM_BUF_CFG] =3D 32, + [RC_DSM_DEV_TX_STOP_WM_CFG] =3D 32, + [RC_DSM_RX_PAUSE_CFG] =3D 32, + [RC_DSM_MAC_CFG] =3D 32, + [RC_DSM_MAC_ADDR_BASE_HIGH_CFG] =3D 30, + [RC_DSM_MAC_ADDR_BASE_LOW_CFG] =3D 30, + [RC_DSM_TAXI_CAL_CFG] =3D 6, + [RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] =3D 30, + [RC_HSCH_PORT_MODE] =3D 35, + [RC_QFWD_SWITCH_PORT_MODE] =3D 35, + [RC_QSYS_PAUSE_CFG] =3D 35, + [RC_QSYS_ATOP] =3D 35, + [RC_QSYS_FWD_PRESSURE] =3D 35, + [RC_QSYS_CAL_AUTO] =3D 4, + [RC_REW_OWN_UPSID] =3D 1, + [RC_REW_RTAG_ETAG_CTRL] =3D 35, +}; + +const unsigned int lan969x_gaddr[GADDR_LAST] =3D { + [GA_ANA_AC_RAM_CTRL] =3D 202000, + [GA_ANA_AC_PS_COMMON] =3D 202880, + [GA_ANA_AC_MIRROR_PROBE] =3D 203232, + [GA_ANA_AC_SRC] =3D 201728, + [GA_ANA_AC_PGID] =3D 131072, + [GA_ANA_AC_TSN_SF] =3D 202028, + [GA_ANA_AC_TSN_SF_CFG] =3D 148480, + [GA_ANA_AC_TSN_SF_STATUS] =3D 147936, + [GA_ANA_AC_SG_ACCESS] =3D 202032, + [GA_ANA_AC_SG_CONFIG] =3D 202752, + [GA_ANA_AC_SG_STATUS] =3D 147952, + [GA_ANA_AC_SG_STATUS_STICKY] =3D 202044, + [GA_ANA_AC_STAT_GLOBAL_CFG_PORT] =3D 202048, + [GA_ANA_AC_STAT_CNT_CFG_PORT] =3D 204800, + [GA_ANA_AC_STAT_GLOBAL_CFG_ACL] =3D 202068, + [GA_ANA_ACL_COMMON] =3D 8192, + [GA_ANA_ACL_KEY_SEL] =3D 9204, + [GA_ANA_ACL_CNT_B] =3D 4096, + [GA_ANA_ACL_STICKY] =3D 10852, + [GA_ANA_AC_POL_POL_ALL_CFG] =3D 17504, + [GA_ANA_AC_POL_COMMON_BDLB] =3D 19464, + [GA_ANA_AC_POL_COMMON_BUM_SLB] =3D 19472, + [GA_ANA_AC_SDLB_LBGRP_TBL] =3D 31788, + [GA_ANA_CL_PORT] =3D 65536, + [GA_ANA_CL_COMMON] =3D 87040, + [GA_ANA_L2_COMMON] =3D 561928, + [GA_ANA_L3_COMMON] =3D 370752, + [GA_ANA_L3_VLAN_ARP_L3MC_STICKY] =3D 368580, + [GA_ASM_CFG] =3D 18304, + [GA_ASM_PFC_TIMER_CFG] =3D 15568, + [GA_ASM_LBK_WM_CFG] =3D 15596, + [GA_ASM_LBK_MISC_CFG] =3D 15608, + [GA_ASM_RAM_CTRL] =3D 15684, + [GA_EACL_ES2_KEY_SELECT_PROFILE] =3D 36864, + [GA_EACL_CNT_TBL] =3D 30720, + [GA_EACL_POL_CFG] =3D 38400, + [GA_EACL_ES2_STICKY] =3D 29072, + [GA_EACL_RAM_CTRL] =3D 29112, + [GA_GCB_SIO_CTRL] =3D 560, + [GA_HSCH_HSCH_DWRR] =3D 36480, + [GA_HSCH_HSCH_MISC] =3D 36608, + [GA_HSCH_HSCH_LEAK_LISTS] =3D 37256, + [GA_HSCH_SYSTEM] =3D 37384, + [GA_HSCH_MMGT] =3D 36260, + [GA_HSCH_TAS_CONFIG] =3D 37696, + [GA_PTP_PTP_CFG] =3D 512, + [GA_PTP_PTP_TOD_DOMAINS] =3D 528, + [GA_PTP_PHASE_DETECTOR_CTRL] =3D 628, + [GA_QSYS_CALCFG] =3D 2164, + [GA_QSYS_RAM_CTRL] =3D 2204, + [GA_REW_COMMON] =3D 98304, + [GA_REW_PORT] =3D 49152, + [GA_REW_VOE_PORT_LM_CNT] =3D 90112, + [GA_REW_RAM_CTRL] =3D 93992, + [GA_VOP_RAM_CTRL] =3D 16368, + [GA_XQS_SYSTEM] =3D 5744, + [GA_XQS_QLIMIT_SHR] =3D 6912, +}; + +const unsigned int lan969x_gcnt[GCNT_LAST] =3D { + [GC_ANA_AC_SRC] =3D 67, + [GC_ANA_AC_PGID] =3D 1054, + [GC_ANA_AC_TSN_SF_CFG] =3D 256, + [GC_ANA_AC_STAT_CNT_CFG_PORT] =3D 35, + [GC_ANA_ACL_KEY_SEL] =3D 99, + [GC_ANA_ACL_CNT_A] =3D 1024, + [GC_ANA_ACL_CNT_B] =3D 1024, + [GC_ANA_AC_SDLB_LBGRP_TBL] =3D 5, + [GC_ANA_AC_SDLB_LBSET_TBL] =3D 496, + [GC_ANA_CL_PORT] =3D 35, + [GC_ANA_L2_ISDX_LIMIT] =3D 256, + [GC_ANA_L2_ISDX] =3D 1024, + [GC_ANA_L3_VLAN] =3D 4608, + [GC_ASM_DEV_STATISTICS] =3D 30, + [GC_EACL_ES2_KEY_SELECT_PROFILE] =3D 68, + [GC_EACL_CNT_TBL] =3D 512, + [GC_GCB_SIO_CTRL] =3D 1, + [GC_HSCH_HSCH_CFG] =3D 1120, + [GC_HSCH_HSCH_DWRR] =3D 32, + [GC_PTP_PTP_PINS] =3D 8, + [GC_PTP_PHASE_DETECTOR_CTRL] =3D 8, + [GC_REW_PORT] =3D 35, + [GC_REW_VOE_PORT_LM_CNT] =3D 240, +}; + +const unsigned int lan969x_gsize[GSIZE_LAST] =3D { + [GW_ANA_AC_SRC] =3D 4, + [GW_ANA_L2_COMMON] =3D 712, + [GW_ASM_CFG] =3D 1092, + [GW_CPU_CPU_REGS] =3D 180, + [GW_DEV2G5_PHASE_DETECTOR_CTRL] =3D 12, + [GW_FDMA_FDMA] =3D 448, + [GW_GCB_CHIP_REGS] =3D 180, + [GW_HSCH_TAS_CONFIG] =3D 16, + [GW_PTP_PHASE_DETECTOR_CTRL] =3D 12, + [GW_QSYS_PAUSE_CFG] =3D 988, +}; + +const unsigned int lan969x_fpos[FPOS_LAST] =3D { + [FP_CPU_PROC_CTRL_AARCH64_MODE_ENA] =3D 7, + [FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS] =3D 6, + [FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS] =3D 5, + [FP_CPU_PROC_CTRL_BE_EXCEP_MODE] =3D 4, + [FP_CPU_PROC_CTRL_VINITHI] =3D 3, + [FP_CPU_PROC_CTRL_CFGTE] =3D 2, + [FP_CPU_PROC_CTRL_CP15S_DISABLE] =3D 1, + [FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] =3D 0, + [FP_CPU_PROC_CTRL_L2_FLUSH_REQ] =3D 8, + [FP_DEV2G5_PHAD_CTRL_PHAD_ENA] =3D 5, + [FP_DEV2G5_PHAD_CTRL_PHAD_FAILED] =3D 3, + [FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] =3D 5, + [FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] =3D 4, + [FP_FDMA_CH_CFG_CH_INJ_PORT] =3D 3, + [FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] =3D 27, + [FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] =3D 25, + [FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL] =3D 24, + [FP_PTP_PHAD_CTRL_PHAD_ENA] =3D 5, + [FP_PTP_PHAD_CTRL_PHAD_FAILED] =3D 3, +}; + +const unsigned int lan969x_fsize[FSIZE_LAST] =3D { + [FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK] =3D 30, + [FW_ANA_AC_SRC_CFG_PORT_MASK] =3D 30, + [FW_ANA_AC_PGID_CFG_PORT_MASK] =3D 30, + [FW_ANA_AC_TSN_SF_PORT_NUM] =3D 7, + [FW_ANA_AC_TSN_SF_CFG_TSN_SGID] =3D 8, + [FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] =3D 8, + [FW_ANA_AC_SG_ACCESS_CTRL_SGID] =3D 8, + [FW_ANA_AC_PORT_SGE_CFG_MASK] =3D 17, + [FW_ANA_AC_SDLB_XLB_START_LBSET_START] =3D 9, + [FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] =3D 3, + [FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] =3D 9, + [FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] =3D 9, + [FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] =3D 3, + [FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] =3D 9, + [FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA] =3D 30, + [FW_ANA_L2_DLB_CFG_DLB_IDX] =3D 9, + [FW_ANA_L2_TSN_CFG_TSN_SFID] =3D 8, + [FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK] =3D 30, + [FW_FDMA_CH_CFG_CH_DCB_DB_CNT] =3D 2, + [FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] =3D 7, + [FW_HSCH_SE_CFG_SE_DWRR_CNT] =3D 5, + [FW_HSCH_SE_CONNECT_SE_LEAK_LINK] =3D 14, + [FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] =3D 6, + [FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] =3D 11, + [FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] =3D 14, + [FW_HSCH_FLUSH_CTRL_FLUSH_PORT] =3D 6, + [FW_HSCH_FLUSH_CTRL_FLUSH_HIER] =3D 14, + [FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] =3D 13, + [FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] =3D 8, + [FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] =3D 13, + [FW_PTP_PTP_PIN_INTR_INTR_PTP] =3D 8, + [FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] =3D 8, + [FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] =3D 8, + [FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] =3D 3, + [FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] =3D 6, + [FW_QRES_RES_CFG_WM_HIGH] =3D 11, + [FW_QRES_RES_STAT_MAXUSE] =3D 19, + [FW_QRES_RES_STAT_CUR_INUSE] =3D 19, + [FW_QSYS_PAUSE_CFG_PAUSE_START] =3D 11, + [FW_QSYS_PAUSE_CFG_PAUSE_STOP] =3D 11, + [FW_QSYS_ATOP_ATOP] =3D 11, + [FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] =3D 11, + [FW_REW_RTAG_ETAG_CTRL_IPE_TBL] =3D 6, + [FW_XQS_STAT_CFG_STAT_VIEW] =3D 10, + [FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] =3D 14, + [FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] =3D 14, + [FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] =3D 14, + [FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] =3D 14, +}; diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_regs.c b/drivers/= net/ethernet/microchip/sparx5/sparx5_regs.c index 1db212ce3df7..220e81b714d4 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_regs.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_regs.c @@ -4,7 +4,7 @@ * Copyright (c) 2024 Microchip Technology Inc. */ =20 -/* This file is autogenerated by cml-utils 2024-09-24 14:02:24 +0200. +/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200. * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b */ =20 @@ -140,6 +140,7 @@ const unsigned int sparx5_gsize[GSIZE_LAST] =3D { [GW_ANA_L2_COMMON] =3D 700, [GW_ASM_CFG] =3D 1088, [GW_CPU_CPU_REGS] =3D 204, + [GW_DEV2G5_PHASE_DETECTOR_CTRL] =3D 8, [GW_FDMA_FDMA] =3D 428, [GW_GCB_CHIP_REGS] =3D 424, [GW_HSCH_TAS_CONFIG] =3D 12, @@ -157,6 +158,8 @@ const unsigned int sparx5_fpos[FPOS_LAST] =3D { [FP_CPU_PROC_CTRL_CP15S_DISABLE] =3D 6, [FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] =3D 5, [FP_CPU_PROC_CTRL_L2_FLUSH_REQ] =3D 1, + [FP_DEV2G5_PHAD_CTRL_PHAD_ENA] =3D 7, + [FP_DEV2G5_PHAD_CTRL_PHAD_FAILED] =3D 6, [FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] =3D 7, [FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] =3D 6, [FP_FDMA_CH_CFG_CH_INJ_PORT] =3D 5, diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_regs.h b/drivers/= net/ethernet/microchip/sparx5/sparx5_regs.h index c4e8b581c1f3..ea28130c2341 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_regs.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_regs.h @@ -4,7 +4,7 @@ * Copyright (c) 2024 Microchip Technology Inc. */ =20 -/* This file is autogenerated by cml-utils 2024-09-24 14:02:24 +0200. +/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200. * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b */ =20 @@ -151,6 +151,7 @@ enum sparx5_gsize_enum { GW_ANA_L2_COMMON, GW_ASM_CFG, GW_CPU_CPU_REGS, + GW_DEV2G5_PHASE_DETECTOR_CTRL, GW_FDMA_FDMA, GW_GCB_CHIP_REGS, GW_HSCH_TAS_CONFIG, @@ -169,6 +170,8 @@ enum sparx5_fpos_enum { FP_CPU_PROC_CTRL_CP15S_DISABLE, FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, FP_CPU_PROC_CTRL_L2_FLUSH_REQ, + FP_DEV2G5_PHAD_CTRL_PHAD_ENA, + FP_DEV2G5_PHAD_CTRL_PHAD_FAILED, FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE, FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, FP_FDMA_CH_CFG_CH_INJ_PORT, --=20 2.34.1 From nobody Mon Nov 25 22:51:56 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E1271FDF9D; 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X-CSE-ConnectionGUID: wd8IJW4NTJ64cR86gqDN2Q== X-CSE-MsgGUID: KM0LWttpTwaDnBlVitA/WA== X-IronPort-AV: E=Sophos;i="6.11,227,1725346800"; d="scan'208";a="200831269" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Oct 2024 15:02:36 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 23 Oct 2024 15:02:12 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 23 Oct 2024 15:02:08 -0700 From: Daniel Machon Date: Thu, 24 Oct 2024 00:01:27 +0200 Subject: [PATCH net-next v2 08/15] net: lan969x: add constants to match data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241024-sparx5-lan969x-switch-driver-2-v2-8-a0b5fae88a0f@microchip.com> References: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> In-Reply-To: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Lars Povlsen , Steen Hegelund , , , , , , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: , , , Steen Hegelund , X-Mailer: b4 0.14-dev Add the lan969x constants to match data. These are already used throughout the Sparx5 code (introduced in earlier series [1]), so no need to update any code use. [1] https://lore.kernel.org/netdev/20241004-b4-sparx5-lan969x-switch-driver= -v2-0-d3290f581663@microchip.com/ Reviewed-by: Steen Hegelund Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/lan969x/lan969x.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x.c b/drivers/net= /ethernet/microchip/lan969x/lan969x.c index 0b47e4e66058..19f91e4a9f3e 100644 --- a/drivers/net/ethernet/microchip/lan969x/lan969x.c +++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c @@ -103,11 +103,32 @@ static const struct sparx5_regs lan969x_regs =3D { .fsize =3D lan969x_fsize, }; =20 +static const struct sparx5_consts lan969x_consts =3D { + .n_ports =3D 30, + .n_ports_all =3D 35, + .n_hsch_l1_elems =3D 32, + .n_hsch_queues =3D 4, + .n_lb_groups =3D 5, + .n_pgids =3D 1054, /* (1024 + n_ports) */ + .n_sio_clks =3D 1, + .n_own_upsids =3D 1, + .n_auto_cals =3D 4, + .n_filters =3D 256, + .n_gates =3D 256, + .n_sdlbs =3D 496, + .n_dsm_cal_taxis =3D 5, + .buf_size =3D 1572864, + .qres_max_prio_idx =3D 315, + .qres_max_colour_idx =3D 323, + .tod_pin =3D 4, +}; + const struct sparx5_match_data lan969x_desc =3D { .iomap =3D lan969x_main_iomap, .iomap_size =3D ARRAY_SIZE(lan969x_main_iomap), .ioranges =3D 2, .regs =3D &lan969x_regs, + .consts =3D &lan969x_consts, }; EXPORT_SYMBOL_GPL(lan969x_desc); =20 --=20 2.34.1 From nobody Mon Nov 25 22:51:56 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C13101FE0E6; Wed, 23 Oct 2024 22:02:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729720962; cv=none; b=QhCBkkSvtEJ7kqZX9PXocu9V+Xv0ZyFGkyyw4bXIeqbu9r9Fz3kFIybEYVki9vHOy/hl2QpeDF/YyrT/4jrjDHTBRf25zBd2Nrtf9rrJxAFb09QAX9wyA5O2BTS3hMjAQOEm6RMSXDXUfdsB4A9NGryeDkM+v6VhH8kJBMRDgIc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Wed, 23 Oct 2024 15:02:16 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 23 Oct 2024 15:02:12 -0700 From: Daniel Machon Date: Thu, 24 Oct 2024 00:01:28 +0200 Subject: [PATCH net-next v2 09/15] net: lan969x: add lan969x ops to match data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241024-sparx5-lan969x-switch-driver-2-v2-9-a0b5fae88a0f@microchip.com> References: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> In-Reply-To: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Lars Povlsen , Steen Hegelund , , , , , , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: , , , Steen Hegelund , X-Mailer: b4 0.14-dev Add a bunch of small lan969x ops in bulk. These ops are explained in detail in a previous series [1]. [1] https://lore.kernel.org/netdev/20241004-b4-sparx5-lan969x-switch-driver= -v2-8-d3290f581663@microchip.com/ Reviewed-by: Steen Hegelund Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/lan969x/lan969x.c | 122 +++++++++++++++++++= ++++ drivers/net/ethernet/microchip/lan969x/lan969x.h | 28 ++++++ 2 files changed, 150 insertions(+) diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x.c b/drivers/net= /ethernet/microchip/lan969x/lan969x.c index 19f91e4a9f3e..2c2b86f9144e 100644 --- a/drivers/net/ethernet/microchip/lan969x/lan969x.c +++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c @@ -6,6 +6,9 @@ =20 #include "lan969x.h" =20 +#define LAN969X_SDLB_GRP_CNT 5 +#define LAN969X_HSCH_LEAK_GRP_CNT 4 + static const struct sparx5_main_io_resource lan969x_main_iomap[] =3D { { TARGET_CPU, 0xc0000, 0 }, /* 0xe00c0000 */ { TARGET_FDMA, 0xc0400, 0 }, /* 0xe00c0400 */ @@ -92,6 +95,112 @@ static const struct sparx5_main_io_resource lan969x_mai= n_iomap[] =3D { { TARGET_ASM, 0x3200000, 1 }, /* 0xe3200000 */ }; =20 +static struct sparx5_sdlb_group lan969x_sdlb_groups[LAN969X_SDLB_GRP_CNT] = =3D { + { 1000000000, 8192 / 2, 64 }, /* 1 G */ + { 500000000, 8192 / 2, 64 }, /* 500 M */ + { 100000000, 8192 / 4, 64 }, /* 100 M */ + { 50000000, 8192 / 4, 64 }, /* 50 M */ + { 5000000, 8192 / 8, 64 }, /* 10 M */ +}; + +static u32 lan969x_hsch_max_group_rate[LAN969X_HSCH_LEAK_GRP_CNT] =3D { + 655355, 1048568, 6553550, 10485680 +}; + +static struct sparx5_sdlb_group *lan969x_get_sdlb_group(int idx) +{ + return &lan969x_sdlb_groups[idx]; +} + +static u32 lan969x_get_hsch_max_group_rate(int grp) +{ + return lan969x_hsch_max_group_rate[grp]; +} + +static u32 lan969x_get_dev_mode_bit(struct sparx5 *sparx5, int port) +{ + if (lan969x_port_is_2g5(port) || lan969x_port_is_5g(port)) + return port; + + /* 10G */ + switch (port) { + case 0: + return 12; + case 4: + return 13; + case 8: + return 14; + case 12: + return 0; + default: + return port; + } +} + +static u32 lan969x_port_dev_mapping(struct sparx5 *sparx5, int port) +{ + if (lan969x_port_is_5g(port)) { + switch (port) { + case 9: + return 0; + case 13: + return 1; + case 17: + return 2; + case 21: + return 3; + } + } + + if (lan969x_port_is_10g(port)) { + switch (port) { + case 0: + return 0; + case 4: + return 1; + case 8: + return 2; + case 12: + return 3; + case 16: + return 4; + case 20: + return 5; + case 24: + return 6; + case 25: + return 7; + case 26: + return 8; + case 27: + return 9; + } + } + + /* 2g5 port */ + return port; +} + +static int lan969x_port_mux_set(struct sparx5 *sparx5, struct sparx5_port = *port, + struct sparx5_port_config *conf) +{ + u32 portno =3D port->portno; + u32 inst; + + if (port->conf.portmode =3D=3D conf->portmode) + return 0; /* Nothing to do */ + + switch (conf->portmode) { + case PHY_INTERFACE_MODE_QSGMII: /* QSGMII: 4x2G5 devices. Mode Q' */ + inst =3D (portno - portno % 4) / 4; + spx5_rmw(BIT(inst), BIT(inst), sparx5, PORT_CONF_QSGMII_ENA); + break; + default: + break; + } + return 0; +} + static const struct sparx5_regs lan969x_regs =3D { .tsize =3D lan969x_tsize, .gaddr =3D lan969x_gaddr, @@ -123,12 +232,25 @@ static const struct sparx5_consts lan969x_consts =3D { .tod_pin =3D 4, }; =20 +static const struct sparx5_ops lan969x_ops =3D { + .is_port_2g5 =3D &lan969x_port_is_2g5, + .is_port_5g =3D &lan969x_port_is_5g, + .is_port_10g =3D &lan969x_port_is_10g, + .is_port_25g =3D &lan969x_port_is_25g, + .get_port_dev_index =3D &lan969x_port_dev_mapping, + .get_port_dev_bit =3D &lan969x_get_dev_mode_bit, + .get_hsch_max_group_rate =3D &lan969x_get_hsch_max_group_rate, + .get_sdlb_group =3D &lan969x_get_sdlb_group, + .set_port_mux =3D &lan969x_port_mux_set, +}; + const struct sparx5_match_data lan969x_desc =3D { .iomap =3D lan969x_main_iomap, .iomap_size =3D ARRAY_SIZE(lan969x_main_iomap), .ioranges =3D 2, .regs =3D &lan969x_regs, .consts =3D &lan969x_consts, + .ops =3D &lan969x_ops, }; EXPORT_SYMBOL_GPL(lan969x_desc); =20 diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x.h b/drivers/net= /ethernet/microchip/lan969x/lan969x.h index 3b4c9ea30071..ee890b26ea79 100644 --- a/drivers/net/ethernet/microchip/lan969x/lan969x.h +++ b/drivers/net/ethernet/microchip/lan969x/lan969x.h @@ -23,4 +23,32 @@ extern const unsigned int lan969x_gsize[GSIZE_LAST]; extern const unsigned int lan969x_fpos[FPOS_LAST]; extern const unsigned int lan969x_fsize[FSIZE_LAST]; =20 +static inline bool lan969x_port_is_2g5(int portno) +{ + return portno =3D=3D 1 || portno =3D=3D 2 || portno =3D=3D 3 || + portno =3D=3D 5 || portno =3D=3D 6 || portno =3D=3D 7 || + portno =3D=3D 10 || portno =3D=3D 11 || portno =3D=3D 14 || + portno =3D=3D 15 || portno =3D=3D 18 || portno =3D=3D 19 || + portno =3D=3D 22 || portno =3D=3D 23; +} + +static inline bool lan969x_port_is_5g(int portno) +{ + return portno =3D=3D 9 || portno =3D=3D 13 || portno =3D=3D 17 || + portno =3D=3D 21; +} + +static inline bool lan969x_port_is_10g(int portno) +{ + return portno =3D=3D 0 || portno =3D=3D 4 || portno =3D=3D 8 || + portno =3D=3D 12 || portno =3D=3D 16 || portno =3D=3D 20 || + portno =3D=3D 24 || portno =3D=3D 25 || portno =3D=3D 26 || + portno =3D=3D 27; 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Wed, 23 Oct 2024 15:02:17 -0700 From: Daniel Machon Date: Thu, 24 Oct 2024 00:01:29 +0200 Subject: [PATCH net-next v2 10/15] net: lan969x: add PTP handler function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241024-sparx5-lan969x-switch-driver-2-v2-10-a0b5fae88a0f@microchip.com> References: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> In-Reply-To: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Lars Povlsen , Steen Hegelund , , , , , , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: , , , Steen Hegelund , X-Mailer: b4 0.14-dev Add PTP IRQ handler for lan969x. This is required, as the PTP registers are placed in two different targets on Sparx5 and lan969x. The implementation is otherwise the same as on Sparx5. Also, expose sparx5_get_hwtimestamp() for use by lan969x. Reviewed-by: Steen Hegelund Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/lan969x/lan969x.c | 90 ++++++++++++++++++= ++++ .../net/ethernet/microchip/sparx5/sparx5_main.h | 5 ++ drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c | 9 +-- 3 files changed, 99 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x.c b/drivers/net= /ethernet/microchip/lan969x/lan969x.c index 2c2b86f9144e..a3b40e09b947 100644 --- a/drivers/net/ethernet/microchip/lan969x/lan969x.c +++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c @@ -201,6 +201,95 @@ static int lan969x_port_mux_set(struct sparx5 *sparx5,= struct sparx5_port *port, return 0; } =20 +static irqreturn_t lan969x_ptp_irq_handler(int irq, void *args) +{ + int budget =3D SPARX5_MAX_PTP_ID; + struct sparx5 *sparx5 =3D args; + + while (budget--) { + struct sk_buff *skb, *skb_tmp, *skb_match =3D NULL; + struct skb_shared_hwtstamps shhwtstamps; + struct sparx5_port *port; + struct timespec64 ts; + unsigned long flags; + u32 val, id, txport; + u32 delay; + + val =3D spx5_rd(sparx5, PTP_TWOSTEP_CTRL); + + /* Check if a timestamp can be retrieved */ + if (!(val & PTP_TWOSTEP_CTRL_PTP_VLD)) + break; + + WARN_ON(val & PTP_TWOSTEP_CTRL_PTP_OVFL); + + if (!(val & PTP_TWOSTEP_CTRL_STAMP_TX)) + continue; + + /* Retrieve the ts Tx port */ + txport =3D PTP_TWOSTEP_CTRL_STAMP_PORT_GET(val); + + /* Retrieve its associated skb */ + port =3D sparx5->ports[txport]; + + /* Retrieve the delay */ + delay =3D spx5_rd(sparx5, PTP_TWOSTEP_STAMP_NSEC); + delay =3D PTP_TWOSTEP_STAMP_NSEC_NS_GET(delay); + + /* Get next timestamp from fifo, which needs to be the + * rx timestamp which represents the id of the frame + */ + spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), + PTP_TWOSTEP_CTRL_PTP_NXT, + sparx5, PTP_TWOSTEP_CTRL); + + val =3D spx5_rd(sparx5, PTP_TWOSTEP_CTRL); + + /* Check if a timestamp can be retrieved */ + if (!(val & PTP_TWOSTEP_CTRL_PTP_VLD)) + break; + + /* Read RX timestamping to get the ID */ + id =3D spx5_rd(sparx5, PTP_TWOSTEP_STAMP_NSEC); + id <<=3D 8; + id |=3D spx5_rd(sparx5, PTP_TWOSTEP_STAMP_SUBNS); + + spin_lock_irqsave(&port->tx_skbs.lock, flags); + skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { + if (SPARX5_SKB_CB(skb)->ts_id !=3D id) + continue; + + __skb_unlink(skb, &port->tx_skbs); + skb_match =3D skb; + break; + } + spin_unlock_irqrestore(&port->tx_skbs.lock, flags); + + /* Next ts */ + spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), + PTP_TWOSTEP_CTRL_PTP_NXT, + sparx5, PTP_TWOSTEP_CTRL); + + if (WARN_ON(!skb_match)) + continue; + + spin_lock(&sparx5->ptp_ts_id_lock); + sparx5->ptp_skbs--; + spin_unlock(&sparx5->ptp_ts_id_lock); + + /* Get the h/w timestamp */ + sparx5_get_hwtimestamp(sparx5, &ts, delay); + + /* Set the timestamp in the skb */ + shhwtstamps.hwtstamp =3D ktime_set(ts.tv_sec, ts.tv_nsec); + skb_tstamp_tx(skb_match, &shhwtstamps); + + dev_kfree_skb_any(skb_match); + } + + return IRQ_HANDLED; +} + static const struct sparx5_regs lan969x_regs =3D { .tsize =3D lan969x_tsize, .gaddr =3D lan969x_gaddr, @@ -242,6 +331,7 @@ static const struct sparx5_ops lan969x_ops =3D { .get_hsch_max_group_rate =3D &lan969x_get_hsch_max_group_rate, .get_sdlb_group =3D &lan969x_get_sdlb_group, .set_port_mux =3D &lan969x_port_mux_set, + .ptp_irq_handler =3D &lan969x_ptp_irq_handler, }; =20 const struct sparx5_match_data lan969x_desc =3D { diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h b/drivers/= net/ethernet/microchip/sparx5/sparx5_main.h index 15f5d38776c4..3f66045c57ef 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h @@ -114,6 +114,8 @@ enum sparx5_vlan_port_type { #define SPX5_DSM_CAL_LEN 64 #define SPX5_DSM_CAL_MAX_DEVS_PER_TAXI 13 =20 +#define SPARX5_MAX_PTP_ID 512 + struct sparx5; =20 struct sparx5_calendar_data { @@ -499,6 +501,9 @@ void sparx5_ptp_txtstamp_release(struct sparx5_port *po= rt, struct sk_buff *skb); irqreturn_t sparx5_ptp_irq_handler(int irq, void *args); int sparx5_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts= ); +void sparx5_get_hwtimestamp(struct sparx5 *sparx5, + struct timespec64 *ts, + u32 nsec); =20 /* sparx5_vcap_impl.c */ int sparx5_vcap_init(struct sparx5 *sparx5); diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c b/drivers/n= et/ethernet/microchip/sparx5/sparx5_ptp.c index a511f14312f1..1c2903700a9c 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c @@ -11,8 +11,6 @@ #include "sparx5_main_regs.h" #include "sparx5_main.h" =20 -#define SPARX5_MAX_PTP_ID 512 - #define TOD_ACC_PIN 0x4 =20 enum { @@ -275,9 +273,9 @@ void sparx5_ptp_txtstamp_release(struct sparx5_port *po= rt, spin_unlock_irqrestore(&sparx5->ptp_ts_id_lock, flags); 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23 Oct 2024 15:02:55 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 23 Oct 2024 15:02:25 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 23 Oct 2024 15:02:21 -0700 From: Daniel Machon Date: Thu, 24 Oct 2024 00:01:30 +0200 Subject: [PATCH net-next v2 11/15] net: lan969x: add function for calculating the DSM calendar Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241024-sparx5-lan969x-switch-driver-2-v2-11-a0b5fae88a0f@microchip.com> References: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> In-Reply-To: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Lars Povlsen , Steen Hegelund , , , , , , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: , , , Steen Hegelund , X-Mailer: b4 0.14-dev Lan969x has support for RedBox / HSR / PRP (not implemented yet). In order to accommodate for this in the future, we need to give lan969x it's own function for calculating the DSM calendar. The function calculates the calendar for each taxi bus. The calendar is used for bandwidth allocation towards the ports attached to the taxi bus. A calendar configuration consists of up-to 64 slots, which may be allocated to ports or left unused. Each slot accounts for 1 clock cycle. Also expose sparx5_cal_speed_to_value(), sparx5_get_port_cal_speed, sparx5_cal_bw and SPX5_DSM_CAL_EMPTY for use by lan969x. Reviewed-by: Steen Hegelund Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/lan969x/Makefile | 2 +- drivers/net/ethernet/microchip/lan969x/lan969x.c | 1 + drivers/net/ethernet/microchip/lan969x/lan969x.h | 3 + .../ethernet/microchip/lan969x/lan969x_calendar.c | 191 +++++++++++++++++= ++++ .../ethernet/microchip/sparx5/sparx5_calendar.c | 20 +-- .../net/ethernet/microchip/sparx5/sparx5_main.h | 15 ++ 6 files changed, 215 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan969x/Makefile b/drivers/net/= ethernet/microchip/lan969x/Makefile index ff40e7e5d420..82d318a7219c 100644 --- a/drivers/net/ethernet/microchip/lan969x/Makefile +++ b/drivers/net/ethernet/microchip/lan969x/Makefile @@ -5,7 +5,7 @@ =20 obj-$(CONFIG_LAN969X_SWITCH) +=3D lan969x-switch.o =20 -lan969x-switch-y :=3D lan969x_regs.o lan969x.o +lan969x-switch-y :=3D lan969x_regs.o lan969x.o lan969x_calendar.o =20 # Provide include files ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/microchip/fdma diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x.c b/drivers/net= /ethernet/microchip/lan969x/lan969x.c index a3b40e09b947..79e5bcefbd73 100644 --- a/drivers/net/ethernet/microchip/lan969x/lan969x.c +++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c @@ -332,6 +332,7 @@ static const struct sparx5_ops lan969x_ops =3D { .get_sdlb_group =3D &lan969x_get_sdlb_group, .set_port_mux =3D &lan969x_port_mux_set, .ptp_irq_handler =3D &lan969x_ptp_irq_handler, + .dsm_calendar_calc =3D &lan969x_dsm_calendar_calc, }; =20 const struct sparx5_match_data lan969x_desc =3D { diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x.h b/drivers/net= /ethernet/microchip/lan969x/lan969x.h index ee890b26ea79..7ce047ad9ca4 100644 --- a/drivers/net/ethernet/microchip/lan969x/lan969x.h +++ b/drivers/net/ethernet/microchip/lan969x/lan969x.h @@ -51,4 +51,7 @@ static inline bool lan969x_port_is_25g(int portno) return false; } =20 +/* lan969x_calendar.c */ +int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, + struct sparx5_calendar_data *data); #endif diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x_calendar.c b/dr= ivers/net/ethernet/microchip/lan969x/lan969x_calendar.c new file mode 100644 index 000000000000..e857640df185 --- /dev/null +++ b/drivers/net/ethernet/microchip/lan969x/lan969x_calendar.c @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Microchip lan969x Switch driver + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + */ + +#include "lan969x.h" + +#define LAN969X_DSM_CAL_DEVS_PER_TAXI 10 +#define LAN969X_DSM_CAL_TAXIS 5 + +enum lan969x_dsm_cal_dev { + DSM_CAL_DEV_2G5, + DSM_CAL_DEV_5G, + DSM_CAL_DEV_10G, + DSM_CAL_DEV_OTHER, /* 1G or less */ + DSM_CAL_DEV_MAX +}; + +/* Each entry in the following struct defines properties for a given speed + * (10G, 5G, 2.5G, or 1G or less). + */ +struct lan969x_dsm_cal_dev_speed { + /* Number of devices that requires this speed. */ + u32 n_devs; + + /* Array of devices that requires this speed. */ + u32 devs[LAN969X_DSM_CAL_DEVS_PER_TAXI]; + + /* Number of slots required for one device running this speed. */ + u32 n_slots; + + /* Gap between two slots for one device running this speed. */ + u32 gap; +}; + +static u32 +lan969x_taxi_ports[LAN969X_DSM_CAL_TAXIS][LAN969X_DSM_CAL_DEVS_PER_TAXI] = =3D { + { 0, 4, 1, 2, 3, 5, 6, 7, 28, 29 }, + { 8, 12, 9, 13, 10, 11, 14, 15, 99, 99 }, + { 16, 20, 17, 21, 18, 19, 22, 23, 99, 99 }, + { 24, 25, 99, 99, 99, 99, 99, 99, 99, 99 }, + { 26, 27, 99, 99, 99, 99, 99, 99, 99, 99 } +}; + +static int lan969x_dsm_cal_idx_get(u32 *calendar, u32 cal_len, u32 *cal_id= x) +{ + if (*cal_idx >=3D cal_len) + return -EINVAL; + + do { + if (calendar[*cal_idx] =3D=3D SPX5_DSM_CAL_EMPTY) + return 0; + + (*cal_idx)++; + } while (*cal_idx < cal_len); + + return -ENOENT; +} + +static enum lan969x_dsm_cal_dev lan969x_dsm_cal_get_dev(int speed) +{ + return (speed =3D=3D 10000 ? DSM_CAL_DEV_10G : + speed =3D=3D 5000 ? DSM_CAL_DEV_5G : + speed =3D=3D 2500 ? DSM_CAL_DEV_2G5 : + DSM_CAL_DEV_OTHER); +} + +static int lan969x_dsm_cal_get_speed(enum lan969x_dsm_cal_dev dev) +{ + return (dev =3D=3D DSM_CAL_DEV_10G ? 10000 : + dev =3D=3D DSM_CAL_DEV_5G ? 5000 : + dev =3D=3D DSM_CAL_DEV_2G5 ? 2500 : + 1000); +} + +int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, + struct sparx5_calendar_data *data) +{ + struct lan969x_dsm_cal_dev_speed dev_speeds[DSM_CAL_DEV_MAX] =3D {}; + u32 cal_len, n_slots, taxi_bw, n_devs =3D 0, required_bw =3D 0; + struct lan969x_dsm_cal_dev_speed *speed; + int err; + + /* Maximum bandwidth for this taxi */ + taxi_bw =3D (128 * 1000000) / sparx5_clk_period(sparx5->coreclock); + + memcpy(data->taxi_ports, &lan969x_taxi_ports[taxi], + LAN969X_DSM_CAL_DEVS_PER_TAXI * sizeof(u32)); + + for (int i =3D 0; i < LAN969X_DSM_CAL_DEVS_PER_TAXI; i++) { + u32 portno =3D data->taxi_ports[i]; + enum sparx5_cal_bw bw; + + bw =3D sparx5_get_port_cal_speed(sparx5, portno); + + if (portno < sparx5->data->consts->n_ports_all) + data->taxi_speeds[i] =3D sparx5_cal_speed_to_value(bw); + else + data->taxi_speeds[i] =3D 0; + } + + /* Determine the different port types (10G, 5G, 2.5G, <=3D 1G) in the + * this taxi map. + */ + for (int i =3D 0; i < LAN969X_DSM_CAL_DEVS_PER_TAXI; i++) { + u32 taxi_speed =3D data->taxi_speeds[i]; + enum lan969x_dsm_cal_dev dev; + + if (taxi_speed =3D=3D 0) + continue; + + required_bw +=3D taxi_speed; + + dev =3D lan969x_dsm_cal_get_dev(taxi_speed); + speed =3D &dev_speeds[dev]; + speed->devs[speed->n_devs++] =3D i; + n_devs++; + } + + if (required_bw > taxi_bw) { + pr_err("Required bandwidth: %u is higher than total taxi bandwidth: %u", + required_bw, taxi_bw); + return -EINVAL; + } + + if (n_devs =3D=3D 0) { + data->schedule[0] =3D SPX5_DSM_CAL_EMPTY; + return 0; + } + + cal_len =3D n_devs; + + /* Search for a calendar length that fits all active devices. */ + while (cal_len < SPX5_DSM_CAL_LEN) { + u32 bw_per_slot =3D taxi_bw / cal_len; + + n_slots =3D 0; + + for (int i =3D 0; i < DSM_CAL_DEV_MAX; i++) { + speed =3D &dev_speeds[i]; + + if (speed->n_devs =3D=3D 0) + continue; + + required_bw =3D lan969x_dsm_cal_get_speed(i); + speed->n_slots =3D DIV_ROUND_UP(required_bw, bw_per_slot); + + if (speed->n_slots) + speed->gap =3D DIV_ROUND_UP(cal_len, + speed->n_slots); + else + speed->gap =3D 0; + + n_slots +=3D speed->n_slots * speed->n_devs; + } + + if (n_slots <=3D cal_len) + break; /* Found a suitable calendar length. */ + + /* Not good enough yet. */ + cal_len =3D n_slots; + } + + if (cal_len > SPX5_DSM_CAL_LEN) { + pr_err("Invalid length: %u for taxi: %u", cal_len, taxi); + return -EINVAL; + } + + for (u32 i =3D 0; i < SPX5_DSM_CAL_LEN; i++) + data->schedule[i] =3D SPX5_DSM_CAL_EMPTY; + + /* Place the remaining devices */ + for (u32 i =3D 0; i < DSM_CAL_DEV_MAX; i++) { + speed =3D &dev_speeds[i]; + for (u32 dev =3D 0; dev < speed->n_devs; dev++) { + u32 idx =3D 0; + + for (n_slots =3D 0; n_slots < speed->n_slots; n_slots++) { + err =3D lan969x_dsm_cal_idx_get(data->schedule, + cal_len, &idx); + if (err) + return err; + data->schedule[idx] =3D speed->devs[dev]; + idx +=3D speed->gap; + } + } + } + + return 0; +} diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c b/driv= ers/net/ethernet/microchip/sparx5/sparx5_calendar.c index edc03b6ebf34..64c5ed70cc6b 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c @@ -15,7 +15,6 @@ #define SPX5_CALBITS_PER_PORT 3 /* Bit per port in calendar reg= ister */ =20 /* DSM calendar information */ -#define SPX5_DSM_CAL_EMPTY 0xFFFF #define SPX5_DSM_CAL_TAXIS 8 #define SPX5_DSM_CAL_BW_LOSS 553 =20 @@ -74,18 +73,6 @@ static u32 sparx5_target_bandwidth(struct sparx5 *sparx5) } } =20 -/* This is used in calendar configuration */ -enum sparx5_cal_bw { - SPX5_CAL_SPEED_NONE =3D 0, - SPX5_CAL_SPEED_1G =3D 1, - SPX5_CAL_SPEED_2G5 =3D 2, - SPX5_CAL_SPEED_5G =3D 3, - SPX5_CAL_SPEED_10G =3D 4, - SPX5_CAL_SPEED_25G =3D 5, - SPX5_CAL_SPEED_0G5 =3D 6, - SPX5_CAL_SPEED_12G5 =3D 7 -}; - static u32 sparx5_clk_to_bandwidth(enum sparx5_core_clockfreq cclock) { switch (cclock) { @@ -98,7 +85,7 @@ static u32 sparx5_clk_to_bandwidth(enum sparx5_core_clock= freq cclock) return 0; } =20 -static u32 sparx5_cal_speed_to_value(enum sparx5_cal_bw speed) +u32 sparx5_cal_speed_to_value(enum sparx5_cal_bw speed) { switch (speed) { case SPX5_CAL_SPEED_1G: return 1000; @@ -111,6 +98,7 @@ static u32 sparx5_cal_speed_to_value(enum sparx5_cal_bw = speed) default: return 0; } } +EXPORT_SYMBOL_GPL(sparx5_cal_speed_to_value); =20 static u32 sparx5_bandwidth_to_calendar(u32 bw) { @@ -128,8 +116,7 @@ static u32 sparx5_bandwidth_to_calendar(u32 bw) } } =20 -static enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, - u32 portno) +enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, u32 po= rtno) { struct sparx5_port *port; =20 @@ -163,6 +150,7 @@ static enum sparx5_cal_bw sparx5_get_port_cal_speed(str= uct sparx5 *sparx5, return SPX5_CAL_SPEED_NONE; return sparx5_bandwidth_to_calendar(port->conf.bandwidth); } +EXPORT_SYMBOL_GPL(sparx5_get_port_cal_speed); =20 /* Auto configure the QSYS calendar based on port configuration */ int sparx5_config_auto_calendar(struct sparx5 *sparx5) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h b/drivers/= net/ethernet/microchip/sparx5/sparx5_main.h index 3f66045c57ef..1828e2a7d610 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h @@ -63,6 +63,18 @@ enum sparx5_vlan_port_type { SPX5_VLAN_PORT_TYPE_S_CUSTOM /* S-port using custom type */ }; =20 +/* This is used in calendar configuration */ +enum sparx5_cal_bw { + SPX5_CAL_SPEED_NONE =3D 0, + SPX5_CAL_SPEED_1G =3D 1, + SPX5_CAL_SPEED_2G5 =3D 2, + SPX5_CAL_SPEED_5G =3D 3, + SPX5_CAL_SPEED_10G =3D 4, + SPX5_CAL_SPEED_25G =3D 5, + SPX5_CAL_SPEED_0G5 =3D 6, + SPX5_CAL_SPEED_12G5 =3D 7 +}; + #define SPX5_PORTS 65 #define SPX5_PORTS_ALL 70 /* Total number of ports */ =20 @@ -113,6 +125,7 @@ enum sparx5_vlan_port_type { =20 #define SPX5_DSM_CAL_LEN 64 #define SPX5_DSM_CAL_MAX_DEVS_PER_TAXI 13 +#define SPX5_DSM_CAL_EMPTY 0xFFFF =20 #define SPARX5_MAX_PTP_ID 512 =20 @@ -454,6 +467,8 @@ int sparx5_config_auto_calendar(struct sparx5 *sparx5); int sparx5_config_dsm_calendar(struct sparx5 *sparx5); int sparx5_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, struct sparx5_calendar_data *data); +u32 sparx5_cal_speed_to_value(enum sparx5_cal_bw speed); +enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, u32 po= rtno); =20 =20 /* sparx5_ethtool.c */ --=20 2.34.1 From nobody Mon Nov 25 22:51:56 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 953BB1FEFBA; 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X-CSE-ConnectionGUID: oMPErp9qRFmiMc0P9W4Bgw== X-CSE-MsgGUID: JoEFOq/hRbaehMbIrrjw7A== X-IronPort-AV: E=Sophos;i="6.11,227,1725346800"; d="scan'208";a="264507058" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Oct 2024 15:02:56 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 23 Oct 2024 15:02:29 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 23 Oct 2024 15:02:25 -0700 From: Daniel Machon Date: Thu, 24 Oct 2024 00:01:31 +0200 Subject: [PATCH net-next v2 12/15] net: sparx5: use is_sparx5() macro throughout Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241024-sparx5-lan969x-switch-driver-2-v2-12-a0b5fae88a0f@microchip.com> References: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> In-Reply-To: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Lars Povlsen , Steen Hegelund , , , , , , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: , , , Steen Hegelund , X-Mailer: b4 0.14-dev Use the is_sparx5() macro (introduced in earlier series [1]), in places where we need to handle things a bit differently on lan969x. These places are: - in sparx5_dsm_calendar_update() we need to switch the calendar from a to b on lan969x. - in sparx5_start() we need to make sure the HSCH_SYS_CLK_PER register is only touched on Sparx5. - in sparx5_start() we need to disable VCAP and FDMA for lan969x (will come in later series). - in sparx5_mirror_port_get() we must make sure the ANA_AC_PROBE_PORT_CFG1 register is only read on Sparx5. - sparx5_netdev.c and sparx5_packet.c we need to use different IFH (Internal Frame Header) offsets for lan969x. - in sparx5_port_fifo_sz() we must bail out on lan969x. - in sparx5_port_config_low_set() we must configure the phase detection registers. - in sparx5_port_config() and sparx5_port_init() we must do some additional configuration of the port devices. - in sparx5_dwrr_conf_set() we must derive the scheduling layer [1] https://lore.kernel.org/netdev/20241004-b4-sparx5-lan969x-switch-driver= -v2-8-d3290f581663@microchip.com/ Reviewed-by: Steen Hegelund Signed-off-by: Daniel Machon --- .../ethernet/microchip/sparx5/sparx5_calendar.c | 21 +++++++++- .../net/ethernet/microchip/sparx5/sparx5_main.c | 21 +++++----- .../net/ethernet/microchip/sparx5/sparx5_mirror.c | 10 ++++- .../net/ethernet/microchip/sparx5/sparx5_netdev.c | 17 ++++---- .../net/ethernet/microchip/sparx5/sparx5_packet.c | 3 +- .../net/ethernet/microchip/sparx5/sparx5_port.c | 46 ++++++++++++++++++= ++++ drivers/net/ethernet/microchip/sparx5/sparx5_qos.c | 3 +- 7 files changed, 99 insertions(+), 22 deletions(-) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c b/driv= ers/net/ethernet/microchip/sparx5/sparx5_calendar.c index 64c5ed70cc6b..5fe941c66c17 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c @@ -531,8 +531,18 @@ static int sparx5_dsm_calendar_check(struct sparx5 *sp= arx5, static int sparx5_dsm_calendar_update(struct sparx5 *sparx5, u32 taxi, struct sparx5_calendar_data *data) { - u32 idx; - u32 cal_len =3D sparx5_dsm_cal_len(data->schedule), len; + u32 cal_len =3D sparx5_dsm_cal_len(data->schedule), len, idx; + + if (!is_sparx5(sparx5)) { + u32 val, act; + + val =3D spx5_rd(sparx5, DSM_TAXI_CAL_CFG(taxi)); + act =3D DSM_TAXI_CAL_CFG_CAL_SEL_STAT_GET(val); + + spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_SEL_SET(!act), + DSM_TAXI_CAL_CFG_CAL_PGM_SEL, + sparx5, DSM_TAXI_CAL_CFG(taxi)); + } =20 spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(1), DSM_TAXI_CAL_CFG_CAL_PGM_ENA, @@ -556,6 +566,13 @@ static int sparx5_dsm_calendar_update(struct sparx5 *s= parx5, u32 taxi, DSM_TAXI_CAL_CFG(taxi))); if (len !=3D cal_len - 1) goto update_err; + + if (!is_sparx5(sparx5)) { + spx5_rmw(DSM_TAXI_CAL_CFG_CAL_SWITCH_SET(1), + DSM_TAXI_CAL_CFG_CAL_SWITCH, + sparx5, DSM_TAXI_CAL_CFG(taxi)); + } + return 0; update_err: dev_err(sparx5->dev, "Incorrect calendar length: %u\n", len); diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c b/drivers/= net/ethernet/microchip/sparx5/sparx5_main.c index 9da755c8b894..741404ccd8f5 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c @@ -538,10 +538,11 @@ static int sparx5_init_coreclock(struct sparx5 *sparx= 5) sparx5->coreclock =3D freq; clk_period =3D sparx5_clk_period(freq); =20 - spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100), - HSCH_SYS_CLK_PER_100PS, - sparx5, - HSCH_SYS_CLK_PER); + if (is_sparx5(sparx5)) + spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100), + HSCH_SYS_CLK_PER_100PS, + sparx5, + HSCH_SYS_CLK_PER); =20 spx5_rmw(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, @@ -731,15 +732,17 @@ static int sparx5_start(struct sparx5 *sparx5) if (err) return err; =20 - err =3D sparx5_vcap_init(sparx5); - if (err) { - sparx5_unregister_notifier_blocks(sparx5); - return err; + if (is_sparx5(sparx5)) { + err =3D sparx5_vcap_init(sparx5); + if (err) { + sparx5_unregister_notifier_blocks(sparx5); + return err; + } } =20 /* Start Frame DMA with fallback to register based INJ/XTR */ err =3D -ENXIO; - if (sparx5->fdma_irq >=3D 0) { + if (sparx5->fdma_irq >=3D 0 && is_sparx5(sparx5)) { if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0) err =3D devm_request_threaded_irq(sparx5->dev, sparx5->fdma_irq, diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c b/driver= s/net/ethernet/microchip/sparx5/sparx5_mirror.c index 459a53676ae9..9806729e9c62 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c @@ -24,8 +24,14 @@ static u32 sparx5_mirror_to_dir(bool ingress) /* Get ports belonging to this mirror */ static u64 sparx5_mirror_port_get(struct sparx5 *sparx5, u32 idx) { - return (u64)spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG1(idx)) << 32 | - spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG(idx)); + u64 val; + + val =3D spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG(idx)); + + if (is_sparx5(sparx5)) + val |=3D (u64)spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG1(idx)) << 32; + + return val; } =20 /* Add port to mirror (only front ports) */ diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c b/driver= s/net/ethernet/microchip/sparx5/sparx5_netdev.c index a94d9a540bd3..1d34af78166a 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c @@ -64,16 +64,16 @@ void sparx5_set_port_ifh(struct sparx5 *sparx5, void *i= fh_hdr, u16 portno) /* MISC.CPU_MASK/DPORT =3D Destination port */ ifh_encode_bitfield(ifh_hdr, portno, 29, 8); /* MISC.PIPELINE_PT */ - ifh_encode_bitfield(ifh_hdr, 16, 37, 5); + ifh_encode_bitfield(ifh_hdr, is_sparx5(sparx5) ? 16 : 17, 37, 5); /* MISC.PIPELINE_ACT */ ifh_encode_bitfield(ifh_hdr, 1, 42, 3); /* FWD.SRC_PORT =3D CPU */ ifh_encode_bitfield(ifh_hdr, sparx5_get_pgid(sparx5, SPX5_PORT_CPU_0), - 46, 7); + 46, is_sparx5(sparx5) ? 7 : 6); /* FWD.SFLOW_ID (disable SFlow sampling) */ - ifh_encode_bitfield(ifh_hdr, 124, 57, 7); + ifh_encode_bitfield(ifh_hdr, 124, is_sparx5(sparx5) ? 57 : 56, 7); /* FWD.UPDATE_FCS =3D Enable. Enforce update of FCS. */ - ifh_encode_bitfield(ifh_hdr, 1, 67, 1); + ifh_encode_bitfield(ifh_hdr, 1, is_sparx5(sparx5) ? 67 : 66, 1); } =20 void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op) @@ -84,19 +84,22 @@ void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_= op) void sparx5_set_port_ifh_pdu_type(struct sparx5 *sparx5, void *ifh_hdr, u32 pdu_type) { - ifh_encode_bitfield(ifh_hdr, pdu_type, 191, 4); + ifh_encode_bitfield(ifh_hdr, pdu_type, is_sparx5(sparx5) ? 191 : 190, + 4); } =20 void sparx5_set_port_ifh_pdu_w16_offset(struct sparx5 *sparx5, void *ifh_h= dr, u32 pdu_w16_offset) { - ifh_encode_bitfield(ifh_hdr, pdu_w16_offset, 195, 6); + ifh_encode_bitfield(ifh_hdr, pdu_w16_offset, + is_sparx5(sparx5) ? 195 : 194, 6); } =20 void sparx5_set_port_ifh_timestamp(struct sparx5 *sparx5, void *ifh_hdr, u64 timestamp) { - ifh_encode_bitfield(ifh_hdr, timestamp, 232, 40); + ifh_encode_bitfield(ifh_hdr, timestamp, 232, + is_sparx5(sparx5) ? 40 : 38); } =20 static int sparx5_port_open(struct net_device *ndev) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c b/driver= s/net/ethernet/microchip/sparx5/sparx5_packet.c index 57fa9ff9dfce..b6f635d85820 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c @@ -43,7 +43,8 @@ void sparx5_ifh_parse(struct sparx5 *sparx5, u32 *ifh, st= ruct frame_info *info) ((u32)xtr_hdr[29] << 8) | ((u32)xtr_hdr[30] << 0); fwd =3D (fwd >> 5); - info->src_port =3D FIELD_GET(GENMASK(7, 1), fwd); + info->src_port =3D spx5_field_get(GENMASK(is_sparx5(sparx5) ? 7 : 6, 1), + fwd); =20 /* * Bit 270-271 are occasionally unexpectedly set by the hardware, diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c b/drivers/= net/ethernet/microchip/sparx5/sparx5_port.c index 0b38b4cb0929..1401761c6251 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c @@ -476,6 +476,9 @@ static int sparx5_port_fifo_sz(struct sparx5 *sparx5, u32 mac_width =3D 8; u32 addition =3D 0; =20 + if (!is_sparx5(sparx5)) + return 0; + switch (speed) { case SPEED_25000: return 0; @@ -921,6 +924,20 @@ static int sparx5_port_config_low_set(struct sparx5 *s= parx5, sparx5, DEV2G5_DEV_RST_CTRL(port->portno)); =20 + /* Enable PHAD_CTRL for better timestamping */ + if (!is_sparx5(sparx5)) { + for (int i =3D 0; i < 2; ++i) { + /* Divide the port clock by three for the two + * phase detection registers. + */ + spx5_rmw(DEV2G5_PHAD_CTRL_DIV_CFG_SET(3) | + DEV2G5_PHAD_CTRL_PHAD_ENA_SET(1), + DEV2G5_PHAD_CTRL_DIV_CFG | + DEV2G5_PHAD_CTRL_PHAD_ENA, + sparx5, DEV2G5_PHAD_CTRL(port->portno, i)); + } + } + return 0; } =20 @@ -978,6 +995,7 @@ int sparx5_port_config(struct sparx5 *sparx5, struct sparx5_port_config *conf) { bool high_speed_dev =3D sparx5_is_baser(conf->portmode); + const struct sparx5_ops *ops =3D sparx5->data->ops; int err, urgency, stop_wm; =20 err =3D sparx5_port_verify_speed(sparx5, port, conf); @@ -993,6 +1011,13 @@ int sparx5_port_config(struct sparx5 *sparx5, if (err) return err; =20 + if (!is_sparx5(sparx5) && ops->is_port_10g(port->portno) && + conf->speed < SPEED_10000) + spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(1), + DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, + sparx5, + DSM_DEV_TX_STOP_WM_CFG(port->portno)); + /* Set the DSM stop watermark */ stop_wm =3D sparx5_port_fifo_sz(sparx5, port->portno, conf->speed); spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(stop_wm), @@ -1144,6 +1169,27 @@ int sparx5_port_init(struct sparx5 *sparx5, DEV25G_PCS25G_SD_CFG(pix)); } =20 + if (!is_sparx5(sparx5)) { + void __iomem *inst; + u32 dev, tinst; + + if (ops->is_port_10g(port->portno)) { + dev =3D sparx5_to_high_dev(sparx5, port->portno); + tinst =3D sparx5_port_dev_index(sparx5, port->portno); + inst =3D spx5_inst_get(sparx5, dev, tinst); + + spx5_inst_wr(5, inst, + DEV10G_PTP_STAMPER_CFG(port->portno)); + } else if (ops->is_port_5g(port->portno)) { + dev =3D sparx5_to_high_dev(sparx5, port->portno); + tinst =3D sparx5_port_dev_index(sparx5, port->portno); + inst =3D spx5_inst_get(sparx5, dev, tinst); + + spx5_inst_wr(5, inst, + DEV5G_PTP_STAMPER_CFG(port->portno)); + } + } + return 0; } =20 diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_qos.c b/drivers/n= et/ethernet/microchip/sparx5/sparx5_qos.c index d065f8c40d37..e580670f3992 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_qos.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_qos.c @@ -367,9 +367,10 @@ static u32 sparx5_weight_to_hw_cost(u32 weight_min, u3= 2 weight) static int sparx5_dwrr_conf_set(struct sparx5_port *port, struct sparx5_dwrr *dwrr) { + u32 layer =3D is_sparx5(port->sparx5) ? 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Lars Povlsen , Steen Hegelund , , , , , , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: , , , Steen Hegelund , X-Mailer: b4 0.14-dev Add compatible strings for the twelve different lan969x targets that we support. Either a sparx5-switch or lan9691-switch compatible string provided on their own, or any lan969x-switch compatible string with a fallback to lan9691-switch. Also, add myself as a maintainer. Reviewed-by: Steen Hegelund Signed-off-by: Daniel Machon Reviewed-by: Krzysztof Kozlowski --- .../bindings/net/microchip,sparx5-switch.yaml | 20 ++++++++++++++++= +++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.= yaml b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml index fcafef8d5a33..dedfad526666 100644 --- a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml +++ b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml @@ -9,6 +9,7 @@ title: Microchip Sparx5 Ethernet switch controller maintainers: - Steen Hegelund - Lars Povlsen + - Daniel Machon =20 description: | The SparX-5 Enterprise Ethernet switch family provides a rich set of @@ -34,7 +35,24 @@ properties: pattern: "^switch@[0-9a-f]+$" =20 compatible: - const: microchip,sparx5-switch + oneOf: + - enum: + - microchip,lan9691-switch + - microchip,sparx5-switch + - items: + - enum: + - microchip,lan969c-switch + - microchip,lan969b-switch + - microchip,lan969a-switch + - microchip,lan9699-switch + - microchip,lan9698-switch + - microchip,lan9697-switch + - microchip,lan9696-switch + - microchip,lan9695-switch + - microchip,lan9694-switch + - microchip,lan9693-switch + - microchip,lan9692-switch + - const: microchip,lan9691-switch =20 reg: items: --=20 2.34.1 From nobody Mon Nov 25 22:51:56 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 810641FF7D9; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241024-sparx5-lan969x-switch-driver-2-v2-14-a0b5fae88a0f@microchip.com> References: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> In-Reply-To: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Lars Povlsen , Steen Hegelund , , , , , , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: , , , Steen Hegelund , X-Mailer: b4 0.14-dev Add lan9691-switch compatible string to mchp_sparx5_match. Guard it with IS_ENABLED(CONFIG_LAN969X_SWITCH) to make sure Sparx5 can be compiled on its own. Reviewed-by: Steen Hegelund Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c b/drivers/= net/ethernet/microchip/sparx5/sparx5_main.c index 741404ccd8f5..fde9e06b3458 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c @@ -24,6 +24,8 @@ #include #include =20 +#include "../lan969x/lan969x.h" /* for lan969x match data */ + #include "sparx5_main_regs.h" #include "sparx5_main.h" #include "sparx5_port.h" @@ -1050,6 +1052,9 @@ static const struct sparx5_match_data sparx5_desc =3D= { =20 static const struct of_device_id mchp_sparx5_match[] =3D { { .compatible =3D "microchip,sparx5-switch", .data =3D &sparx5_desc }, +#if IS_ENABLED(CONFIG_LAN969X_SWITCH) + { .compatible =3D "microchip,lan9691-switch", .data =3D &lan969x_desc }, +#endif { } }; MODULE_DEVICE_TABLE(of, mchp_sparx5_match); --=20 2.34.1 From nobody Mon Nov 25 22:51:56 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 600B2200120; Wed, 23 Oct 2024 22:03:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729720982; cv=none; b=XIBBYXtjkdfW+zCCc/NOx/9bM4UWyobeaL6K/K28Md0Mp5hVoW24zSFdyiWqTHJ7VP75RIG9vznDCMfqpdtTSJjFwFCgCh6x+YbS0tqdbK1tFa0TUb38BKGYjHP/T2SxJC6IQ/dwnv6ubLRLBd8YC2PzCBqpy7iwEW0opuKky0g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729720982; c=relaxed/simple; bh=esNMXB8X1MNGOmYz9S2m1lVZA9GJT5ND8odp2j2gb6Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Vs4yRmNJoA9MteS899g6k5UD8Qlus76Lb9MpdLyAH8fHLTiqtFCrHVbV4QoK434kvM5TxVIVtYbEJvoJeUQXDYE/67rv8LCqtgF++AcgIy0xsDdByZSykbMstaAN+77su0EUt0qUreRzpStflGkG1SF5JWgy+8I2iFrLMvGCEAM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=qGAJKwRL; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="qGAJKwRL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1729720980; x=1761256980; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=esNMXB8X1MNGOmYz9S2m1lVZA9GJT5ND8odp2j2gb6Q=; b=qGAJKwRLcbre0hEdB4jV30Fy2aOFhy+H5EaYtoaL7esb2jhqYzyq42Xi OBiQXK5drDXi0lgfMaeUTrB77F2rR+cFCtQsi5n82TDh0b0M4NY0dBczW ltlEY2fcSNkJT//GQRvg9R+HF+S3UUcYt/lAUgWGIYZvPPCNU2ONRQpRd f+cTuQPgmOGebvieZdYcpDNStRh50ULs+SoFdiBU9fU7Fz0J/Sc274RIz ENwbq2aCQKgm8CHIy+a8+muioEnUc21KNBF9aeyVzsTAOh+3BIoeFCRDf LlQutq8ZXxNEIxFqQmwASxoRAmyoVBm93n5t365AOjzl8dvXEoS30vS/p A==; X-CSE-ConnectionGUID: oMPErp9qRFmiMc0P9W4Bgw== X-CSE-MsgGUID: dsoK4pyNSSyagCAMHqgqUA== X-IronPort-AV: E=Sophos;i="6.11,227,1725346800"; d="scan'208";a="264507062" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Oct 2024 15:02:58 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 23 Oct 2024 15:02:42 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 23 Oct 2024 15:02:38 -0700 From: Daniel Machon Date: Thu, 24 Oct 2024 00:01:34 +0200 Subject: [PATCH net-next v2 15/15] net: sparx5: add feature support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241024-sparx5-lan969x-switch-driver-2-v2-15-a0b5fae88a0f@microchip.com> References: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> In-Reply-To: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Lars Povlsen , Steen Hegelund , , , , , , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: , , , Steen Hegelund , X-Mailer: b4 0.14-dev Lan969x supports a number of different features, depending on the target. Add new field sparx5->features and initialize the features based on the target. Also add the function sparx5_has_feature() and use it throughout. For now, we only need to handle features: PSFP and PTP - more will come in the future. [1] https://www.microchip.com/en-us/product/lan9698 Reviewed-by: Steen Hegelund Signed-off-by: Daniel Machon --- .../net/ethernet/microchip/sparx5/sparx5_main.c | 40 ++++++++++++++++++= +++- .../net/ethernet/microchip/sparx5/sparx5_main.h | 7 ++++ .../ethernet/microchip/sparx5/sparx5_tc_flower.c | 5 +++ 3 files changed, 51 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c b/drivers/= net/ethernet/microchip/sparx5/sparx5_main.c index fde9e06b3458..4f2d5413a64f 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c @@ -229,6 +229,40 @@ bool is_sparx5(struct sparx5 *sparx5) } } =20 +static void sparx5_init_features(struct sparx5 *sparx5) +{ + switch (sparx5->target_ct) { + case SPX5_TARGET_CT_7546: + case SPX5_TARGET_CT_7549: + case SPX5_TARGET_CT_7552: + case SPX5_TARGET_CT_7556: + case SPX5_TARGET_CT_7558: + case SPX5_TARGET_CT_7546TSN: + case SPX5_TARGET_CT_7549TSN: + case SPX5_TARGET_CT_7552TSN: + case SPX5_TARGET_CT_7556TSN: + case SPX5_TARGET_CT_7558TSN: + case SPX5_TARGET_CT_LAN9691VAO: + case SPX5_TARGET_CT_LAN9694TSN: + case SPX5_TARGET_CT_LAN9694RED: + case SPX5_TARGET_CT_LAN9692VAO: + case SPX5_TARGET_CT_LAN9696TSN: + case SPX5_TARGET_CT_LAN9696RED: + case SPX5_TARGET_CT_LAN9693VAO: + case SPX5_TARGET_CT_LAN9698TSN: + case SPX5_TARGET_CT_LAN9698RED: + sparx5->features =3D (SPX5_FEATURE_PSFP | SPX5_FEATURE_PTP); + break; + default: + break; + } +} + +bool sparx5_has_feature(struct sparx5 *sparx5, enum sparx5_feature feature) +{ + return sparx5->features & feature; +} + static int sparx5_create_targets(struct sparx5 *sparx5) { const struct sparx5_main_io_resource *iomap =3D sparx5->data->iomap; @@ -771,7 +805,8 @@ static int sparx5_start(struct sparx5 *sparx5) sparx5->xtr_irq =3D -ENXIO; } =20 - if (sparx5->ptp_irq >=3D 0) { + if (sparx5->ptp_irq >=3D 0 && + sparx5_has_feature(sparx5, SPX5_FEATURE_PTP)) { err =3D devm_request_threaded_irq(sparx5->dev, sparx5->ptp_irq, NULL, ops->ptp_irq_handler, IRQF_ONESHOT, "sparx5-ptp", @@ -915,6 +950,9 @@ static int mchp_sparx5_probe(struct platform_device *pd= ev) sparx5->target_ct =3D (enum spx5_target_chiptype) GCB_CHIP_ID_PART_ID_GET(sparx5->chip_id); =20 + /* Initialize the features based on the target */ + sparx5_init_features(sparx5); + /* Initialize Switchcore and internal RAMs */ err =3D sparx5_init_switchcore(sparx5); if (err) { diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h b/drivers/= net/ethernet/microchip/sparx5/sparx5_main.h index 1828e2a7d610..146bdc938adc 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h @@ -75,6 +75,11 @@ enum sparx5_cal_bw { SPX5_CAL_SPEED_12G5 =3D 7 }; =20 +enum sparx5_feature { + SPX5_FEATURE_PSFP =3D BIT(0), + SPX5_FEATURE_PTP =3D BIT(1), +}; + #define SPX5_PORTS 65 #define SPX5_PORTS_ALL 70 /* Total number of ports */ =20 @@ -337,6 +342,7 @@ struct sparx5 { struct device *dev; u32 chip_id; enum spx5_target_chiptype target_ct; + u32 features; void __iomem *regs[NUM_TARGETS]; int port_count; struct mutex lock; /* MAC reg lock */ @@ -404,6 +410,7 @@ struct sparx5 { =20 /* sparx5_main.c */ bool is_sparx5(struct sparx5 *sparx5); +bool sparx5_has_feature(struct sparx5 *sparx5, enum sparx5_feature feature= ); =20 /* sparx5_switchdev.c */ int sparx5_register_notifier_blocks(struct sparx5 *sparx5); diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_tc_flower.c b/dri= vers/net/ethernet/microchip/sparx5/sparx5_tc_flower.c index c3bbed140554..4dc1ebd5d510 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_tc_flower.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_tc_flower.c @@ -1284,6 +1284,11 @@ static int sparx5_tc_flower_replace(struct net_devic= e *ndev, =20 /* Setup PSFP */ if (tc_sg_idx >=3D 0 || tc_pol_idx >=3D 0) { + if (!sparx5_has_feature(sparx5, SPX5_FEATURE_PSFP)) { + err =3D -EOPNOTSUPP; + goto out; + } + err =3D sparx5_tc_flower_psfp_setup(sparx5, vrule, tc_sg_idx, tc_pol_idx, &sg, &fm, &sf); if (err) --=20 2.34.1