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Thu, 24 Oct 2024 13:31:57 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49ODVtu0028781 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Oct 2024 13:31:55 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 24 Oct 2024 06:31:51 -0700 From: Imran Shaik Date: Thu, 24 Oct 2024 19:01:17 +0530 Subject: [PATCH v2 4/6] clk: qcom: Add support for Camera Clock Controller on QCS8300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241024-qcs8300-mm-patches-v2-4-76c905060d0a@quicinc.com> References: <20241024-qcs8300-mm-patches-v2-0-76c905060d0a@quicinc.com> In-Reply-To: <20241024-qcs8300-mm-patches-v2-0-76c905060d0a@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Ajit Pandey , Taniya Das , Jagadeesh Kona , Satya Priya Kakitapalli , , , , , Imran Shaik , Dmitry Baryshkov X-Mailer: b4 0.14.1 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 0f-_HXTP827mzry3xEjBannnfa4MKXRz X-Proofpoint-GUID: 0f-_HXTP827mzry3xEjBannnfa4MKXRz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 priorityscore=1501 adultscore=0 bulkscore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=999 impostorscore=0 suspectscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410240110 Add support to the QCS8300 Camera clock controller by extending the SA8775P Camera clock controller, which is mostly identical but QCS8300 has few additional clocks and few other differences. Reviewed-by: Dmitry Baryshkov Signed-off-by: Imran Shaik --- drivers/clk/qcom/camcc-sa8775p.c | 99 ++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 95 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/camcc-sa8775p.c b/drivers/clk/qcom/camcc-sa87= 75p.c index c04801a5af35..0ef3c6015c34 100644 --- a/drivers/clk/qcom/camcc-sa8775p.c +++ b/drivers/clk/qcom/camcc-sa8775p.c @@ -1682,6 +1682,24 @@ static struct clk_branch cam_cc_sm_obs_clk =3D { }, }; =20 +static struct clk_branch cam_cc_titan_top_accu_shift_clk =3D { + .halt_reg =3D 0x131f0, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x131f0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_titan_top_accu_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + static struct gdsc cam_cc_titan_top_gdsc =3D { .gdscr =3D 0x131bc, .en_rest_wait_val =3D 0x2, @@ -1776,6 +1794,7 @@ static struct clk_regmap *cam_cc_sa8775p_clocks[] =3D= { [CAM_CC_SLEEP_CLK_SRC] =3D &cam_cc_sleep_clk_src.clkr, [CAM_CC_SLOW_AHB_CLK_SRC] =3D &cam_cc_slow_ahb_clk_src.clkr, [CAM_CC_SM_OBS_CLK] =3D &cam_cc_sm_obs_clk.clkr, + [CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] =3D NULL, [CAM_CC_XO_CLK_SRC] =3D &cam_cc_xo_clk_src.clkr, [CAM_CC_QDSS_DEBUG_XO_CLK] =3D &cam_cc_qdss_debug_xo_clk.clkr, }; @@ -1812,6 +1831,7 @@ static struct qcom_cc_desc cam_cc_sa8775p_desc =3D { }; =20 static const struct of_device_id cam_cc_sa8775p_match_table[] =3D { + { .compatible =3D "qcom,qcs8300-camcc" }, { .compatible =3D "qcom,sa8775p-camcc" }, { } }; @@ -1842,10 +1862,81 @@ static int cam_cc_sa8775p_probe(struct platform_dev= ice *pdev) clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); =20 - /* Keep some clocks always enabled */ - qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */ - qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */ - qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */ + if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcs8300-camcc")) { + cam_cc_camnoc_axi_clk_src.cmd_rcgr =3D 0x13154; + cam_cc_camnoc_axi_clk.halt_reg =3D 0x1316c; + cam_cc_camnoc_axi_clk.clkr.enable_reg =3D 0x1316c; + cam_cc_camnoc_dcd_xo_clk.halt_reg =3D 0x13174; + cam_cc_camnoc_dcd_xo_clk.clkr.enable_reg =3D 0x13174; + + cam_cc_csi0phytimer_clk_src.cmd_rcgr =3D 0x15054; + cam_cc_csi1phytimer_clk_src.cmd_rcgr =3D 0x15078; + cam_cc_csi2phytimer_clk_src.cmd_rcgr =3D 0x15098; + cam_cc_csid_clk_src.cmd_rcgr =3D 0x13134; + + cam_cc_mclk0_clk_src.cmd_rcgr =3D 0x15000; + cam_cc_mclk1_clk_src.cmd_rcgr =3D 0x1501c; + cam_cc_mclk2_clk_src.cmd_rcgr =3D 0x15038; + + cam_cc_fast_ahb_clk_src.cmd_rcgr =3D 0x13104; + cam_cc_slow_ahb_clk_src.cmd_rcgr =3D 0x1311c; + cam_cc_xo_clk_src.cmd_rcgr =3D 0x131b8; + cam_cc_sleep_clk_src.cmd_rcgr =3D 0x131d4; + + cam_cc_core_ahb_clk.halt_reg =3D 0x131b4; + cam_cc_core_ahb_clk.clkr.enable_reg =3D 0x131b4; + + cam_cc_cpas_ahb_clk.halt_reg =3D 0x130f4; + cam_cc_cpas_ahb_clk.clkr.enable_reg =3D 0x130f4; + cam_cc_cpas_fast_ahb_clk.halt_reg =3D 0x130fc; + cam_cc_cpas_fast_ahb_clk.clkr.enable_reg =3D 0x130fc; + + cam_cc_csi0phytimer_clk.halt_reg =3D 0x1506c; + cam_cc_csi0phytimer_clk.clkr.enable_reg =3D 0x1506c; + cam_cc_csi1phytimer_clk.halt_reg =3D 0x15090; + cam_cc_csi1phytimer_clk.clkr.enable_reg =3D 0x15090; + cam_cc_csi2phytimer_clk.halt_reg =3D 0x150b0; + cam_cc_csi2phytimer_clk.clkr.enable_reg =3D 0x150b0; + cam_cc_csid_clk.halt_reg =3D 0x1314c; + cam_cc_csid_clk.clkr.enable_reg =3D 0x1314c; + cam_cc_csid_csiphy_rx_clk.halt_reg =3D 0x15074; + cam_cc_csid_csiphy_rx_clk.clkr.enable_reg =3D 0x15074; + cam_cc_csiphy0_clk.halt_reg =3D 0x15070; + cam_cc_csiphy0_clk.clkr.enable_reg =3D 0x15070; + cam_cc_csiphy1_clk.halt_reg =3D 0x15094; + cam_cc_csiphy1_clk.clkr.enable_reg =3D 0x15094; + cam_cc_csiphy2_clk.halt_reg =3D 0x150b4; + cam_cc_csiphy2_clk.clkr.enable_reg =3D 0x150b4; + + cam_cc_mclk0_clk.halt_reg =3D 0x15018; + cam_cc_mclk0_clk.clkr.enable_reg =3D 0x15018; + cam_cc_mclk1_clk.halt_reg =3D 0x15034; + cam_cc_mclk1_clk.clkr.enable_reg =3D 0x15034; + cam_cc_mclk2_clk.halt_reg =3D 0x15050; + cam_cc_mclk2_clk.clkr.enable_reg =3D 0x15050; + + cam_cc_titan_top_gdsc.gdscr =3D 0x131a0; + + cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK] =3D NULL; + cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK_SRC] =3D NULL; + cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK] =3D NULL; + cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK_SRC] =3D NULL; + cam_cc_sa8775p_clocks[CAM_CC_CSIPHY3_CLK] =3D NULL; + cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK] =3D NULL; + cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK_SRC] =3D NULL; + cam_cc_sa8775p_clocks[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] =3D + &cam_cc_titan_top_accu_shift_clk.clkr; + + /* Keep some clocks always enabled */ + qcom_branch_set_clk_en(regmap, 0x13178); /* CAM_CC_CAMNOC_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x131d0); /* CAM_CC_GDSC_CLK */ + qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_SLEEP_CLK */ + } else { + /* Keep some clocks always enabled */ + qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */ + qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */ + } =20 ret =3D qcom_cc_really_probe(&pdev->dev, &cam_cc_sa8775p_desc, regmap); =20 --=20 2.25.1