From nobody Mon Nov 25 20:47:25 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C36AE1D173E; Thu, 24 Oct 2024 12:34:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729773279; cv=none; b=m/5b+T3V5FEtmC8NzjMc4hm2Lls9s8uLR90Nn2SFdpU+zxVjLuxzpsoh6QSusGI42hSYBO8poIT30GoKUlfGjAkTT/mxiTOkrASGSgmDIABtJWJb3IXVhTTycF9XQiOAuYQoyM5WsOLOR6ojDRg9y/0pI3iS7gKVkkPAVSRK068= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729773279; c=relaxed/simple; bh=ARMhkFtKcvJ7wG19Nw9Gz9MB2Ixs7MGDWQrNMepvqpE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mZkpCNLCPPtxunszyzTdoRc6H/2/mpDzmaowJlr6sJGjbz/bFw5xQx0OjfHqpOVy6n/qjIla8OkJ0ZaRshHvYJygURVPeWvZA8p8zYhMBaYcs51qeW6AqM6oq/RXWQaC6A9SuojhPaZvVHSTxRwlzQofjdcq5e44lSAfK7je1HY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iNWxGaDr; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iNWxGaDr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2C54CC4CEE3; Thu, 24 Oct 2024 12:34:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729773279; bh=ARMhkFtKcvJ7wG19Nw9Gz9MB2Ixs7MGDWQrNMepvqpE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iNWxGaDrV8rzpckfKkGdl/jHqYULomoZIAhFJ9ylXP/RSf969VI8YwrDhA3FuVC0t r09rrA5zIvDCCjipt4GAsYsQSX9O3jdIvFzc9CdTPf2Aug+4vVWiQnePcfHt5cThBG PXEkq0rw92dK3QmH7Mnt0zbGJ6sxbdSUa2OxhzHLEzEuJImQyf48Mcdr4AUoMfPtEL 6/P9i2DQ0wx6o0otu3gVuMy3VSuOgmxr+Rxxo2W9ew+FpoQdz8qj5wF+bX5SSbuGXH sFqVeLz2Yl7EqMoObu0cw1F5C3EXbZdfxnpR6JoimuMtky6hpbbcGHUOUN8yMQWnJD 3Tgl/MCRhRhXQ== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andy Chiu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/5] RISC-V: add vector crypto extension validation checks Date: Thu, 24 Oct 2024 13:34:29 +0100 Message-ID: <20241024-bunny-unexposed-196d8da36e7a@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241024-fanning-enrage-bcc39f8ed47d@spud> References: <20241024-fanning-enrage-bcc39f8ed47d@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=10668; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=gYl9oqODRe6In1OlN/4WG2lZumLCQ+UY8gilsqm+PPg=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDOlSdlelzyccCE8xPJg9Q/3ipgsGWVsfscb17Gq3kb/Gx PUg/eP/jlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAEzEX57hf5jdMZ+06Mgv+QdC inTV939bzl4lxFjV9P1uUV/X+d/dnxgZWj34RK7lPGpp/8yua6rv/jHXI83x747sRhdp6Tbeh5x cAA== X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Using Clement's new validation callbacks, support checking that dependencies have been satisfied for the vector crpyto extensions. Currently riscv_isa_extension_available() will return true on systems that support the extensions but vector itself has been disabled by the kernel, adding validation callbacks will prevent such a scenario from occuring and make the behaviour of the extension detection functions more consistent with user expectations - it's not expected to have to check for vector AND the specific crypto extension. The 1.0.0 Vector crypto spec states: The Zvknhb and Zvbc Vector Crypto Extensions --and accordingly the composite extensions Zvkn and Zvks-- require a Zve64x base, or application ("V") base Vector Extension. All of the other Vector Crypto Extensions can be built on any embedded (Zve*) or application ("V") base Vector Extension. and this could be used as the basis for checking that the correct base for individual crypto extensions, but that's not really the kernel's job in my opinion and it is sufficient to leave that sort of precision to the dt-bindings. The kernel only needs to make sure that vector, in some form, is available. Since vector will now be disabled proactively, there's no need to clear the bit in elf_hwcap in riscv_fill_hwcap() any longer. Link: https://github.com/riscv/riscv-crypto/releases/tag/v1.0.0 Signed-off-by: Conor Dooley --- arch/riscv/include/asm/cpufeature.h | 3 + arch/riscv/kernel/cpufeature.c | 112 ++++++++++++++++++---------- 2 files changed, 76 insertions(+), 39 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index 45f9c1171a486..1de408c3deee7 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -51,6 +51,9 @@ void riscv_user_isa_enable(void); #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, \ ARRAY_SIZE(_bundled_exts), NULL) +#define __RISCV_ISA_EXT_BUNDLE_VALIDATE(_name, _bundled_exts, _validate) \ + _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, \ + ARRAY_SIZE(_bundled_exts), _validate) =20 /* Used to declare extensions that are a superset of other extensions (Zvb= b for instance) */ #define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3a8eeaa9310c3..020b19edee2e8 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -101,6 +101,52 @@ static int riscv_ext_zicboz_validate(const struct risc= v_isa_ext_data *data, return 0; } =20 +static int riscv_ext_vector_x_validate(const struct riscv_isa_ext_data *da= ta, + const unsigned long *isa_bitmap) +{ + if (!IS_ENABLED(CONFIG_RISCV_ISA_V)) + return -EINVAL; + + return 0; +} + +static int riscv_ext_vector_float_validate(const struct riscv_isa_ext_data= *data, + const unsigned long *isa_bitmap) +{ + if (!IS_ENABLED(CONFIG_RISCV_ISA_V)) + return -EINVAL; + + if (!IS_ENABLED(CONFIG_FPU)) + return -EINVAL; + + /* + * The kernel doesn't support systems that don't implement both of + * F and D, so if any of the vector extensions that do floating point + * are to be usable, both floating point extensions need to be usable. + */ + if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) + return -EINVAL; + + return 0; +} + +static int riscv_ext_vector_crypto_validate(const struct riscv_isa_ext_dat= a *data, + const unsigned long *isa_bitmap) +{ + if (!IS_ENABLED(CONFIG_RISCV_ISA_V)) + return -EINVAL; + + /* + * It isn't the kernel's job to check that the binding is correct, so + * it should be enough to check that any of the vector extensions are + * enabled, which in-turn means that vector is usable in this kernel + */ + if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZVE32X)) + return -EINVAL; + + return 0; +} + static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data, const unsigned long *isa_bitmap) { @@ -308,12 +354,10 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d), __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q), __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts), - __RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_v, riscv_v_exts, riscv= _ext_vector_float_validate), __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), - __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xli= nuxenvcfg_exts, - riscv_ext_zicbom_validate), - __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xli= nuxenvcfg_exts, - riscv_ext_zicboz_validate), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xli= nuxenvcfg_exts, riscv_ext_zicbom_validate), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xli= nuxenvcfg_exts, riscv_ext_zicboz_validate), __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), @@ -339,40 +383,40 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC), __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX), __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), - __RISCV_ISA_EXT_BUNDLE(zk, riscv_zk_bundled_exts), - __RISCV_ISA_EXT_BUNDLE(zkn, riscv_zkn_bundled_exts), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zk, riscv_zk_bundled_exts, riscv_ext_vect= or_crypto_validate), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zkn, riscv_zkn_bundled_exts, riscv_ext_ve= ctor_crypto_validate), __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND), __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE), __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH), __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR), - __RISCV_ISA_EXT_BUNDLE(zks, riscv_zks_bundled_exts), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zks, riscv_zks_bundled_exts, riscv_ext_ve= ctor_crypto_validate), __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO), - __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts), - __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC), - __RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts), - __RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X), - __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts), - __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts), - __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_ex= ts, riscv_ext_vector_x_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zvbc, RISCV_ISA_EXT_ZVBC, riscv_ext_vector_= crypto_validate), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve= 32f_exts, riscv_ext_vector_float_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zve32x, RISCV_ISA_EXT_ZVE32X, riscv_ext_vec= tor_x_validate), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve= 64d_exts, riscv_ext_vector_float_validate), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve= 64f_exts, riscv_ext_vector_float_validate), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve= 64x_exts, riscv_ext_vector_x_validate), __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH), __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN), - __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB), - __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG), - __RISCV_ISA_EXT_BUNDLE(zvkn, riscv_zvkn_bundled_exts), - __RISCV_ISA_EXT_BUNDLE(zvknc, riscv_zvknc_bundled_exts), - __RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED), - __RISCV_ISA_EXT_BUNDLE(zvkng, riscv_zvkng_bundled_exts), - __RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA), - __RISCV_ISA_EXT_DATA(zvknhb, RISCV_ISA_EXT_ZVKNHB), - __RISCV_ISA_EXT_BUNDLE(zvks, riscv_zvks_bundled_exts), - __RISCV_ISA_EXT_BUNDLE(zvksc, riscv_zvksc_bundled_exts), - __RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED), - __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH), - __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), - __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), + __RISCV_ISA_EXT_DATA_VALIDATE(zvkb, RISCV_ISA_EXT_ZVKB, riscv_ext_vector_= crypto_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zvkg, RISCV_ISA_EXT_ZVKG, riscv_ext_vector_= crypto_validate), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvkn, riscv_zvkn_bundled_exts, riscv_ext_= vector_crypto_validate), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvknc, riscv_zvknc_bundled_exts, riscv_ex= t_vector_crypto_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zvkned, RISCV_ISA_EXT_ZVKNED, riscv_ext_vec= tor_crypto_validate), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvkng, riscv_zvkng_bundled_exts, riscv_ex= t_vector_crypto_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zvknha, RISCV_ISA_EXT_ZVKNHA, riscv_ext_vec= tor_crypto_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zvknhb, RISCV_ISA_EXT_ZVKNHB, riscv_ext_vec= tor_crypto_validate), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvks, riscv_zvks_bundled_exts, riscv_ext_= vector_crypto_validate), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvksc, riscv_zvksc_bundled_exts, riscv_ex= t_vector_crypto_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zvksed, RISCV_ISA_EXT_ZVKSED, riscv_ext_vec= tor_crypto_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zvksh, RISCV_ISA_EXT_ZVKSH, riscv_ext_vecto= r_crypto_validate), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvksg, riscv_zvksg_bundled_exts, riscv_ex= t_vector_crypto_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zvkt, RISCV_ISA_EXT_ZVKT, riscv_ext_vector_= crypto_validate), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), @@ -882,16 +926,6 @@ void __init riscv_fill_hwcap(void) riscv_v_setup_vsize(); } =20 - if (elf_hwcap & COMPAT_HWCAP_ISA_V) { - /* - * ISA string in device tree might have 'v' flag, but - * CONFIG_RISCV_ISA_V is disabled in kernel. - * Clear V flag in elf_hwcap if CONFIG_RISCV_ISA_V is disabled. - */ - if (!IS_ENABLED(CONFIG_RISCV_ISA_V)) - elf_hwcap &=3D ~COMPAT_HWCAP_ISA_V; - } - memset(print_str, 0, sizeof(print_str)); for (i =3D 0, j =3D 0; i < NUM_ALPHA_EXTS; i++) if (riscv_isa[0] & BIT_MASK(i)) --=20 2.45.2 From nobody Mon Nov 25 20:47:25 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 782B71D968E; Thu, 24 Oct 2024 12:34:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729773282; cv=none; b=IdtOPQq6opmKwN+TPVzn4RY/J9usaYUMukgqI0+ndxdi56bgEY5DUOBLGGJjYZsRIzwGa956qyGzaUhjIAumj5qrTf3qrTaH+kzsSu7/Nn8KaUMOsgQRwGjf8gRS+g2o4NorX1+hCaXZj9JHNNCrMBr3TJL3VXbNDeXsJKe/T2s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729773282; c=relaxed/simple; bh=wSLCfX8wndX+rlS9G+CmOUl2Cwte9stfmakvhsfLyUc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Gf8YXSip+oSHgw0/+bS5pYO9fvHUYlK/Txj/ZYo0QZBKJ0dByyMLYtyge9tt2kZRxv85HX1NynBBM1J1iAXWSe5NDWPECe+xRbNju+2c9k5LutkBdhIvgvI/mjHOBHtNMzE+/WF2rUTr+CMq4MkB9BWWrKco7lpIfEsgUlnaR48= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iJptutNj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iJptutNj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C0377C4CECC; Thu, 24 Oct 2024 12:34:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729773282; bh=wSLCfX8wndX+rlS9G+CmOUl2Cwte9stfmakvhsfLyUc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iJptutNj5MijtBI9tMs3A1CwAXFGnS8Xtq7G5VnIKvaBVZDYSyyo2PBRt6smOgNwP 1RcfX/Kmt8V2Nn/jpLk3AKIqsMB5XelikZMqVSwAcJlCEroRR3M+8jMODx6T62/cLc DVFW5KTylQDIS29154ZuSUYCC/JVORfVJT7VvQg7s/G5VT6DRPK9M2TXxNJ7PvteF4 sN2BpJ89g6xCjKw2d52dprCAKOmAQS/ggUyMsNmKTLzKwRZqnXiBBmDXU20/bMm780 MVu4xpa7ZZfEzwE8r7rOQEk7M08YoLhcCl53/Hs0VeDOoTvqNVB6JcGKaL1hQkrHDv JXxx5eYtZdqyw== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andy Chiu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/5] RISC-V: add f & d extension validation checks Date: Thu, 24 Oct 2024 13:34:30 +0100 Message-ID: <20241024-only-crepe-64267d0eebe1@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241024-fanning-enrage-bcc39f8ed47d@spud> References: <20241024-fanning-enrage-bcc39f8ed47d@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2981; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=UvTI7yQ4XDO7pBfMOp39hyEWkU6sqFWGVmdNeuF8vEc=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDOlSdldvG/5Z/lq47UnO8or4cNXwyGtqPHNaZoXnf9iUN n21otXbjlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAExkXxrDHw537uJ5H1jc//9k utO/bov9ceNitVvn7u2p41zyo61HL5Dhf5WNs8AxESdemY+rLqkJim26lJqhqnVA7OiOq18V7/1 fwgUA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Using Clement's new validation callbacks, support checking that dependencies have been satisfied for the floating point extensions. The check for "d" might be slightly confusingly shorter than that of "f", despite "d" depending on "f". This is because the requirement that a hart supporting double precision must also support single precision, should be validated by dt-bindings etc, not the kernel but lack of support for single precision only is a limitation of the kernel. Since vector will now be disabled proactively, there's no need to clear the bit in elf_hwcap in riscv_fill_hwcap() any longer. Signed-off-by: Conor Dooley --- arch/riscv/kernel/cpufeature.c | 36 +++++++++++++++++++++++----------- 1 file changed, 25 insertions(+), 11 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 020b19edee2e8..1326049d2ac3b 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -101,6 +101,29 @@ static int riscv_ext_zicboz_validate(const struct risc= v_isa_ext_data *data, return 0; } =20 +static int riscv_ext_f_validate(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) { + pr_warn_once("This kernel does not support systems with F but not D\n"); + return -EINVAL; + } + + if (!IS_ENABLED(CONFIG_FPU)) + return -EINVAL; + + return 0; +} + +static int riscv_ext_d_validate(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + if (!IS_ENABLED(CONFIG_FPU)) + return -EINVAL; + + return 0; +} + static int riscv_ext_vector_x_validate(const struct riscv_isa_ext_data *da= ta, const unsigned long *isa_bitmap) { @@ -350,8 +373,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i), __RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m), __RISCV_ISA_EXT_DATA(a, RISCV_ISA_EXT_a), - __RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f), - __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d), + __RISCV_ISA_EXT_DATA_VALIDATE(f, RISCV_ISA_EXT_f, riscv_ext_f_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(d, RISCV_ISA_EXT_d, riscv_ext_d_validate), __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q), __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts), __RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_v, riscv_v_exts, riscv= _ext_vector_float_validate), @@ -910,15 +933,6 @@ void __init riscv_fill_hwcap(void) } } =20 - /* - * We don't support systems with F but without D, so mask those out - * here. - */ - if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)= ) { - pr_info("This kernel does not support systems with F but not D\n"); - elf_hwcap &=3D ~COMPAT_HWCAP_ISA_F; - } - if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ZVE32X)) { /* * This cannot fail when called on the boot hart --=20 2.45.2 From nobody Mon Nov 25 20:47:25 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BAB11D9A79; Thu, 24 Oct 2024 12:34:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729773285; cv=none; b=hn6WnvU/7qrGvPf9dksoQt8xJadHz6NV6m3neqSgOWhYCAUm7yaz+/SW4B9+AFQ6Z3mSoCJSrgoUJUkrYenCVOOND3TqdF8KLnhyB5Rkz+qxoVBLxq5Cff+HomQ5hpEbdfIE3JzX//EvwVKDa3s9r3t0hAZIexyGt2rmnWsCnLg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729773285; c=relaxed/simple; bh=ptol331dzJMPhFm6aP6N4KOrUBpmiXlYM+nw8AjqcLA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=sTeSl3RRTg6fmsx2sdFR9yVB10R+Zp7OuIMRpQp24z0rKuwCtJtPjm9PaFTBoV+c5Qt6Bqc0QwLsY81bVUruCfrCL4KpNGdb8vYj2BvERvfmCvuW0jjPYreI027WSl3m3EofXrbapxMeHDTPRnqbqyaXiV1dRqOjj3og/h9Hdt4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=d5jjhn74; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="d5jjhn74" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 60A1AC4CEE8; Thu, 24 Oct 2024 12:34:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729773284; bh=ptol331dzJMPhFm6aP6N4KOrUBpmiXlYM+nw8AjqcLA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=d5jjhn74Pf0GY9BVrZdiAYRJo9/cLV8M09yXG0ZpNcUdHsJmpA+1YDL469lWm3NDy /JhTza2W9T1+wR+bl/U9uQby7399mQq4kSjBVCDCnPfvtU5OafXj3pXJNZ44RhZebM YCCU9LRCPO+qPPMMR3Vkx4QcJHoOdwgP/6v6GnQ39yXI2RYpbYr7f0SqCF+yWUYfTA jeW9kk+T/49Sr2jbJyBSsILXpBqb13XZk9zxbGfFTgipdPUNEIC+Sw3SO55Zwhh1fJ qGRFHT0QjPudq1IlURf+BJ+NEORpKgfaMj9OHmjZVFsyxicb7wkJCRSsM09atqbtLO 9JmgsGGelioNA== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andy Chiu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v2 3/5] dt-bindings: riscv: d requires f Date: Thu, 24 Oct 2024 13:34:31 +0100 Message-ID: <20241024-petted-oasis-426993b07f75@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241024-fanning-enrage-bcc39f8ed47d@spud> References: <20241024-fanning-enrage-bcc39f8ed47d@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Developer-Signature: v=1; a=openpgp-sha256; l=1207; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=OXDrUW3asuNmjBXo7oSLxm76Z3KlXKOnfCj4qooySls=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDOlSdteubDlzaP9d1Ym6e+88iv5n+7hYuUKr//B+jy/1F xpelUef7ihlYRDjYJAVU2RJvN3XIrX+j8sO5563MHNYmUCGMHBxCsBElrIxMmyYVxJZeyFk08JD EZ2ity3PBE84dXH75Zl/8mRmHLd/+/UFI8Pxvo0O8ZFWn1q6tfaVutvNk4jXO8sxv3jR04sx/xm EtPgB X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable From: Conor Dooley Per the specifications, the d extension for double-precision floating point operations depends on the f extension for single-precision floating point. Add that requirement to the bindings. This differs from the Linux implementation, where single-precious only is not supported. Reviewed-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 2cf2026cff574..c697be64d3bfc 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -571,6 +571,12 @@ properties: https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.= 0.0-Datasheet.pdf =20 allOf: + - if: + contains: + const: d + then: + contains: + const: f # Zcb depends on Zca - if: contains: --=20 2.45.2 From nobody Mon Nov 25 20:47:25 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 046041DBB24; Thu, 24 Oct 2024 12:34:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729773288; cv=none; b=OIIG26ZUG7CdtapaR7222/JtDdaON6agmQQ5YhY/l47M55gsJVqZuWiTeAIE2b/vaAhAUzprSFI2XD896QqGqT5ieY45zsyIOfQ5j7IBhyQScBZYg+PaNx5c+wRki+dumThiSJvIyBuPr5Nnh9lkPYm9/SaHALmgXzGT18HXjhY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729773288; c=relaxed/simple; bh=hcHQ85R98EralwanuOTJcKXBev45BYhijHl4CsbVU8k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KsI6qHm7wQfRCeVuZX2t/QP6+5NEyy/SEozM+d4Kp8+J1NW5r2iszsZ55jTZ9R9IqE4QnMSFmv4s+3sZ9MgpVKPkCSq7hc3tEbzdte6hIHAPfNCEpKhsGa/LyT+gxV6PDsYkzGyut+kdIYubzuMMBIH61TxP9KG9Ru7BXUi2sOA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fwlgVcWo; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fwlgVcWo" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 31664C4CECC; Thu, 24 Oct 2024 12:34:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729773287; bh=hcHQ85R98EralwanuOTJcKXBev45BYhijHl4CsbVU8k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fwlgVcWohf/PXX/NXbuf6IhjVQcE6oIeCiieIkydcuP/6t2WN6L8/5hjL3cV9j4Kn pdisnl936vFNrkfznY3+tiFTMJ1+SibbZeAanZB28AyRHxBZgbkWitgdsSgF/32k6N +a+mukmFxGSjMqij0th5tobFLDzMCiew3jTPGkHduQ3fV1AbhvjvLZNX1iYIFlImVB OYzw5QroUsCKCLrV9p+S7UXFK9ndLg+vgfFw6YrN+UJOt2+QMiz+CRxN7sAR35Em17 d+HkphUY1goR++ttyX4JEb3vL7Rqeb0FmTQwwGRobco9wwJSpDcM+Pmy3M3LaLcV1/ 9mF+no4iqgnXg== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andy Chiu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v2 4/5] dt-bindings: riscv: add vector sub-extension dependencies Date: Thu, 24 Oct 2024 13:34:32 +0100 Message-ID: <20241024-shrink-eligibly-b5a4325fa286@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241024-fanning-enrage-bcc39f8ed47d@spud> References: <20241024-fanning-enrage-bcc39f8ed47d@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Developer-Signature: v=1; a=openpgp-sha256; l=2334; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=DCTAFUzYk9DPluUbp/0vltmkI6PevBaQollD7j8w0BM=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDOlSdtfmT3FZzrp91XWh/0yTOp/lan56v6BUt1Vlys+eZ zM12WdO7ChlYRDjYJAVU2RJvN3XIrX+j8sO5563MHNYmUCGMHBxCsBEvsxjZJjrzNR/Y0HK+fdN 17Z4dIib2b0w6ym+zHnQfk1izLEnypUM/x3+rKtfvrr9842re49ELJM7kj5BZOeuvR7+bKn88SJ ywnwA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable From: Conor Dooley Section 33.18.2. Zve*: Vector Extensions for Embedded Processors in [1] says: | The Zve32f and Zve64x extensions depend on the Zve32x extension. The Zve6= 4f extension depends | on the Zve32f and Zve64x extensions. The Zve64d extension depends on the = Zve64f extension | The Zve32x extension depends on the Zicsr extension. The Zve32f and Zve64= f extensions depend | upon the F extension | The Zve64d extension depends upon the D extension Apply these rules to the bindings to help prevent invalid combinations. Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-rele= ase-698e64a-2024-09-09 [1] Reviewed-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index c697be64d3bfc..20cead7d8af71 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -612,6 +612,52 @@ properties: contains: const: zca =20 + - if: + contains: + const: zve32x + then: + contains: + const: zicsr + + - if: + contains: + const: zve32f + then: + allOf: + - contains: + const: f + - contains: + const: zve32x + + - if: + contains: + const: zve64x + then: + contains: + const: zve32x + + - if: + contains: + const: zve64f + then: + allOf: + - contains: + const: f + - contains: + const: zve32f + - contains: + const: zve64x + + - if: + contains: + const: zve64d + then: + allOf: + - contains: + const: d + - contains: + const: zve64f + allOf: # Zcf extension does not exist on rv64 - if: --=20 2.45.2 From nobody Mon Nov 25 20:47:25 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C6C41D63CE; Thu, 24 Oct 2024 12:34:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729773290; cv=none; b=GknSqhDweZH+1cKKtWXY6jk3zoq2NYLuljz3nCGfCitgSSNTPBmHknlVrCb8tPGgk/AL2Sh3vt8ru8snXxdw6YyIUbe+JHoqo7pjbp9TPDc7S8PezTQqoGzrcpBSTyL9Ye1FuaEhH3ZCTJqhuAvU07rhFZmow0YLhi8V/a8LJOU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729773290; c=relaxed/simple; bh=K3gXF6XbnmUL4vxccwBpDJwpWrMAwTUAMTHCmMZNmhU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dtzlr8Py0XDk5WAciFIhB3fwT30tiXnvYQidFCvxFCfAs0l30JYxDre9iP8cexgPMHacQkxYvCagnqunU8gsZ1z7tObKeAyYyTu0ZRpe2jb++SyRjF/J/IXnZwt+nosL3mrwKJpvt1KH4DWxcyqFltR0f+UFZiA43sKTkRSgiXE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=E2OCOXA1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="E2OCOXA1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EDCE2C4CEC7; Thu, 24 Oct 2024 12:34:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729773290; bh=K3gXF6XbnmUL4vxccwBpDJwpWrMAwTUAMTHCmMZNmhU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E2OCOXA1DSNsWokyzFT/mLl5SxryxKZX+3uEFZQikGCaaPIBuqawl6DMXGiXvLUAA nuqpD+M4WL6rs5QZnaRH5R45WA2EM5M7L+44oDQ/AtqvIzLPji6QNDVFJqv4yoVQbi G/BZVS3T7GhoCcLBTJLwBlVVHeo+nReL0wEXLfBNloyz2c4Ox9Slr1VPJCEebXan+L dTc/8m54UOThkT5CrsY16Eyj/yeWy66zIwBkD+1qPvwGuCEvFlweX1Ul5N64E6Dq4M srpEbt7N6AyG/yjLAd4VzAz/BkcrYwc+/Z9XKdk7ySHhG1ViO5IVOjfEIuy83lMtVy 4a/EtsGZcGeqg== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andy Chiu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v2 5/5] dt-bindings: riscv: document vector crypto requirements Date: Thu, 24 Oct 2024 13:34:33 +0100 Message-ID: <20241024-pungent-lasso-42dd3512a3c8@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241024-fanning-enrage-bcc39f8ed47d@spud> References: <20241024-fanning-enrage-bcc39f8ed47d@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2037; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=VOy2t1F9TKOOPNx3M+MXPHgxN3iDgl3UPDedDE/djSQ=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDOlSdtes2OevZCwRtevndV7gEHIv9262WM9tzomNe3Z+K //45+DdjlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAExkzndGhn7rDdXb5CRP8WyW 3XL2n4Tnfl2WpeH5b3qLH0+d83Jl71VGholrOFib/4X9zJPsnjjzvdihro2/X8bKyoXfuv7+8hn bbQwA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Section 35.2. Extensions Overview of [1] says: | The Zvknhb and Zvbc Vector Crypto Extensions --and accordingly the compos= ite extensions Zvkn and | Zvks-- (sic) require a Zve64x base, or application ("V") base Vector Exte= nsion. | All of the other Vector Crypto Extensions can be built on any embedded (Z= ve*) or application ("V") base | Vector Extension Apply these rules in the binding, so that invalid combinations can be avoided. Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-rele= ase-698e64a-2024-09-09 [1] Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 20cead7d8af71..38d77043552a3 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -658,6 +658,38 @@ properties: - contains: const: zve64f =20 + - if: + contains: + anyOf: + - const: zvbc + - const: zvkn + - const: zvknhb + - const: zvks + then: + contains: + anyOf: + - const: v + - const: zve64x + + - if: + contains: + anyOf: + - const: zvbb + - const: zvkb + - const: zvkg + - const: zvkned + - const: zvknha + - const: zvksed + - const: zvksh + - const: zvknc + - const: zvkng + - const: zvkt + then: + contains: + anyOf: + - const: v + - const: zve32x + allOf: # Zcf extension does not exist on rv64 - if: --=20 2.45.2