From nobody Tue Nov 26 01:46:08 2024 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EFAB18A6C5; Thu, 24 Oct 2024 05:21:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729747316; cv=none; b=WParXUUcfAlSbTfp14frxL8+Wi21BzJPJtg6cJDE/U8L+qSCXjDWKf2JXt4n2zDEhK7Jw6da/uDynB5dmawKoQrMjDlD5Jv65S8grkgxcyjMmoFrgxG5+I7ZYkPdXQ7JWvnX4WIXMnhXIcVN1SpmVX7UROGnJkBS5pt0XxvU10o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729747316; c=relaxed/simple; bh=DIvjMla05HLiI1/XLCDUNxF0kf/gSNM5WoACMqNNNxE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=dDJwfmQVe25IQig1hqOIv+9Yx5ctYKcSKP+xU3cWH7p2c5oLMoTX0kimsPcGyfc0Ket5u3hKTEJE9jxqXTEJcxPIePSE25MwTaV0s+QAtmsezaE1xhWxyT41w/a0lrfg5RXq4NB6U0BefqQ7MD9y6YpoDS07n3NE5uDdkj6oEnQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=uIAw/BqK; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="uIAw/BqK" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 49O5LmIB109932; Thu, 24 Oct 2024 00:21:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1729747308; bh=FovBiw1gy5DMbMWuNTogpl1PBiY530irUGBBAainHsw=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=uIAw/BqKMJGE7MoTmqL4jlPFl08WJTsk/mxWoSL8S9GQq1odcMvk3SdmYYyznD8ek gs+AzErBSDe/DZP7lRVgZfv6S84bMPvsuDuiW8p7/GuGJzM1rAHFAFqCkiElsiElPD KJVwbbtB4H46w4CtZovWbvcyjVURqdtTDCPBd6Zw= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49O5Lmtc025122; Thu, 24 Oct 2024 00:21:48 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 24 Oct 2024 00:21:48 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 24 Oct 2024 00:21:48 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49O5L4lH090467; Thu, 24 Oct 2024 00:21:44 -0500 From: Manorit Chawdhry Date: Thu, 24 Oct 2024 10:51:06 +0530 Subject: [PATCH v6 09/12] arm64: dts: ti: k3-am68-sk*: Add bootph-* properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241024-b4-upstream-bootph-all-v6-9-2af90e3a4fe7@ti.com> References: <20241024-b4-upstream-bootph-all-v6-0-2af90e3a4fe7@ti.com> In-Reply-To: <20241024-b4-upstream-bootph-all-v6-0-2af90e3a4fe7@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1729747264; l=3955; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=DIvjMla05HLiI1/XLCDUNxF0kf/gSNM5WoACMqNNNxE=; b=156ZjYMbc3oyJNYzbnhEhndJie2LnzTfXGQcJXxKDohtChyrzYci09QT2ywgMoIADjTn+RXmn 6spVbFMro3dD8xac/3GmHBAQlolt5S9quLjlM66V5CyRJBVd65tvHZA X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to: - main_uart8, mcu_uart0(DM), wkup_uart0(TIFS) for Traces - mmc1, ospi0 for enabling various bootmodes. - eeprom for board detection Reviewed-by: Udit Kumar Signed-off-by: Manorit Chawdhry --- Notes: R-by picked up in v4 ( Udit ) arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 8 ++++++++ arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 5 +++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/= boot/dts/ti/k3-am68-sk-base-board.dts index d5ceab79536ca45fb1421a2a2e133db6a458b518..11522b36e0cece248571b27819c= 8a87e0ffe06e2 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -184,6 +184,7 @@ main_uart8_pins_default: main-uart8-default-pins { J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ >; + bootph-all; }; =20 main_i2c0_pins_default: main-i2c0-default-pins { @@ -211,6 +212,7 @@ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ >; + bootph-all; }; =20 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { @@ -313,6 +315,7 @@ J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_G= PIO0_7.WKUP_UART0_RTSn */ J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ >; + bootph-all; }; =20 mcu_cpsw_pins_default: mcu-cpsw-default-pins { @@ -372,6 +375,7 @@ mcu_uart0_pins_default: mcu-uart0-default-pins { J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0= _RXD */ J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART= 0_TXD */ >; + bootph-all; }; =20 mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 { @@ -413,6 +417,7 @@ &wkup_uart0 { status =3D "reserved"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_uart0_pins_default>; + bootph-all; }; =20 &wkup_i2c0 { @@ -495,6 +500,7 @@ &mcu_uart0 { status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_uart0_pins_default>; + bootph-all; }; =20 &main_uart8 { @@ -503,6 +509,7 @@ &main_uart8 { pinctrl-0 =3D <&main_uart8_pins_default>; /* Shared with TFA on this platform */ power-domains =3D <&k3_pds 357 TI_SCI_PD_SHARED>; + bootph-all; }; =20 &main_i2c0 { @@ -597,6 +604,7 @@ &main_sdhci1 { disable-wp; vmmc-supply =3D <&vdd_mmc1>; vqmmc-supply =3D <&vdd_sd_dv>; + bootph-all; }; =20 &mcu_cpsw { diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/d= ts/ti/k3-am68-sk-som.dtsi index 5bc0d2fb4b8f3969d6f372a374be91e5b5cbd821..4ca2d4e2fb9b063086b4bec2a18= 4e01dfab11f24 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -156,6 +156,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins { J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ >; + bootph-all; }; }; =20 @@ -169,6 +170,7 @@ eeprom@51 { /* AT24C512C-MAHM-T */ compatible =3D "atmel,24c512"; reg =3D <0x51>; + bootph-all; }; }; =20 @@ -190,7 +192,6 @@ flash@0 { cdns,read-delay =3D <4>; =20 partitions { - bootph-all; compatible =3D "fixed-partitions"; #address-cells =3D <1>; #size-cells =3D <1>; @@ -226,9 +227,9 @@ partition@800000 { }; =20 partition@3fc0000 { - bootph-pre-ram; label =3D "ospi.phypattern"; reg =3D <0x3fc0000 0x40000>; + bootph-all; }; }; }; --=20 2.46.0