From nobody Tue Nov 26 02:15:13 2024 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61CF01741E8; Thu, 24 Oct 2024 05:21:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729747295; cv=none; b=nHi5+NfbkmxdStaRnQSuRnEoIAjv0aeI03phAa3rH0NmyOnGc2ETnr6BdlkZMhIA40fi3Pj9uQ+uvGTab2uH95tbLBuRjKcO/PxALU4U/Y8ghsjh2OHOcrqVmbhgpt9EjpWRVkGmicII01jFhQyi2JA1/ALK+t1NF5yi8FCiX9U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729747295; c=relaxed/simple; bh=2BDHihROVg8eztkArItUGNLASEwXMBXatnAsVyQgE+A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=aPJ/11jTDRzPti5vjhKIUJdbqSPZ835Rt/fiBG2DpOj5PdixxpsDreDNf+/qvTKMN8BznVI96tsDbUwgn/P4MW5nxTeiB9xa+ZQUP09d7qc5gHTXXMjEwpEVgjUj+x71wbCtEg0hrFp6bRSZmvBL3udEgVAzvUaCQj1ZfN2MVCg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=mnMaH7wz; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="mnMaH7wz" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 49O5LRvP015355; Thu, 24 Oct 2024 00:21:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1729747287; bh=2P/n8qOVQ/193CdfajD1J+Oma75AgqNoZyY1Pitb1Y0=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=mnMaH7wzNi/hMcqx/3ADxrb5gH9ztgvrpLycrpNf4SrZOn6ZLa8nK4N6PD3tZv/BW x7Mw+STcNi/UmJlLzPsGhNN6DmpK53HGeluOS8Nhb//b8+eG66z7QlTi59/MUXs4Kq sWs0hXEcMG+ILAJQpPyZzJl/q4GaMs9gXoipFsH0= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 49O5LR5v072014 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 24 Oct 2024 00:21:27 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 24 Oct 2024 00:21:26 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 24 Oct 2024 00:21:26 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49O5L4lC090467; Thu, 24 Oct 2024 00:21:22 -0500 From: Manorit Chawdhry Date: Thu, 24 Oct 2024 10:51:01 +0530 Subject: [PATCH v6 04/12] arm64: dts: ti: k3-j721s2: Add bootph-* properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241024-b4-upstream-bootph-all-v6-4-2af90e3a4fe7@ti.com> References: <20241024-b4-upstream-bootph-all-v6-0-2af90e3a4fe7@ti.com> In-Reply-To: <20241024-b4-upstream-bootph-all-v6-0-2af90e3a4fe7@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1729747264; l=4130; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=2BDHihROVg8eztkArItUGNLASEwXMBXatnAsVyQgE+A=; b=klrXbMugIXlCxlUX4aXv8bwN4zNQpIjdvFiixdAd8g48IYpe9Gu4Tm7TATYpd3GEYdzHeOAN1 JNhbyhHmnLnBv15QK6JjWpAdBSDh0ETEJXLrng4wSI8Y+vqSxi2zY+n X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to - System controller nodes that allow controlling power domain, clocks, etc. - secure_proxy_sa3/secure_proxy_main mboxes for communication with System Controller - mcu_ringacc/mcu_udmap for DMA to SMS - chipid for detection soc information. - mcu_timer0 for bootloader tick-timer. - wkup_vtm for enabling Adaptive voltage scaling(AVS) support Reviewed-by: Andrew Davis Signed-off-by: Manorit Chawdhry --- Notes: R-by picked up in v3 ( Andrew ) arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 13 +++++++++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 9ed6949b40e9dfafdaf6861944b0b128b053a44f..9889144d665a832e5346e13daa7= 887c9c968fbcd 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -816,6 +816,7 @@ secure_proxy_main: mailbox@32c00000 { <0x00 0x32800000 0x00 0x100000>; interrupt-names =3D "rx_011"; interrupts =3D ; + bootph-all; }; =20 hwspinlock: spinlock@30e00000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 9d96b19d0e7cf5bb86b50c73f4ec1a6b43b8bf83..c36888c455316774a07d6932626= 2465ac958a6fc 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -21,16 +21,19 @@ sms: system-controller@44083000 { k3_pds: power-controller { compatible =3D "ti,sci-pm-domain"; #power-domain-cells =3D <2>; + bootph-all; }; =20 k3_clks: clock-controller { compatible =3D "ti,k2g-sci-clk"; #clock-cells =3D <2>; + bootph-all; }; =20 k3_reset: reset-controller { compatible =3D "ti,sci-reset"; #reset-cells =3D <2>; + bootph-all; }; }; =20 @@ -43,6 +46,7 @@ wkup_conf: bus@43000000 { chipid: chipid@14 { compatible =3D "ti,am654-chipid"; reg =3D <0x14 0x4>; + bootph-all; }; }; =20 @@ -53,6 +57,8 @@ secure_proxy_sa3: mailbox@43600000 { reg =3D <0x00 0x43600000 0x00 0x10000>, <0x00 0x44880000 0x00 0x20000>, <0x00 0x44860000 0x00 0x20000>; + bootph-pre-ram; + /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -167,6 +173,7 @@ mcu_timer0: timer@40400000 { assigned-clocks =3D <&k3_clks 35 1>; assigned-clock-parents =3D <&k3_clks 35 2>; power-domains =3D <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + bootph-pre-ram; ti,timer-pwm; /* Non-MPU Firmware usage */ status =3D "reserved"; @@ -361,6 +368,7 @@ wkup_i2c0: i2c@42120000 { clocks =3D <&k3_clks 223 1>; clock-names =3D "fck"; power-domains =3D <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; + bootph-all; status =3D "disabled"; }; =20 @@ -469,6 +477,7 @@ mcu_ringacc: ringacc@2b800000 { <0x0 0x2a500000 0x0 0x40000>, <0x0 0x28440000 0x0 0x40000>; reg-names =3D "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; + bootph-all; ti,num-rings =3D <286>; ti,sci-rm-range-gp-rings =3D <0x1>; ti,sci =3D <&sms>; @@ -488,6 +497,7 @@ mcu_udmap: dma-controller@285c0000 { "tchan", "rchan", "rflow"; msi-parent =3D <&main_udmass_inta>; #dma-cells =3D <1>; + bootph-all; =20 ti,sci =3D <&sms>; ti,sci-dev-id =3D <273>; @@ -507,6 +517,8 @@ secure_proxy_mcu: mailbox@2a480000 { reg =3D <0x00 0x2a480000 0x00 0x80000>, <0x00 0x2a380000 0x00 0x80000>, <0x00 0x2a400000 0x00 0x80000>; + bootph-pre-ram; + /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -667,6 +679,7 @@ wkup_vtm0: temperature-sensor@42040000 { <0x00 0x42050000 0x0 0x350>; power-domains =3D <&k3_pds 180 TI_SCI_PD_SHARED>; #thermal-sensor-cells =3D <1>; + bootph-pre-ram; }; =20 mcu_r5fss0: r5fss@41000000 { --=20 2.46.0