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[2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0b93d53sm10828922f8f.70.2024.10.24.01.17.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2024 01:17:25 -0700 (PDT) From: Julien Stephan Date: Thu, 24 Oct 2024 10:16:58 +0200 Subject: [PATCH v3 3/4] iio: adc: ad7380: add support for adaq4370-4 and adaq4380-4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241024-ad7380-add-adaq4380-4-support-v3-3-6a29bd0f79da@baylibre.com> References: <20241024-ad7380-add-adaq4380-4-support-v3-0-6a29bd0f79da@baylibre.com> In-Reply-To: <20241024-ad7380-add-adaq4380-4-support-v3-0-6a29bd0f79da@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.14.2 adaq4370-4 (2MSPS) and adaq4380-4 (4MSPS) are quad-channel precision data acquisition signal chain =CE=BCModule solutions compatible with the ad738x family, with the following differences: - pin selectable gain in front of each 4 adc - internal reference is 3V derived from refin-supply (5V) - additional supplies This implies that IIO_CHAN_INFO_SCALE can not be shared by type. Signed-off-by: Julien Stephan --- drivers/iio/adc/ad7380.c | 130 +++++++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 126 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index d57e17f38925da5fb7c8a0a2320a21474ba04b37..f36dc27b8f9da7ebc7551193b5d= 847f7e8bef396 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -13,6 +13,8 @@ * ad7381-4 : https://www.analog.com/media/en/technical-documentation/data= -sheets/ad7381-4.pdf * ad7383/4-4 : https://www.analog.com/media/en/technical-documentation/da= ta-sheets/ad7383-4-ad7384-4.pdf * ad7386/7/8-4 : https://www.analog.com/media/en/technical-documentation/= data-sheets/ad7386-4-7387-4-7388-4.pdf + * adaq4370-4 : https://www.analog.com/media/en/technical-documentation/da= ta-sheets/adaq4370-4.pdf + * adaq4380-4 : https://www.analog.com/media/en/technical-documentation/da= ta-sheets/adaq4380-4.pdf */ =20 #include @@ -22,11 +24,14 @@ #include #include #include +#include #include #include #include #include #include +#include +#include =20 #include #include @@ -36,6 +41,8 @@ #define MAX_NUM_CHANNELS 8 /* 2.5V internal reference voltage */ #define AD7380_INTERNAL_REF_MV 2500 +/* 3.3V internal reference voltage for ADAQ */ +#define ADAQ4380_INTERNAL_REF_MV 3300 =20 /* reading and writing registers is more reliable at lower than max speed = */ #define AD7380_REG_WR_SPEED_HZ 10000000 @@ -82,6 +89,7 @@ * supports only 1 SDO line (standard SPI transaction) */ #define AD7380_NUM_SDO_LINES 1 +#define AD7380_DEFAULT_GAIN_MILLI 1000 =20 struct ad7380_timing_specs { const unsigned int t_csh_ns; /* CS minimum high time */ @@ -92,10 +100,12 @@ struct ad7380_chip_info { const struct iio_chan_spec *channels; unsigned int num_channels; unsigned int num_simult_channels; + bool has_hardware_gain; bool has_mux; const char * const *supplies; unsigned int num_supplies; bool external_ref_only; + bool adaq_internal_ref_only; const char * const *vcm_supplies; unsigned int num_vcm_supplies; const unsigned long *available_scan_masks; @@ -187,11 +197,12 @@ static const struct iio_scan_type ad7380_scan_type_16= _u[] =3D { }, }; =20 -#define AD7380_CHANNEL(index, bits, diff, sign) { \ +#define _AD7380_CHANNEL(index, bits, diff, sign, gain) { \ .type =3D IIO_VOLTAGE, \ .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + ((gain) ? BIT(IIO_CHAN_INFO_SCALE) : 0) | \ ((diff) ? 0 : BIT(IIO_CHAN_INFO_OFFSET)), \ - .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE) | \ + .info_mask_shared_by_type =3D ((gain) ? 0 : BIT(IIO_CHAN_INFO_SCALE)) | \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .info_mask_shared_by_type_available =3D \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ @@ -205,6 +216,12 @@ static const struct iio_scan_type ad7380_scan_type_16_= u[] =3D { .num_ext_scan_type =3D ARRAY_SIZE(ad7380_scan_type_##bits##_##sign), \ } =20 +#define AD7380_CHANNEL(index, bits, diff, sign) \ + _AD7380_CHANNEL(index, bits, diff, sign, false) + +#define ADAQ4380_CHANNEL(index, bits, diff, sign) \ + _AD7380_CHANNEL(index, bits, diff, sign, true) + #define DEFINE_AD7380_2_CHANNEL(name, bits, diff, sign) \ static const struct iio_chan_spec name[] =3D { \ AD7380_CHANNEL(0, bits, diff, sign), \ @@ -221,6 +238,15 @@ static const struct iio_chan_spec name[] =3D { \ IIO_CHAN_SOFT_TIMESTAMP(4), \ } =20 +#define DEFINE_ADAQ4380_4_CHANNEL(name, bits, diff, sign) \ +static const struct iio_chan_spec name[] =3D { \ + ADAQ4380_CHANNEL(0, bits, diff, sign), \ + ADAQ4380_CHANNEL(1, bits, diff, sign), \ + ADAQ4380_CHANNEL(2, bits, diff, sign), \ + ADAQ4380_CHANNEL(3, bits, diff, sign), \ + IIO_CHAN_SOFT_TIMESTAMP(4), \ +} + #define DEFINE_AD7380_8_CHANNEL(name, bits, diff, sign) \ static const struct iio_chan_spec name[] =3D { \ AD7380_CHANNEL(0, bits, diff, sign), \ @@ -239,6 +265,7 @@ DEFINE_AD7380_2_CHANNEL(ad7380_channels, 16, 1, s); DEFINE_AD7380_2_CHANNEL(ad7381_channels, 14, 1, s); DEFINE_AD7380_4_CHANNEL(ad7380_4_channels, 16, 1, s); DEFINE_AD7380_4_CHANNEL(ad7381_4_channels, 14, 1, s); +DEFINE_ADAQ4380_4_CHANNEL(adaq4380_4_channels, 16, 1, s); /* pseudo differential */ DEFINE_AD7380_2_CHANNEL(ad7383_channels, 16, 0, s); DEFINE_AD7380_2_CHANNEL(ad7384_channels, 14, 0, s); @@ -257,6 +284,10 @@ static const char * const ad7380_supplies[] =3D { "vcc", "vlogic", }; =20 +static const char * const adaq4380_supplies[] =3D { + "ldo", "vcc", "vlogic", "vs-p", "vs-n", "refin", +}; + static const char * const ad7380_2_channel_vcm_supplies[] =3D { "aina", "ainb", }; @@ -347,6 +378,11 @@ static const int ad7380_oversampling_ratios[] =3D { 1, 2, 4, 8, 16, 32, }; =20 +/* Gains stored as fractions of 1000 so they can be expressed by integers.= */ +static const int ad7380_gains[] =3D { + 300, 600, 1000, 1600, +}; + static const struct ad7380_chip_info ad7380_chip_info =3D { .name =3D "ad7380", .channels =3D ad7380_channels, @@ -516,6 +552,32 @@ static const struct ad7380_chip_info ad7388_4_chip_inf= o =3D { .timing_specs =3D &ad7380_4_timing, }; =20 +static const struct ad7380_chip_info adaq4370_4_chip_info =3D { + .name =3D "adaq4370-4", + .channels =3D adaq4380_4_channels, + .num_channels =3D ARRAY_SIZE(adaq4380_4_channels), + .num_simult_channels =3D 4, + .supplies =3D adaq4380_supplies, + .num_supplies =3D ARRAY_SIZE(adaq4380_supplies), + .adaq_internal_ref_only =3D true, + .has_hardware_gain =3D true, + .available_scan_masks =3D ad7380_4_channel_scan_masks, + .timing_specs =3D &ad7380_4_timing, +}; + +static const struct ad7380_chip_info adaq4380_4_chip_info =3D { + .name =3D "adaq4380-4", + .channels =3D adaq4380_4_channels, + .num_channels =3D ARRAY_SIZE(adaq4380_4_channels), + .num_simult_channels =3D 4, + .supplies =3D adaq4380_supplies, + .num_supplies =3D ARRAY_SIZE(adaq4380_supplies), + .adaq_internal_ref_only =3D true, + .has_hardware_gain =3D true, + .available_scan_masks =3D ad7380_4_channel_scan_masks, + .timing_specs =3D &ad7380_4_timing, +}; + struct ad7380_state { const struct ad7380_chip_info *chip_info; struct spi_device *spi; @@ -526,6 +588,7 @@ struct ad7380_state { bool seq; unsigned int vref_mv; unsigned int vcm_mv[MAX_NUM_CHANNELS]; + unsigned int gain_milli[MAX_NUM_CHANNELS]; /* xfers, message an buffer for reading sample data */ struct spi_transfer normal_xfer[2]; struct spi_message normal_msg; @@ -876,8 +939,15 @@ static int ad7380_read_raw(struct iio_dev *indio_dev, * * (2 =C3=97 VREF) / 2^N, for differential chips * * VREF / 2^N, for pseudo-differential chips * where N is the ADC resolution (i.e realbits) + * + * The gain is stored as a fraction of 1000 and, as we need to + * divide vref_mv by the gain, we invert the gain/1000 fraction. */ - *val =3D st->vref_mv; + if (st->chip_info->has_hardware_gain) + *val =3D mult_frac(st->vref_mv, MILLI, + st->gain_milli[chan->scan_index]); + else + *val =3D st->vref_mv; *val2 =3D scan_type->realbits - chan->differential; =20 return IIO_VAL_FRACTIONAL_LOG2; @@ -1058,7 +1128,19 @@ static int ad7380_probe(struct spi_device *spi) "Failed to enable power supplies\n"); fsleep(T_POWERUP_US); =20 - if (st->chip_info->external_ref_only) { + if (st->chip_info->adaq_internal_ref_only) { + /* + * ADAQ chips use fixed internal reference but still + * require a specific reference supply to power it. + * "refin" is already enabled with other power supplies + * in bulk_get_enable(). + */ + + st->vref_mv =3D ADAQ4380_INTERNAL_REF_MV; + + /* these chips don't have a register bit for this */ + external_ref_en =3D false; + } else if (st->chip_info->external_ref_only) { ret =3D devm_regulator_get_enable_read_voltage(&spi->dev, "refin"); if (ret < 0) @@ -1104,6 +1186,42 @@ static int ad7380_probe(struct spi_device *spi) st->vcm_mv[i] =3D ret / 1000; } =20 + for (i =3D 0; i < MAX_NUM_CHANNELS; i++) + st->gain_milli[i] =3D AD7380_DEFAULT_GAIN_MILLI; + + if (st->chip_info->has_hardware_gain) { + device_for_each_child_node_scoped(&spi->dev, node) { + unsigned int channel, gain; + int gain_idx; + + ret =3D fwnode_property_read_u32(node, "reg", &channel); + if (ret) + return dev_err_probe(&spi->dev, ret, + "Failed to read reg property\n"); + + if (channel >=3D st->chip_info->num_channels - 1) + return dev_err_probe(&spi->dev, -EINVAL, + "Invalid channel number %i\n", + channel); + + ret =3D fwnode_property_read_u32(node, "adi,gain-milli", + &gain); + if (ret && ret !=3D -EINVAL) + return dev_err_probe(&spi->dev, ret, + "Failed to read gain for channel %i\n", + channel); + if (ret !=3D -EINVAL) { + /* + * Match gain value from dt to one of supported + * gains + */ + gain_idx =3D find_closest(gain, ad7380_gains, + ARRAY_SIZE(ad7380_gains)); + st->gain_milli[channel] =3D ad7380_gains[gain_idx]; + } + } + } + st->regmap =3D devm_regmap_init(&spi->dev, NULL, st, &ad7380_regmap_confi= g); if (IS_ERR(st->regmap)) return dev_err_probe(&spi->dev, PTR_ERR(st->regmap), @@ -1186,6 +1304,8 @@ static const struct of_device_id ad7380_of_match_tabl= e[] =3D { { .compatible =3D "adi,ad7386-4", .data =3D &ad7386_4_chip_info }, { .compatible =3D "adi,ad7387-4", .data =3D &ad7387_4_chip_info }, { .compatible =3D "adi,ad7388-4", .data =3D &ad7388_4_chip_info }, + { .compatible =3D "adi,adaq4370-4", .data =3D &adaq4370_4_chip_info }, + { .compatible =3D "adi,adaq4380-4", .data =3D &adaq4380_4_chip_info }, { } }; =20 @@ -1204,6 +1324,8 @@ static const struct spi_device_id ad7380_id_table[] = =3D { { "ad7386-4", (kernel_ulong_t)&ad7386_4_chip_info }, { "ad7387-4", (kernel_ulong_t)&ad7387_4_chip_info }, { "ad7388-4", (kernel_ulong_t)&ad7388_4_chip_info }, + { "adaq4370-4", (kernel_ulong_t)&adaq4370_4_chip_info }, + { "adaq4380-4", (kernel_ulong_t)&adaq4380_4_chip_info }, { } }; MODULE_DEVICE_TABLE(spi, ad7380_id_table); --=20 2.47.0