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[2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0b93d53sm10828922f8f.70.2024.10.24.01.17.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2024 01:17:22 -0700 (PDT) From: Julien Stephan Date: Thu, 24 Oct 2024 10:16:56 +0200 Subject: [PATCH v3 1/4] dt-bindings: iio: adc: ad7380: add adaq4370-4 and adaq4380-4 compatible parts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241024-ad7380-add-adaq4380-4-support-v3-1-6a29bd0f79da@baylibre.com> References: <20241024-ad7380-add-adaq4380-4-support-v3-0-6a29bd0f79da@baylibre.com> In-Reply-To: <20241024-ad7380-add-adaq4380-4-support-v3-0-6a29bd0f79da@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.14.2 adaq4370-4 (2MSPS) and adaq4380-4 (4MSPS) are quad-channel precision data acquisition signal chain =CE=BCModule solutions compatible with the ad738x family, with the following differences: - pin selectable gain in front of each 4 adc - internal reference is 3V derived from refin-supply (5V) - additional supplies To select the gain a new patternProperties is added to describe each channel. It is restricted to adaq devices. Signed-off-by: Julien Stephan Reviewed-by: Conor Dooley --- .../devicetree/bindings/iio/adc/adi,ad7380.yaml | 120 +++++++++++++++++= ++++ 1 file changed, 120 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7380.yaml index 0065d650882489e21b952bb9fb25f1e3a070ee68..ada08005b3cd1ce7ba13f96484a= 33fdee0e83a1c 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml @@ -25,6 +25,8 @@ description: | * https://www.analog.com/en/products/ad7386-4.html * https://www.analog.com/en/products/ad7387-4.html * https://www.analog.com/en/products/ad7388-4.html + * https://www.analog.com/en/products/adaq4370-4.html + * https://www.analog.com/en/products/adaq4380-4.html =20 =20 $ref: /schemas/spi/spi-peripheral-props.yaml# @@ -46,6 +48,8 @@ properties: - adi,ad7386-4 - adi,ad7387-4 - adi,ad7388-4 + - adi,adaq4370-4 + - adi,adaq4380-4 =20 reg: maxItems: 1 @@ -70,6 +74,20 @@ properties: refin-supply: description: A 2.5V to 3.3V supply for external reference voltage, for ad7380-4 o= nly. + For adaq devices, a 5V supply voltage. A 3.3V internal reference is + derived from it. Connect to vs-p-supply for normal operation. + + vs-p-supply: + description: + Amplifiers positive supply. + + vs-n-supply: + description: + Amplifiers negative supply. + + ldo-supply: + description: + LDO supply. Connect to vs-p-supply or a 3.6 to 5.5 V supply. =20 aina-supply: description: @@ -97,12 +115,45 @@ properties: specify the ALERT interrupt. maxItems: 1 =20 + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + required: - compatible - reg - vcc-supply - vlogic-supply =20 +patternProperties: + "^channel@[0-3]$": + $ref: adc.yaml + type: object + + properties: + reg: + description: + The channel number. From 0 to 3 corresponding to channels A,B,C,D + minimum: 0 + maximum: 3 + + adi,gain-milli: + description: + The hardware gain applied to the ADC input (in milli units). + If not present, default to 1000 (no actual gain applied). + Refer to the typical connection diagrams section of the datashee= t for + pin wiring. + $ref: /schemas/types.yaml#/definitions/uint16 + enum: [300, 600, 1000, 1600] + default: 1000 + + required: + - reg + + additionalProperties: false + unevaluatedProperties: false =20 allOf: @@ -140,6 +191,7 @@ allOf: aind-supply: false =20 # ad7380-4 uses refin-supply as external reference. + # adaq devices use internal reference only, derived from refin-supply # All other chips from ad738x family use refio as optional external refe= rence. # When refio-supply is omitted, internal reference is used. - if: @@ -147,6 +199,8 @@ allOf: compatible: enum: - adi,ad7380-4 + - adi,adaq4370-4 + - adi,adaq4380-4 then: properties: refio-supply: false @@ -156,6 +210,27 @@ allOf: properties: refin-supply: false =20 + # adaq devices need more supplies and using channel to declare gain prop= erty + # only applies to adaq devices + - if: + properties: + compatible: + enum: + - adi,adaq4370-4 + - adi,adaq4380-4 + then: + required: + - vs-p-supply + - vs-n-supply + - ldo-supply + else: + properties: + vs-p-supply: false + vs-n-supply: false + ldo-supply: false + patternProperties: + "^channel@[0-3]$": false + examples: - | #include @@ -180,3 +255,48 @@ examples: refio-supply =3D <&supply_2_5V>; }; }; + + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,adaq4380-4"; + reg =3D <0>; + + spi-cpol; + spi-cpha; + spi-max-frequency =3D <80000000>; + + interrupts =3D <27 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent =3D <&gpio0>; + + vcc-supply =3D <&supply_3_3V>; + vlogic-supply =3D <&supply_3_3V>; + refin-supply =3D <&supply_5V>; + vs-p-supply =3D <&supply_5V>; + vs-n-supply =3D <&supply_0V>; + ldo-supply =3D <&supply_5V>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + channel@0 { + reg =3D <0>; + adi,gain-milli =3D /bits/ 16 <300>; + }; + + channel@2 { + reg =3D <2>; + adi,gain-milli =3D /bits/ 16 <600>; + }; + + channel@3 { + reg =3D <3>; + adi,gain-milli =3D /bits/ 16 <1000>; + }; + }; + }; --=20 2.47.0 From nobody Mon Nov 25 21:57:39 2024 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C2D3189BB3 for ; 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[2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0b93d53sm10828922f8f.70.2024.10.24.01.17.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2024 01:17:23 -0700 (PDT) From: Julien Stephan Date: Thu, 24 Oct 2024 10:16:57 +0200 Subject: [PATCH v3 2/4] iio: adc: ad7380: fix oversampling formula Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241024-ad7380-add-adaq4380-4-support-v3-2-6a29bd0f79da@baylibre.com> References: <20241024-ad7380-add-adaq4380-4-support-v3-0-6a29bd0f79da@baylibre.com> In-Reply-To: <20241024-ad7380-add-adaq4380-4-support-v3-0-6a29bd0f79da@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.14.2 The formula in the datasheet for oversampling time conversion seems to be valid when device is at full speed using the maximum number of SDO lines. The driver currently support only 1 SDO line. The formula will produce larger delays than what is currently set, but some devices actually require it. Signed-off-by: Julien Stephan --- drivers/iio/adc/ad7380.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index fb728570debe6432d5f991595cb35e9e7af8b740..d57e17f38925da5fb7c8a0a2320= a21474ba04b37 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -77,6 +77,12 @@ #define T_CONVERT_X_NS 500 /* xth conversion start time (oversampling) */ #define T_POWERUP_US 5000 /* Power up */ =20 +/* + * AD738x support several SDO lines to increase throughput, but driver cur= rently + * supports only 1 SDO line (standard SPI transaction) + */ +#define AD7380_NUM_SDO_LINES 1 + struct ad7380_timing_specs { const unsigned int t_csh_ns; /* CS minimum high time */ }; @@ -649,7 +655,8 @@ static int ad7380_set_ch(struct ad7380_state *st, unsig= ned int ch) =20 if (st->oversampling_ratio > 1) xfer.delay.value =3D T_CONVERT_0_NS + - T_CONVERT_X_NS * (st->oversampling_ratio - 1); + T_CONVERT_X_NS * (st->oversampling_ratio - 1) * + st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES; =20 return spi_sync_transfer(st->spi, &xfer, 1); } @@ -667,12 +674,13 @@ static void ad7380_update_xfers(struct ad7380_state *= st, =20 /* * In the case of oversampling, conversion time is higher than in normal - * mode. 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[2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0b93d53sm10828922f8f.70.2024.10.24.01.17.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2024 01:17:25 -0700 (PDT) From: Julien Stephan Date: Thu, 24 Oct 2024 10:16:58 +0200 Subject: [PATCH v3 3/4] iio: adc: ad7380: add support for adaq4370-4 and adaq4380-4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241024-ad7380-add-adaq4380-4-support-v3-3-6a29bd0f79da@baylibre.com> References: <20241024-ad7380-add-adaq4380-4-support-v3-0-6a29bd0f79da@baylibre.com> In-Reply-To: <20241024-ad7380-add-adaq4380-4-support-v3-0-6a29bd0f79da@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.14.2 adaq4370-4 (2MSPS) and adaq4380-4 (4MSPS) are quad-channel precision data acquisition signal chain =CE=BCModule solutions compatible with the ad738x family, with the following differences: - pin selectable gain in front of each 4 adc - internal reference is 3V derived from refin-supply (5V) - additional supplies This implies that IIO_CHAN_INFO_SCALE can not be shared by type. Signed-off-by: Julien Stephan --- drivers/iio/adc/ad7380.c | 130 +++++++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 126 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index d57e17f38925da5fb7c8a0a2320a21474ba04b37..f36dc27b8f9da7ebc7551193b5d= 847f7e8bef396 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -13,6 +13,8 @@ * ad7381-4 : https://www.analog.com/media/en/technical-documentation/data= -sheets/ad7381-4.pdf * ad7383/4-4 : https://www.analog.com/media/en/technical-documentation/da= ta-sheets/ad7383-4-ad7384-4.pdf * ad7386/7/8-4 : https://www.analog.com/media/en/technical-documentation/= data-sheets/ad7386-4-7387-4-7388-4.pdf + * adaq4370-4 : https://www.analog.com/media/en/technical-documentation/da= ta-sheets/adaq4370-4.pdf + * adaq4380-4 : https://www.analog.com/media/en/technical-documentation/da= ta-sheets/adaq4380-4.pdf */ =20 #include @@ -22,11 +24,14 @@ #include #include #include +#include #include #include #include #include #include +#include +#include =20 #include #include @@ -36,6 +41,8 @@ #define MAX_NUM_CHANNELS 8 /* 2.5V internal reference voltage */ #define AD7380_INTERNAL_REF_MV 2500 +/* 3.3V internal reference voltage for ADAQ */ +#define ADAQ4380_INTERNAL_REF_MV 3300 =20 /* reading and writing registers is more reliable at lower than max speed = */ #define AD7380_REG_WR_SPEED_HZ 10000000 @@ -82,6 +89,7 @@ * supports only 1 SDO line (standard SPI transaction) */ #define AD7380_NUM_SDO_LINES 1 +#define AD7380_DEFAULT_GAIN_MILLI 1000 =20 struct ad7380_timing_specs { const unsigned int t_csh_ns; /* CS minimum high time */ @@ -92,10 +100,12 @@ struct ad7380_chip_info { const struct iio_chan_spec *channels; unsigned int num_channels; unsigned int num_simult_channels; + bool has_hardware_gain; bool has_mux; const char * const *supplies; unsigned int num_supplies; bool external_ref_only; + bool adaq_internal_ref_only; const char * const *vcm_supplies; unsigned int num_vcm_supplies; const unsigned long *available_scan_masks; @@ -187,11 +197,12 @@ static const struct iio_scan_type ad7380_scan_type_16= _u[] =3D { }, }; =20 -#define AD7380_CHANNEL(index, bits, diff, sign) { \ +#define _AD7380_CHANNEL(index, bits, diff, sign, gain) { \ .type =3D IIO_VOLTAGE, \ .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + ((gain) ? BIT(IIO_CHAN_INFO_SCALE) : 0) | \ ((diff) ? 0 : BIT(IIO_CHAN_INFO_OFFSET)), \ - .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE) | \ + .info_mask_shared_by_type =3D ((gain) ? 0 : BIT(IIO_CHAN_INFO_SCALE)) | \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .info_mask_shared_by_type_available =3D \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ @@ -205,6 +216,12 @@ static const struct iio_scan_type ad7380_scan_type_16_= u[] =3D { .num_ext_scan_type =3D ARRAY_SIZE(ad7380_scan_type_##bits##_##sign), \ } =20 +#define AD7380_CHANNEL(index, bits, diff, sign) \ + _AD7380_CHANNEL(index, bits, diff, sign, false) + +#define ADAQ4380_CHANNEL(index, bits, diff, sign) \ + _AD7380_CHANNEL(index, bits, diff, sign, true) + #define DEFINE_AD7380_2_CHANNEL(name, bits, diff, sign) \ static const struct iio_chan_spec name[] =3D { \ AD7380_CHANNEL(0, bits, diff, sign), \ @@ -221,6 +238,15 @@ static const struct iio_chan_spec name[] =3D { \ IIO_CHAN_SOFT_TIMESTAMP(4), \ } =20 +#define DEFINE_ADAQ4380_4_CHANNEL(name, bits, diff, sign) \ +static const struct iio_chan_spec name[] =3D { \ + ADAQ4380_CHANNEL(0, bits, diff, sign), \ + ADAQ4380_CHANNEL(1, bits, diff, sign), \ + ADAQ4380_CHANNEL(2, bits, diff, sign), \ + ADAQ4380_CHANNEL(3, bits, diff, sign), \ + IIO_CHAN_SOFT_TIMESTAMP(4), \ +} + #define DEFINE_AD7380_8_CHANNEL(name, bits, diff, sign) \ static const struct iio_chan_spec name[] =3D { \ AD7380_CHANNEL(0, bits, diff, sign), \ @@ -239,6 +265,7 @@ DEFINE_AD7380_2_CHANNEL(ad7380_channels, 16, 1, s); DEFINE_AD7380_2_CHANNEL(ad7381_channels, 14, 1, s); DEFINE_AD7380_4_CHANNEL(ad7380_4_channels, 16, 1, s); DEFINE_AD7380_4_CHANNEL(ad7381_4_channels, 14, 1, s); +DEFINE_ADAQ4380_4_CHANNEL(adaq4380_4_channels, 16, 1, s); /* pseudo differential */ DEFINE_AD7380_2_CHANNEL(ad7383_channels, 16, 0, s); DEFINE_AD7380_2_CHANNEL(ad7384_channels, 14, 0, s); @@ -257,6 +284,10 @@ static const char * const ad7380_supplies[] =3D { "vcc", "vlogic", }; =20 +static const char * const adaq4380_supplies[] =3D { + "ldo", "vcc", "vlogic", "vs-p", "vs-n", "refin", +}; + static const char * const ad7380_2_channel_vcm_supplies[] =3D { "aina", "ainb", }; @@ -347,6 +378,11 @@ static const int ad7380_oversampling_ratios[] =3D { 1, 2, 4, 8, 16, 32, }; =20 +/* Gains stored as fractions of 1000 so they can be expressed by integers.= */ +static const int ad7380_gains[] =3D { + 300, 600, 1000, 1600, +}; + static const struct ad7380_chip_info ad7380_chip_info =3D { .name =3D "ad7380", .channels =3D ad7380_channels, @@ -516,6 +552,32 @@ static const struct ad7380_chip_info ad7388_4_chip_inf= o =3D { .timing_specs =3D &ad7380_4_timing, }; =20 +static const struct ad7380_chip_info adaq4370_4_chip_info =3D { + .name =3D "adaq4370-4", + .channels =3D adaq4380_4_channels, + .num_channels =3D ARRAY_SIZE(adaq4380_4_channels), + .num_simult_channels =3D 4, + .supplies =3D adaq4380_supplies, + .num_supplies =3D ARRAY_SIZE(adaq4380_supplies), + .adaq_internal_ref_only =3D true, + .has_hardware_gain =3D true, + .available_scan_masks =3D ad7380_4_channel_scan_masks, + .timing_specs =3D &ad7380_4_timing, +}; + +static const struct ad7380_chip_info adaq4380_4_chip_info =3D { + .name =3D "adaq4380-4", + .channels =3D adaq4380_4_channels, + .num_channels =3D ARRAY_SIZE(adaq4380_4_channels), + .num_simult_channels =3D 4, + .supplies =3D adaq4380_supplies, + .num_supplies =3D ARRAY_SIZE(adaq4380_supplies), + .adaq_internal_ref_only =3D true, + .has_hardware_gain =3D true, + .available_scan_masks =3D ad7380_4_channel_scan_masks, + .timing_specs =3D &ad7380_4_timing, +}; + struct ad7380_state { const struct ad7380_chip_info *chip_info; struct spi_device *spi; @@ -526,6 +588,7 @@ struct ad7380_state { bool seq; unsigned int vref_mv; unsigned int vcm_mv[MAX_NUM_CHANNELS]; + unsigned int gain_milli[MAX_NUM_CHANNELS]; /* xfers, message an buffer for reading sample data */ struct spi_transfer normal_xfer[2]; struct spi_message normal_msg; @@ -876,8 +939,15 @@ static int ad7380_read_raw(struct iio_dev *indio_dev, * * (2 =C3=97 VREF) / 2^N, for differential chips * * VREF / 2^N, for pseudo-differential chips * where N is the ADC resolution (i.e realbits) + * + * The gain is stored as a fraction of 1000 and, as we need to + * divide vref_mv by the gain, we invert the gain/1000 fraction. */ - *val =3D st->vref_mv; + if (st->chip_info->has_hardware_gain) + *val =3D mult_frac(st->vref_mv, MILLI, + st->gain_milli[chan->scan_index]); + else + *val =3D st->vref_mv; *val2 =3D scan_type->realbits - chan->differential; =20 return IIO_VAL_FRACTIONAL_LOG2; @@ -1058,7 +1128,19 @@ static int ad7380_probe(struct spi_device *spi) "Failed to enable power supplies\n"); fsleep(T_POWERUP_US); =20 - if (st->chip_info->external_ref_only) { + if (st->chip_info->adaq_internal_ref_only) { + /* + * ADAQ chips use fixed internal reference but still + * require a specific reference supply to power it. + * "refin" is already enabled with other power supplies + * in bulk_get_enable(). + */ + + st->vref_mv =3D ADAQ4380_INTERNAL_REF_MV; + + /* these chips don't have a register bit for this */ + external_ref_en =3D false; + } else if (st->chip_info->external_ref_only) { ret =3D devm_regulator_get_enable_read_voltage(&spi->dev, "refin"); if (ret < 0) @@ -1104,6 +1186,42 @@ static int ad7380_probe(struct spi_device *spi) st->vcm_mv[i] =3D ret / 1000; } =20 + for (i =3D 0; i < MAX_NUM_CHANNELS; i++) + st->gain_milli[i] =3D AD7380_DEFAULT_GAIN_MILLI; + + if (st->chip_info->has_hardware_gain) { + device_for_each_child_node_scoped(&spi->dev, node) { + unsigned int channel, gain; + int gain_idx; + + ret =3D fwnode_property_read_u32(node, "reg", &channel); + if (ret) + return dev_err_probe(&spi->dev, ret, + "Failed to read reg property\n"); + + if (channel >=3D st->chip_info->num_channels - 1) + return dev_err_probe(&spi->dev, -EINVAL, + "Invalid channel number %i\n", + channel); + + ret =3D fwnode_property_read_u32(node, "adi,gain-milli", + &gain); + if (ret && ret !=3D -EINVAL) + return dev_err_probe(&spi->dev, ret, + "Failed to read gain for channel %i\n", + channel); + if (ret !=3D -EINVAL) { + /* + * Match gain value from dt to one of supported + * gains + */ + gain_idx =3D find_closest(gain, ad7380_gains, + ARRAY_SIZE(ad7380_gains)); + st->gain_milli[channel] =3D ad7380_gains[gain_idx]; + } + } + } + st->regmap =3D devm_regmap_init(&spi->dev, NULL, st, &ad7380_regmap_confi= g); if (IS_ERR(st->regmap)) return dev_err_probe(&spi->dev, PTR_ERR(st->regmap), @@ -1186,6 +1304,8 @@ static const struct of_device_id ad7380_of_match_tabl= e[] =3D { { .compatible =3D "adi,ad7386-4", .data =3D &ad7386_4_chip_info }, { .compatible =3D "adi,ad7387-4", .data =3D &ad7387_4_chip_info }, { .compatible =3D "adi,ad7388-4", .data =3D &ad7388_4_chip_info }, + { .compatible =3D "adi,adaq4370-4", .data =3D &adaq4370_4_chip_info }, + { .compatible =3D "adi,adaq4380-4", .data =3D &adaq4380_4_chip_info }, { } }; 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[2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0b93d53sm10828922f8f.70.2024.10.24.01.17.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2024 01:17:26 -0700 (PDT) From: Julien Stephan Date: Thu, 24 Oct 2024 10:16:59 +0200 Subject: [PATCH v3 4/4] docs: iio: ad7380: add adaq4370-4 and adaq4380-4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241024-ad7380-add-adaq4380-4-support-v3-4-6a29bd0f79da@baylibre.com> References: <20241024-ad7380-add-adaq4380-4-support-v3-0-6a29bd0f79da@baylibre.com> In-Reply-To: <20241024-ad7380-add-adaq4380-4-support-v3-0-6a29bd0f79da@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.14.2 Adding documentation for adaq4370-4 and adaq4380-4 supported devices. In particular, document the reference voltage mechanism and the gain parameter that are specific to adaq devices. Signed-off-by: Julien Stephan --- Documentation/iio/ad7380.rst | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/iio/ad7380.rst b/Documentation/iio/ad7380.rst index 6f70b49b9ef27c1ac32acaefecd1146e5c8bd6cc..ae408ff2fa9c97427a9fef57020= fb54203d2d33e 100644 --- a/Documentation/iio/ad7380.rst +++ b/Documentation/iio/ad7380.rst @@ -27,6 +27,8 @@ The following chips are supported by this driver: * `AD7386-4 `_ * `AD7387-4 `_ * `AD7388-4 `_ +* `ADAQ4370-4 `_ +* `ADAQ4380-4 `_ =20 =20 Supported features @@ -47,6 +49,12 @@ ad7380-4 ad7380-4 supports only an external reference voltage (2.5V to 3.3V). It mu= st be declared in the device tree as ``refin-supply``. =20 +adaq devices +~~~~~~~~~~~~ + +adaq4370-4 and adaq4380-4 don't have an external reference, but use a 3V +internal reference derived from one of its supplies (``refin-supply``) + All other devices from ad738x family ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ =20 @@ -121,6 +129,16 @@ Example for AD7386/7/8 (2 channels parts): =20 When enabling sequencer mode, the effective sampling rate is divided by tw= o. =20 + +Gain (adaq devices only) +~~~~~~~~~~~~~~~~~~~~~~~~ + +adaq devices have a pin selectable gain in front of each adc. The appropri= ate +gain is selectable from device tree using the ``adi,gain-milli`` property. +Refer to the typical connection diagrams section of the datasheet for pin +wiring. + + Unimplemented features ---------------------- =20 --=20 2.47.0