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[93.34.91.161]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-37ee0ba7dffsm9249993f8f.116.2024.10.23.09.20.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2024 09:20:38 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Matthias Brugger , AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next RFC PATCH v2 1/3] dt-bindings: net: dsa: Add Airoha AN8855 Gigabit Switch documentation Date: Wed, 23 Oct 2024 18:19:50 +0200 Message-ID: <20241023161958.12056-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241023161958.12056-1-ansuelsmth@gmail.com> References: <20241023161958.12056-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Airoha AN8855 5 port Gigabit Switch documentation. The switch node requires an additional mdio node to describe each internal PHY relative offset as the PHY address for the switch match the one for the PHY ports. On top of internal PHY address, the switch base PHY address is added. Also the switch base PHY address can be configured and changed after the first initialization. On reset, the switch PHY address is ALWAYS 1. This can be configured with the use of "airoha,base_smi_address". Calibration values might be stored in switch EFUSE and internal PHY might need to be calibrated, in such case, airoha,ext_surge needs to be enabled and relative NVMEM cells needs to be defined in nvmem-layout node. Signed-off-by: Christian Marangi --- .../bindings/net/dsa/airoha,an8855.yaml | 253 ++++++++++++++++++ 1 file changed, 253 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/dsa/airoha,an8855= .yaml diff --git a/Documentation/devicetree/bindings/net/dsa/airoha,an8855.yaml b= /Documentation/devicetree/bindings/net/dsa/airoha,an8855.yaml new file mode 100644 index 000000000000..5982b4c39536 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/airoha,an8855.yaml @@ -0,0 +1,253 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dsa/airoha,an8855.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN8855 Gigabit switch + +maintainers: + - Christian Marangi + +description: + Airoha AN8855 is a 5-port Gigabit Switch. + + The switch node requires an additional mdio node to describe each intern= al + PHY relative offset as the PHY address for the switch match the one for + the PHY ports. On top of internal PHY address, the switch base PHY addre= ss + is added. + + Also the switch base PHY address can be configured and changed after the + first initialization. On reset, the switch PHY address is ALWAYS 1. + +properties: + compatible: + const: airoha,an8855 + + reg: + maxItems: 1 + + reset-gpios: + description: + GPIO to be used to reset the whole device + maxItems: 1 + + airoha,base_smi_address: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Configure and change the base switch PHY address to a new address on + the bus. + On reset, the switch PHY address is ALWAYS 1. + default: 1 + maximum: 31 + + airoha,ext_surge: + $ref: /schemas/types.yaml#/definitions/flag + description: + Calibrate the internal PHY with the calibration values stored in EFU= SE + for the r50Ohm values. + + '#nvmem-cell-cells': + const: 0 + + nvmem-layout: + $ref: /schemas/nvmem/layouts/nvmem-layout.yaml + description: + NVMEM Layout for exposed EFUSE. (for example to propagate calibration + value for r50Ohm for internal PHYs) + + mdio: + $ref: /schemas/net/mdio.yaml# + unevaluatedProperties: false + description: + Define the relative address of the internal PHY for each port. + + Each reg for the PHY is relative to the switch base PHY address. + +$ref: dsa.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + switch@1 { + compatible =3D "airoha,an8855"; + reg =3D <1>; + reset-gpios =3D <&pio 39 0>; + + airoha,ext_surge; + + #nvmem-cell-cells =3D <0>; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + shift_sel_port0_tx_a: shift-sel-port0-tx-a@c { + reg =3D <0xc 0x4>; + }; + + shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 { + reg =3D <0x10 0x4>; + }; + + shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 { + reg =3D <0x14 0x4>; + }; + + shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 { + reg =3D <0x18 0x4>; + }; + + shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c { + reg =3D <0x1c 0x4>; + }; + + shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 { + reg =3D <0x20 0x4>; + }; + + shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 { + reg =3D <0x24 0x4>; + }; + + shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 { + reg =3D <0x28 0x4>; + }; + + shift_sel_port2_tx_a: shift-sel-port2-tx-a@2c { + reg =3D <0x2c 0x4>; + }; + + shift_sel_port2_tx_b: shift-sel-port2-tx-b@30 { + reg =3D <0x30 0x4>; + }; + + shift_sel_port2_tx_c: shift-sel-port2-tx-c@34 { + reg =3D <0x34 0x4>; + }; + + shift_sel_port2_tx_d: shift-sel-port2-tx-d@38 { + reg =3D <0x38 0x4>; + }; + + shift_sel_port3_tx_a: shift-sel-port3-tx-a@4c { + reg =3D <0x4c 0x4>; + }; + + shift_sel_port3_tx_b: shift-sel-port3-tx-b@50 { + reg =3D <0x50 0x4>; + }; + + shift_sel_port3_tx_c: shift-sel-port3-tx-c@54 { + reg =3D <0x54 0x4>; + }; + + shift_sel_port3_tx_d: shift-sel-port3-tx-d@58 { + reg =3D <0x58 0x4>; + }; + }; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + label =3D "lan1"; + phy-mode =3D "internal"; + phy-handle =3D <&internal_phy0>; + }; + + port@1 { + reg =3D <1>; + label =3D "lan2"; + phy-mode =3D "internal"; + phy-handle =3D <&internal_phy1>; + }; + + port@2 { + reg =3D <2>; + label =3D "lan3"; + phy-mode =3D "internal"; + phy-handle =3D <&internal_phy2>; + }; + + port@3 { + reg =3D <3>; + label =3D "lan4"; + phy-mode =3D "internal"; + phy-handle =3D <&internal_phy3>; + }; + + port@5 { + reg =3D <5>; + label =3D "cpu"; + ethernet =3D <&gmac0>; + phy-mode =3D "2500base-x"; + + fixed-link { + speed =3D <2500>; + full-duplex; + pause; + }; + }; + }; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + internal_phy0: phy@0 { + reg =3D <0>; + + nvmem-cells =3D <&shift_sel_port0_tx_a>, + <&shift_sel_port0_tx_b>, + <&shift_sel_port0_tx_c>, + <&shift_sel_port0_tx_d>; + nvmem-cell-names =3D "tx_a", "tx_b", "tx_c", "tx_d"; + }; + + internal_phy1: phy@1 { + reg =3D <1>; + + nvmem-cells =3D <&shift_sel_port1_tx_a>, + <&shift_sel_port1_tx_b>, + <&shift_sel_port1_tx_c>, + <&shift_sel_port1_tx_d>; + nvmem-cell-names =3D "tx_a", "tx_b", "tx_c", "tx_d"; + }; + + internal_phy2: phy@2 { + reg =3D <2>; + + nvmem-cells =3D <&shift_sel_port2_tx_a>, + <&shift_sel_port2_tx_b>, + <&shift_sel_port2_tx_c>, + <&shift_sel_port2_tx_d>; + nvmem-cell-names =3D "tx_a", "tx_b", "tx_c", "tx_d"; + }; + + internal_phy3: phy@3 { + reg =3D <3>; + + nvmem-cells =3D <&shift_sel_port3_tx_a>, + <&shift_sel_port3_tx_b>, + <&shift_sel_port3_tx_c>, + <&shift_sel_port3_tx_d>; + nvmem-cell-names =3D "tx_a", "tx_b", "tx_c", "tx_d"; + }; + }; + }; + }; --=20 2.45.2