From nobody Mon Nov 25 23:36:09 2024 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 989E34436E; Wed, 23 Oct 2024 16:19:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729700345; cv=none; b=higDzeVQu5Jd1dWxyORyXb9RiC9BTDCp/5GWBVCcJYg+cNf6zuwEVi9gLsSXoI1b0346Gd2emMEyVM8V7cP0ZBOMGdIO4zLfiibHgCtgmthZ074DQQFgGpDet8Tg3xgYV/uPYmZbtU3rMRmwvEfLnkqK6HiMfelVk2r0zCnvVCw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729700345; c=relaxed/simple; bh=J570N3NOgV7gHgf7qjqKBVTohRJXUBY3jwyIVrc8ly8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KjFOg4A2RiSZ79cxJ98mslvY5YoMx03cl6vhMtKlzHyP/zV92bLu6g2oei6RKlDXLDsK8/O66C5wzlP/XGIxKFI4QbG/oS28z7VpCyHrHoSCE9K+TGr4haetLeC/Nu3YGyKM+dapOUUGBQeL7f9BPYQelspz581EWAY4G6AmL5o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=OaBTzsoe; arc=none smtp.client-ip=67.231.156.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="OaBTzsoe" Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49NBVaRS017659; Wed, 23 Oct 2024 09:18:54 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-type:date:from:in-reply-to:message-id:mime-version :references:subject:to; s=pfpt0220; bh=QpdXzjQvvXAC3RI2nHb+frWF5 EOIOck5EePEF3wL0pQ=; b=OaBTzsoeE6x/06RI1b7GFsAY+zHz9uuQRsuJ0ZTpd 7LNS9pWjCvqkogFL8g1XC7GIBC464vZNv74JHN7IQgcWSuyMFk5Vs3S+ybLX5AIl d99D0ilzkvFn9ke9eJdyxemtRy23PJIXT8o0gVwwDH/NQhjrIKcfK2Aj8Xhwc5N5 Y/Pyl9L/97JsDP4AiD4jdSlafDGFOANdH7gH/Tga/lGully/Lu4P7ElaBZFH68pY XY/wIyGL6+loFqDgSPAu0nc4Bh5+cNCHQ3RFlPrFMtrK7QsZ3QDub2gSAwUu232N 3FSyLgYvF4Jt0jENUc1VPp83FB2R+XfS2zbpPY9GSb2Rg== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 42em2c2bke-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 23 Oct 2024 09:18:53 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 23 Oct 2024 09:18:52 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 23 Oct 2024 09:18:52 -0700 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id 084673F706B; Wed, 23 Oct 2024 09:18:48 -0700 (PDT) From: Geetha sowjanya To: , CC: , , , , , , , , Subject: [net-next PATCH v4 1/4] octeontx2-pf: Define common API for HW resources configuration Date: Wed, 23 Oct 2024 21:48:40 +0530 Message-ID: <20241023161843.15543-2-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241023161843.15543-1-gakula@marvell.com> References: <20241023161843.15543-1-gakula@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: pxjmdRdt2bSjbwZWUCaRyOYK6UyzsyTw X-Proofpoint-ORIG-GUID: pxjmdRdt2bSjbwZWUCaRyOYK6UyzsyTw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define new API "otx2_init_rsrc" and move the HW blocks NIX/NPA resources configuration code under this API. So, that it can be used by the RVU representor driver that has similar resources of RVU NIC. Signed-off-by: Geetha sowjanya Reviewed-by: Jiri Pirko Reviewed-by: Simon Horman --- .../marvell/octeontx2/nic/otx2_common.h | 1 + .../ethernet/marvell/octeontx2/nic/otx2_pf.c | 145 ++++++++++-------- 2 files changed, 83 insertions(+), 63 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/dri= vers/net/ethernet/marvell/octeontx2/nic/otx2_common.h index f27a3456ae64..a47001a2b93f 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h @@ -996,6 +996,7 @@ int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, int stack_pages, int numptrs, int buf_size, int type); int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, int pool_id, int numptrs); +int otx2_init_rsrc(struct pci_dev *pdev, struct otx2_nic *pf); =20 /* RSS configuration APIs*/ int otx2_rss_init(struct otx2_nic *pfvf); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_pf.c index 5492dea547a1..180a16b42ac3 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c @@ -2872,6 +2872,87 @@ static void otx2_sriov_vfcfg_cleanup(struct otx2_nic= *pf) } } =20 +int otx2_init_rsrc(struct pci_dev *pdev, struct otx2_nic *pf) +{ + struct device *dev =3D &pdev->dev; + struct otx2_hw *hw =3D &pf->hw; + int num_vec, err; + + num_vec =3D pci_msix_vec_count(pdev); + hw->irq_name =3D devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, + GFP_KERNEL); + if (!hw->irq_name) + return -ENOMEM; + + hw->affinity_mask =3D devm_kcalloc(&hw->pdev->dev, num_vec, + sizeof(cpumask_var_t), GFP_KERNEL); + if (!hw->affinity_mask) + return -ENOMEM; + + /* Map CSRs */ + pf->reg_base =3D pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); + if (!pf->reg_base) { + dev_err(dev, "Unable to map physical function CSRs, aborting\n"); + return -ENOMEM; + } + + err =3D otx2_check_pf_usable(pf); + if (err) + return err; + + err =3D pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, + RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); + if (err < 0) { + dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", + __func__, num_vec); + return err; + } + + otx2_setup_dev_hw_settings(pf); + + /* Init PF <=3D> AF mailbox stuff */ + err =3D otx2_pfaf_mbox_init(pf); + if (err) + goto err_free_irq_vectors; + + /* Register mailbox interrupt */ + err =3D otx2_register_mbox_intr(pf, true); + if (err) + goto err_mbox_destroy; + + /* Request AF to attach NPA and NIX LFs to this PF. + * NIX and NPA LFs are needed for this PF to function as a NIC. + */ + err =3D otx2_attach_npa_nix(pf); + if (err) + goto err_disable_mbox_intr; + + err =3D otx2_realloc_msix_vectors(pf); + if (err) + goto err_detach_rsrc; + + err =3D cn10k_lmtst_init(pf); + if (err) + goto err_detach_rsrc; + + return 0; + +err_detach_rsrc: + if (pf->hw.lmt_info) + free_percpu(pf->hw.lmt_info); + if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) + qmem_free(pf->dev, pf->dync_lmt); + otx2_detach_resources(&pf->mbox); +err_disable_mbox_intr: + otx2_disable_mbox_intr(pf); +err_mbox_destroy: + otx2_pfaf_mbox_destroy(pf); +err_free_irq_vectors: + pci_free_irq_vectors(hw->pdev); + + return err; +} + static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct device *dev =3D &pdev->dev; @@ -2879,7 +2960,6 @@ static int otx2_probe(struct pci_dev *pdev, const str= uct pci_device_id *id) struct net_device *netdev; struct otx2_nic *pf; struct otx2_hw *hw; - int num_vec; =20 err =3D pcim_enable_device(pdev); if (err) { @@ -2930,72 +3010,14 @@ static int otx2_probe(struct pci_dev *pdev, const s= truct pci_device_id *id) /* Use CQE of 128 byte descriptor size by default */ hw->xqe_size =3D 128; =20 - num_vec =3D pci_msix_vec_count(pdev); - hw->irq_name =3D devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, - GFP_KERNEL); - if (!hw->irq_name) { - err =3D -ENOMEM; - goto err_free_netdev; - } - - hw->affinity_mask =3D devm_kcalloc(&hw->pdev->dev, num_vec, - sizeof(cpumask_var_t), GFP_KERNEL); - if (!hw->affinity_mask) { - err =3D -ENOMEM; - goto err_free_netdev; - } - - /* Map CSRs */ - pf->reg_base =3D pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); - if (!pf->reg_base) { - dev_err(dev, "Unable to map physical function CSRs, aborting\n"); - err =3D -ENOMEM; - goto err_free_netdev; - } - - err =3D otx2_check_pf_usable(pf); + err =3D otx2_init_rsrc(pdev, pf); if (err) goto err_free_netdev; =20 - err =3D pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, - RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); - if (err < 0) { - dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", - __func__, num_vec); - goto err_free_netdev; - } - - otx2_setup_dev_hw_settings(pf); - - /* Init PF <=3D> AF mailbox stuff */ - err =3D otx2_pfaf_mbox_init(pf); - if (err) - goto err_free_irq_vectors; - - /* Register mailbox interrupt */ - err =3D otx2_register_mbox_intr(pf, true); - if (err) - goto err_mbox_destroy; - - /* Request AF to attach NPA and NIX LFs to this PF. - * NIX and NPA LFs are needed for this PF to function as a NIC. - */ - err =3D otx2_attach_npa_nix(pf); - if (err) - goto err_disable_mbox_intr; - - err =3D otx2_realloc_msix_vectors(pf); - if (err) - goto err_detach_rsrc; - err =3D otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues); if (err) goto err_detach_rsrc; =20 - err =3D cn10k_lmtst_init(pf); - if (err) - goto err_detach_rsrc; - /* Assign default mac address */ otx2_get_mac_from_af(netdev); =20 @@ -3118,11 +3140,8 @@ static int otx2_probe(struct pci_dev *pdev, const st= ruct pci_device_id *id) if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) qmem_free(pf->dev, pf->dync_lmt); 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Date: Wed, 23 Oct 2024 21:48:41 +0530 Message-ID: <20241023161843.15543-3-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241023161843.15543-1-gakula@marvell.com> References: <20241023161843.15543-1-gakula@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: iL--c-gqc8DT0thGnlGE49L9ldAPlmfV X-Proofpoint-ORIG-GUID: iL--c-gqc8DT0thGnlGE49L9ldAPlmfV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Group the queue(RX/TX/CQ) memory allocation and free code to single APIs. Signed-off-by: Geetha sowjanya Reviewed-by: Pavan Chebbi Reviewed-by: Simon Horman --- .../marvell/octeontx2/nic/otx2_common.h | 2 + .../ethernet/marvell/octeontx2/nic/otx2_pf.c | 53 +++++++++++++------ 2 files changed, 39 insertions(+), 16 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/dri= vers/net/ethernet/marvell/octeontx2/nic/otx2_common.h index a47001a2b93f..df548aeffecf 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h @@ -997,6 +997,8 @@ int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, int pool_id, int numptrs); int otx2_init_rsrc(struct pci_dev *pdev, struct otx2_nic *pf); +void otx2_free_queue_mem(struct otx2_qset *qset); +int otx2_alloc_queue_mem(struct otx2_nic *pf); =20 /* RSS configuration APIs*/ int otx2_rss_init(struct otx2_nic *pfvf); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_pf.c index 180a16b42ac3..1185f1bdfa01 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c @@ -1770,15 +1770,23 @@ static void otx2_dim_work(struct work_struct *w) dim->state =3D DIM_START_MEASURE; } =20 -int otx2_open(struct net_device *netdev) +void otx2_free_queue_mem(struct otx2_qset *qset) +{ + kfree(qset->sq); + qset->sq =3D NULL; + kfree(qset->cq); + qset->cq =3D NULL; + kfree(qset->rq); + qset->rq =3D NULL; + kfree(qset->napi); + qset->napi =3D NULL; +} + +int otx2_alloc_queue_mem(struct otx2_nic *pf) { - struct otx2_nic *pf =3D netdev_priv(netdev); - struct otx2_cq_poll *cq_poll =3D NULL; struct otx2_qset *qset =3D &pf->qset; - int err =3D 0, qidx, vec; - char *irq_name; + struct otx2_cq_poll *cq_poll; =20 - netif_carrier_off(netdev); =20 /* RQ and SQs are mapped to different CQs, * so find out max CQ IRQs (i.e CINTs) needed. @@ -1798,7 +1806,6 @@ int otx2_open(struct net_device *netdev) /* CQ size of SQ */ qset->sqe_cnt =3D qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K); =20 - err =3D -ENOMEM; qset->cq =3D kcalloc(pf->qset.cq_cnt, sizeof(struct otx2_cq_queue), GFP_KERNEL); if (!qset->cq) @@ -1814,6 +1821,27 @@ int otx2_open(struct net_device *netdev) if (!qset->rq) goto err_free_mem; =20 + return 0; + +err_free_mem: + otx2_free_queue_mem(qset); + return -ENOMEM; +} + +int otx2_open(struct net_device *netdev) +{ + struct otx2_nic *pf =3D netdev_priv(netdev); + struct otx2_cq_poll *cq_poll =3D NULL; + struct otx2_qset *qset =3D &pf->qset; + int err =3D 0, qidx, vec; + char *irq_name; + + netif_carrier_off(netdev); + + err =3D otx2_alloc_queue_mem(pf); + if (err) + return err; + err =3D otx2_init_hw_resources(pf); if (err) goto err_free_mem; @@ -1979,10 +2007,7 @@ int otx2_open(struct net_device *netdev) otx2_disable_napi(pf); otx2_free_hw_resources(pf); err_free_mem: - kfree(qset->sq); - kfree(qset->cq); - kfree(qset->rq); - kfree(qset->napi); + otx2_free_queue_mem(qset); return err; } EXPORT_SYMBOL(otx2_open); @@ -2047,11 +2072,7 @@ int otx2_stop(struct net_device *netdev) for (qidx =3D 0; qidx < netdev->num_tx_queues; qidx++) netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); =20 - - kfree(qset->sq); - kfree(qset->cq); - kfree(qset->rq); - kfree(qset->napi); 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charset="utf-8" Reuse the maximum support HW MTU value that is fetch during probe. Instead of fetching through mbox each time mtu is changed as the value is fixed for interface. Signed-off-by: Geetha sowjanya Reviewed-by: Simon Horman --- drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c | 4 ++-- drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h | 1 + drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c | 1 + drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c | 1 + 4 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c b/dri= vers/net/ethernet/marvell/octeontx2/nic/otx2_common.c index 87d5776e3b88..34e76cfd941b 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c @@ -227,7 +227,7 @@ int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu) u16 maxlen; int err; =20 - maxlen =3D otx2_get_max_mtu(pfvf) + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; + maxlen =3D pfvf->hw.max_mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; =20 mutex_lock(&pfvf->mbox.lock); req =3D otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox); @@ -236,7 +236,7 @@ int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu) return -ENOMEM; } =20 - req->maxlen =3D pfvf->netdev->mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; + req->maxlen =3D mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; =20 /* Use max receive length supported by hardware for loopback devices */ if (is_otx2_lbkvf(pfvf->pdev)) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/dri= vers/net/ethernet/marvell/octeontx2/nic/otx2_common.h index df548aeffecf..b36b87dae2cb 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h @@ -228,6 +228,7 @@ struct otx2_hw { u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; u16 matchall_ipolicer; u32 dwrr_mtu; + u32 max_mtu; u8 smq_link_type; =20 /* HW settings, coalescing etc */ diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_pf.c index 1185f1bdfa01..15ed1305fbf8 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c @@ -3101,6 +3101,7 @@ static int otx2_probe(struct pci_dev *pdev, const str= uct pci_device_id *id) =20 netdev->min_mtu =3D OTX2_MIN_MTU; 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Wed, 23 Oct 2024 09:19:05 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 23 Oct 2024 09:19:04 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 23 Oct 2024 09:19:04 -0700 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id B910C3F706B; Wed, 23 Oct 2024 09:19:00 -0700 (PDT) From: Geetha sowjanya To: , CC: , , , , , , , , Subject: [net-next PATCH v4 4/4] octeontx2-pf: Move shared APIs to header file Date: Wed, 23 Oct 2024 21:48:43 +0530 Message-ID: <20241023161843.15543-5-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241023161843.15543-1-gakula@marvell.com> References: <20241023161843.15543-1-gakula@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: LnoT46BWqbZRJWhK3r-Wg03aXrAHXoxw X-Proofpoint-ORIG-GUID: LnoT46BWqbZRJWhK3r-Wg03aXrAHXoxw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move mbox, hw resources and interrupt configuration functions to common header file. So, that they can be used later by the RVU representor driver. Signed-off-by: Geetha sowjanya Reviewed-by: Simon Horman --- .../marvell/octeontx2/nic/otx2_common.h | 11 ++++++++ .../ethernet/marvell/octeontx2/nic/otx2_pf.c | 27 ++++++++++--------- .../ethernet/marvell/octeontx2/nic/otx2_vf.c | 4 +-- 3 files changed, 28 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/dri= vers/net/ethernet/marvell/octeontx2/nic/otx2_common.h index b36b87dae2cb..327254e578d5 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h @@ -1000,6 +1000,17 @@ int otx2_aura_init(struct otx2_nic *pfvf, int aura_i= d, int otx2_init_rsrc(struct pci_dev *pdev, struct otx2_nic *pf); void otx2_free_queue_mem(struct otx2_qset *qset); int otx2_alloc_queue_mem(struct otx2_nic *pf); +int otx2_init_hw_resources(struct otx2_nic *pfvf); +void otx2_free_hw_resources(struct otx2_nic *pf); +int otx2_wq_init(struct otx2_nic *pf); +int otx2_check_pf_usable(struct otx2_nic *pf); +int otx2_pfaf_mbox_init(struct otx2_nic *pf); +int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af); +int otx2_realloc_msix_vectors(struct otx2_nic *pf); +void otx2_pfaf_mbox_destroy(struct otx2_nic *pf); +void otx2_disable_mbox_intr(struct otx2_nic *pf); +void otx2_disable_napi(struct otx2_nic *pf); +irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq); =20 /* RSS configuration APIs*/ int otx2_rss_init(struct otx2_nic *pfvf); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_pf.c index 15ed1305fbf8..e6b03bad2dba 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c @@ -1008,7 +1008,7 @@ static irqreturn_t otx2_pfaf_mbox_intr_handler(int ir= q, void *pf_irq) return IRQ_HANDLED; } =20 -static void otx2_disable_mbox_intr(struct otx2_nic *pf) +void otx2_disable_mbox_intr(struct otx2_nic *pf) { int vector =3D pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX); =20 @@ -1017,7 +1017,7 @@ static void otx2_disable_mbox_intr(struct otx2_nic *p= f) free_irq(vector, pf); } =20 -static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) +int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) { struct otx2_hw *hw =3D &pf->hw; struct msg_req *req; @@ -1061,7 +1061,7 @@ static int otx2_register_mbox_intr(struct otx2_nic *p= f, bool probe_af) return 0; } =20 -static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) +void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) { struct mbox *mbox =3D &pf->mbox; =20 @@ -1077,7 +1077,7 @@ static void otx2_pfaf_mbox_destroy(struct otx2_nic *p= f) otx2_mbox_destroy(&mbox->mbox_up); } =20 -static int otx2_pfaf_mbox_init(struct otx2_nic *pf) +int otx2_pfaf_mbox_init(struct otx2_nic *pf) { struct mbox *mbox =3D &pf->mbox; void __iomem *hwbase; @@ -1379,7 +1379,7 @@ static irqreturn_t otx2_q_intr_handler(int irq, void = *data) return IRQ_HANDLED; } =20 -static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) +irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) { struct otx2_cq_poll *cq_poll =3D (struct otx2_cq_poll *)cq_irq; struct otx2_nic *pf =3D (struct otx2_nic *)cq_poll->dev; @@ -1399,15 +1399,18 @@ static irqreturn_t otx2_cq_intr_handler(int irq, vo= id *cq_irq) return IRQ_HANDLED; } =20 -static void otx2_disable_napi(struct otx2_nic *pf) +void otx2_disable_napi(struct otx2_nic *pf) { struct otx2_qset *qset =3D &pf->qset; struct otx2_cq_poll *cq_poll; + struct work_struct *work; int qidx; =20 for (qidx =3D 0; qidx < pf->hw.cint_cnt; qidx++) { cq_poll =3D &qset->napi[qidx]; - cancel_work_sync(&cq_poll->dim.work); + work =3D &cq_poll->dim.work; + if (work->func) + cancel_work_sync(work); napi_disable(&cq_poll->napi); netif_napi_del(&cq_poll->napi); } @@ -1477,7 +1480,7 @@ static int otx2_get_rbuf_size(struct otx2_nic *pf, in= t mtu) return ALIGN(rbuf_size, 2048); } =20 -static int otx2_init_hw_resources(struct otx2_nic *pf) +int otx2_init_hw_resources(struct otx2_nic *pf) { struct nix_lf_free_req *free_req; struct mbox *mbox =3D &pf->mbox; @@ -1602,7 +1605,7 @@ static int otx2_init_hw_resources(struct otx2_nic *pf) return err; } =20 -static void otx2_free_hw_resources(struct otx2_nic *pf) +void otx2_free_hw_resources(struct otx2_nic *pf) { struct otx2_qset *qset =3D &pf->qset; struct nix_lf_free_req *free_req; @@ -2807,7 +2810,7 @@ static const struct net_device_ops otx2_netdev_ops = =3D { .ndo_set_vf_trust =3D otx2_ndo_set_vf_trust, }; =20 -static int otx2_wq_init(struct otx2_nic *pf) +int otx2_wq_init(struct otx2_nic *pf) { pf->otx2_wq =3D create_singlethread_workqueue("otx2_wq"); if (!pf->otx2_wq) @@ -2818,7 +2821,7 @@ static int otx2_wq_init(struct otx2_nic *pf) return 0; } =20 -static int otx2_check_pf_usable(struct otx2_nic *nic) +int otx2_check_pf_usable(struct otx2_nic *nic) { u64 rev; =20 @@ -2836,7 +2839,7 @@ static int otx2_check_pf_usable(struct otx2_nic *nic) return 0; } =20 -static int otx2_realloc_msix_vectors(struct otx2_nic *pf) +int otx2_realloc_msix_vectors(struct otx2_nic *pf) { struct otx2_hw *hw =3D &pf->hw; int num_vec, err; diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_vf.c index 79a8acac6283..c4e6c78a8deb 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c @@ -500,7 +500,7 @@ static const struct net_device_ops otx2vf_netdev_ops = =3D { .ndo_setup_tc =3D otx2_setup_tc, }; =20 -static int otx2_wq_init(struct otx2_nic *vf) +static int otx2_vf_wq_init(struct otx2_nic *vf) { vf->otx2_wq =3D create_singlethread_workqueue("otx2vf_wq"); if (!vf->otx2_wq) @@ -689,7 +689,7 @@ static int otx2vf_probe(struct pci_dev *pdev, const str= uct pci_device_id *id) goto err_ptp_destroy; } =20 - err =3D otx2_wq_init(vf); + err =3D otx2_vf_wq_init(vf); if (err) goto err_unreg_netdev; =20 --=20 2.25.1